CN112202447A

CN112202447A - Novel digital-to-analog conversion structure

Info

Publication number: CN112202447A
Application number: CN202011037906.2A
Authority: CN
Inventors: 章彬; 李湘春; 胡锦; 徐兴; 蓝龙伟
Original assignee: Suzhou Ruidilian Electronic Technology Co ltd
Current assignee: Suzhou Ruidilian Electronic Technology Co ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2021-01-08

Abstract

The embodiment of the application discloses novel digital-to-analog conversion structure, including a plurality of low weight devices and coding module, coding module includes high-order section submodule piece, low-order section submodule piece, high-order section submodule piece passes through the low weight device corresponds low-order section submodule piece constitutes. The novel digital-to-analog conversion structure is suitable for DAC conversion mechanisms of a current mode, a capacitance mode and a resistance mode, reduces the requirement of the area of the weight device mismatch pair, relaxes the layout requirement of each submodule, and has high INL integral nonlinear performance.

Description

Novel digital-to-analog conversion structure

Technical Field

The application relates to the technical field of digital-to-analog conversion circuits, in particular to a novel digital-to-analog conversion structure.

Background

Conventional DAC architectures are typically constructed with devices of different weights, such as capacitors, resistors, and the like. The structure is easy to generate mismatching when the low-weight device is switched to the high-weight device, so that the error performance of the DAC structure is poor. Therefore, a new digital-to-analog conversion structure is needed to solve this problem.

Disclosure of Invention

The application aims at solving the technical problem and provides a novel digital-to-analog conversion structure, mismatch generated by multiple weight device components is avoided, and DAC error performance is ensured.

In order to achieve the purpose, the application discloses a novel digital-to-analog conversion structure, which comprises a plurality of low-weight devices and an encoding module, wherein the encoding module comprises a high-level section submodule and a low-level section submodule, and the high-level section submodule corresponds to the low-level section submodule to form the novel digital-to-analog conversion structure.

Preferably, the high-order segment submodule includes a hot coded thermal code and a binary coded binary code.

Preferably, the low-order segment submodule includes a binary code and a complement code.

Preferably, the capacitor DAC layout of the novel digital-to-analog conversion structure comprises a plurality of conversion function capacitors and complementary capacitors arranged in the centers of the conversion function capacitors.

Has the advantages that: according to the novel digital-to-analog conversion structure, the binary code control code of each high-order section submodule and each low-order section submodule is [5:0] of DAC input [9:0], so that the change basis of the output voltage of the DAC is the unit capacitance change of LSB, the maximum DNL error occurs between the conversion of 100000 and 011111, and the requirement of mismatch area is greatly reduced. Meanwhile, each submodule completely completes unit capacitance control in sequence, and the requirement on submodule layout is relaxed. Through the layout design of the capacitor DAC, the INL integral nonlinear performance can be effectively improved, and the higher INL integral nonlinear performance can be obtained. On the other hand, the novel digital-to-analog conversion structure is suitable for DAC conversion mechanisms in a current mode, a capacitance mode and a resistance mode, and has a wide application range.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of a DAC layout in an embodiment of the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Example (b): a novel digital-to-analog conversion structure comprises a plurality of low-weight devices and an encoding module, wherein the encoding module comprises a high-level section submodule and a low-level section submodule, and the high-level section submodule is formed by the low-level section submodule corresponding to the low-weight devices.

In this embodiment, the high-order sub-module includes a hot coded thermal code and a binary coded binary code. The low-order segment submodule comprises a binary coding binary code and a complement coding code.

In this embodiment, the layout of the capacitor DAC with the novel digital-to-analog conversion structure includes a plurality of conversion function capacitors and a complementary capacitor disposed in the center of the plurality of conversion function capacitors.

The working principle is shown in fig. 1, taking the layout of the capacitor DAC with 10bit precision as an example:

firstly, as a 10-bit DAC, a control code of a capacitor array is divided into a high-order section and a low-order section, wherein the high-order section is a mixture of thermal code and binary code, and the low-order section is composed of binary code and complement code. It is assumed that the high-order bits have 4 bits and the low-order bits have 6 bits after the area and circuit complexity trade-off is considered.

a) As shown in part (a) of fig. 1, there is a complementary bit code 0' in addition to [5:0] controlled by the binary code. The effect of the code 0' is equivalent to the effect that after [6:0] = 0111111 and one LSB are changed to 1000000, the capacitance corresponding to the bit6 is controlled by the code 1. The novel digital-to-analog conversion structure does not convert the function of bit [6] to the corresponding capacitor array in the existing DAC structure, but realizes the function through the complement code 0', and in the embodiment, the capacitor array is a low-level sub-module.

b) As shown in part (B) of fig. 1, the capacitor array is composed of 16 low-stage sub-modules. The control bit of any one low-level segment submodule consists of a group of binary codes and a complement code, all the low-level segment submodules are completely the same, namely the functional action of any one low-level segment submodule is started from the minimum unit capacitance until all 64 unit capacitances are acted, and then the starting of the other low-level segment submodule is started. The starting of the 16 low-level sub-modules is controlled by the coding form of a hot coded thermal code, and the change needs to follow the following mode:

0000 0000 0000 0000

0000 0000 0000 0001

0000 0000 0000 0011

0000 0000 0000 0111

0000 0000 0000 1111

.

0011 1111 1111 1111

0111 1111 1111 1111

1111 1111 1111 1111。

c) when the thermal code = 0000000000000000, it indicates that only the capacitance of one low-order segment submodule is manipulated, for example, the low-order segment submodule whose coordinate is (4, 0) at this position. When the thermal code = 0000000000000001 is thermally encoded, 64 unit capacitances in the lower segment sub-module of the coordinate (4, 0) are all determined as the code "1". Under this condition, further conversion change occurs in the capacitor array of the lower sub-module of the coordinate (3, 0), and the control bits of the capacitors in the lower sub-modules of other coordinate positions are not moved. The sequential analogy to 0111111111111111 shows whether the complement code in the last low-order sub-module needs to be active or not, which depends on the DAC requirement.

The foregoing description is for the purpose of illustration and is not for the purpose of limitation. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for all purposes. The omission in the foregoing claims of any aspect of subject matter that is disclosed herein is not intended to forego the subject matter and should not be construed as an admission that the applicant does not consider such subject matter to be part of the disclosed subject matter.

Claims

1. The utility model provides a novel digital-to-analog conversion structure, its characterized in that includes a plurality of low weight devices and coding module, coding module includes high-order section submodule piece, low-order section submodule piece, high-order section submodule piece is through the low weight device corresponds low-order section submodule piece constitutes.

2. The new dac architecture of claim 1 wherein the high level segment submodules include a thermally coded thermal code and a binary coded binary code.

3. The new dac architecture of claim 2 wherein the low level segment submodules include binary code and complement code.

4. The new digital-to-analog conversion structure as claimed in any one of claims 1, 2 or 3, wherein the capacitor DAC layout of the new digital-to-analog conversion structure comprises a plurality of conversion function capacitors and a complementary capacitor disposed at the center of the plurality of conversion function capacitors.