CN112202446A - Phase synchronization device and method - Google Patents
Phase synchronization device and method Download PDFInfo
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- CN112202446A CN112202446A CN201910612126.7A CN201910612126A CN112202446A CN 112202446 A CN112202446 A CN 112202446A CN 201910612126 A CN201910612126 A CN 201910612126A CN 112202446 A CN112202446 A CN 112202446A
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- 238000000034 method Methods 0.000 title claims description 15
- 230000001413 cellular effect Effects 0.000 claims description 12
- 239000013078 crystal Substances 0.000 abstract description 10
- 230000000630 rising effect Effects 0.000 description 7
- 230000003111 delayed effect Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
Abstract
The device comprises a first trigger and a second trigger, wherein a receiving end of the first trigger is connected with a first signal source, a clock signal end of the first trigger is connected with a second signal source, a receiving end of the second trigger is connected with the first signal source, and a clock signal end of the second trigger is connected with the second signal source, so that on one hand, the condition that the system performance is reduced due to different phases of the two signals is avoided, and the working performance of the system is ensured; on the other hand, the square wave is additionally generated as a clock control signal without arranging components such as a crystal oscillator, a filter and the like, so that the purchase of the components is reduced, and the cost of signal processing is reduced.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a phase synchronization apparatus and method, an antenna array transmitter of a cellular network, an antenna array receiver of the cellular network, and a wireless multi-antenna-array electronic device.
Background
Radio communication devices need to generate stable operating frequencies for proper operation. Generally, the clock signal is generated by using a crystal oscillator, because the crystal oscillator only allows a signal with the same resonance frequency as the crystal oscillator to pass through, the crystal oscillator can generate a very precise frequency, the frequency depends on the size and the characteristics of the crystal, and the signal generated by the crystal oscillator is used as the clock signal.
In a time division duplex system, in order to reduce power consumption, a phase-locked loop needs to be closed when the phase-locked loop is not in work, and the phase-locked loop is opened when the phase-locked loop is in work, so that the frequency can be locked, the phase is stable after each time of switching, but the phase cannot be guaranteed to be the same every time, the phase difference is 180 degrees at random, the phase difference of two signals in a phased array or multi-antenna system can cause beam pointing deviation and gain reduction, the baseband data can be influenced to be out of synchronization, error codes and even high-order modulation and demodulation failures are caused, and the performance of the.
Disclosure of Invention
In view of the above, embodiments of the present application provide a phase synchronization apparatus and method, an antenna array transmitter of a cellular network, an antenna array receiver of a cellular network, and a wireless multi-antenna array electronic device, so as to solve the technical defects in the prior art.
The embodiment of the application provides a phase synchronization device, including first, two triggers, the receiving terminal and the first signal source of first trigger are connected, the clock signal end and the second signal source of first trigger are connected, the receiving terminal and the first signal source of second trigger are connected, the clock signal end and the second signal source of second trigger are connected.
The embodiment of the application also discloses a phase synchronization method, which comprises the following steps:
receiving a first signal and a second signal to be processed, wherein the first signal and the second signal are square wave signals with same frequency and different phases;
inputting the two first signals to signal receiving ends of a first trigger and a second trigger;
inputting the two second signals to clock signal ends of the first flip-flop and the second flip-flop;
the output ends of the first trigger and the second trigger respectively output a third signal and a fourth signal with the same frequency and phase.
The embodiment of the application also discloses an antenna array transmitter of a cellular network, which comprises the phase synchronization device.
The embodiment of the application also discloses an antenna array receiver of a cellular network, which comprises the phase synchronization device.
The embodiment of the application also discloses wireless multi-antenna array electronic equipment which comprises the phase synchronization device.
Compared with the prior art, the technical effect of this application does: the device carries out phase synchronization processing on two square wave signals with the same frequency and different phases, receiving ends of a first trigger and a second trigger receive a first signal output by a first signal source, clock signal ends of the first trigger and the second trigger receive a second signal output by a second signal source, the second signal is directly used as a clock control signal and is respectively input to the first trigger and the second trigger, and output ends of the first trigger and the second trigger respectively output signals with the same frequency and phase, so that on one hand, the condition that the system performance is reduced due to different phases of the two signals is avoided, and the phase synchronization among a plurality of pieces of equipment in a time division system is quickly realized; on the other hand, the square wave is additionally generated as a clock control signal without arranging components such as a crystal oscillator, a filter and the like, so that the purchase of the components is reduced, and the cost of signal processing is reduced.
Drawings
FIG. 1 is a schematic structural diagram of a phase synchronization apparatus according to the present application;
FIG. 2a is a schematic diagram of waveforms of first, second, third, and fourth signals in the present application;
FIG. 2b is a schematic diagram of the third and fourth waveforms for processing the first and second signal outputs in the present application;
FIG. 3 is a flowchart illustrating a phase synchronization method according to an embodiment of the present application;
fig. 4 is a flowchart illustrating a phase synchronization method according to another embodiment of the present application.
In reference numerals, 1 — a first signal source; 2-a second signal source; 11-a first flip-flop; 12-second flip-flop, 21-first delay; 22-a second delay; 31-a first buffer; 32-a second buffer; 40-frequency multiplier.
Detailed Description
The following description of specific embodiments of the present application refers to the accompanying drawings.
In this document, "upper", "lower", "front", "rear", "left", "right", and the like are used only to indicate relative positional relationships between relevant portions, and do not limit absolute positions of the relevant portions.
In this document, "first", "second", and the like are used only for distinguishing one from another, and do not indicate the degree and order of importance, the premise that each other exists, and the like.
In this context, "equal", "same", etc. are not strictly mathematical and/or geometric limitations, but also include tolerances as would be understood by a person skilled in the art and allowed for manufacturing or use, etc.
Unless otherwise indicated, numerical ranges herein include not only the entire range within its two endpoints, but also several sub-ranges subsumed therein.
Referring to fig. 1 and 2, a phase synchronization apparatus includes a first flip-flop 11 and a second flip-flop 12, where a receiving end of the first flip-flop 11 is connected to a first signal source 1, a clock signal end of the first flip-flop 11 is connected to a second signal source 2, a receiving end of the second flip-flop 12 is connected to the first signal source 1, and a clock signal end of the second flip-flop 12 is connected to the second signal source 2.
The first signal source 1 and the second signal source 2 respectively generate a first signal and a second signal, the first signal and the second signal are square wave signals with same frequency and different phase, namely, the device carries out phase synchronization processing on two square wave signals with same frequency and different phases, receives a first signal output by a first signal source 1 through receiving ends of a first trigger 11 and a second trigger 12, receives a second signal output by a second signal source 2 through clock signal ends of the first trigger 11 and the second trigger 12, and because the second signal is a square wave signal, namely the second signals are directly input as clock control signals to the first flip-flop 11 and the second flip-flop 12 respectively, the output ends of the first and second triggers 11 and 12 respectively output signals with the same frequency and phase, so that on one hand, the condition of system performance reduction caused by different phases of the two signals is avoided, and the phase synchronization among multiple pieces of equipment in a time division system is quickly realized; on the other hand, the square wave is additionally generated as a clock control signal without arranging components such as a crystal oscillator, a filter and the like, so that the purchase of the components is reduced, and the cost of signal processing is reduced.
The first and second flip- flops 11 and 12 are edge flip-flops, and the edge flip-flops implement the sub-states of the flip-flops only depending on the states of the input signals at the time when the falling edge or the rising edge of the clock pulse reaches, and are not related to the states of the input signals of the other flip-flops at the time. Therefore, the edge trigger greatly improves the reliability of work and enhances the anti-interference capability.
The phase synchronization device further comprises a first delayer 21 and a second delayer 22, wherein the output end of the first delayer 21 is connected with the receiving end of the first trigger 11, the output end of the second delayer 22 is connected with the receiving end of the second trigger 12, and the receiving ends of the first delayer 21 and the second delayer 22 are connected with the first signal source 1.
Through setting up first, two delayers 21, 22, first, two delayers 21, 22 carry out the time delay processing to two first signals respectively, the time that inputs two first signals to first, two flip- flops 11, 12 respectively staggers, prevents that the dead zone's condition from appearing in two first signal inputs to first, two flip- flops 11, 12, ensures that first signal and second signal can carry out phase synchronization steadily, improves the performance of system.
The receiving ends of the first and second delay units 21 and 22 are respectively connected to the signal output end of the first buffer 31, and the receiving end of the first buffer 31 is connected to the first signal source 1.
The first buffer 31 can amplify the first signal, which not only ensures the strength of the two paths of first signals output by the first buffer 31, but also ensures that the two first signals can be synchronously transmitted all the time.
The phase synchronization device further comprises a second buffer 32, the clock signal ends of the first and second flip- flops 11 and 12 are respectively connected with the signal output end of the second buffer 32, and the receiving end of the second buffer 32 is connected with the second signal source 2.
The second buffer 32 may be a zero-delay buffer, the second buffer 32 fans out one clock control signal into a plurality of clock control signals, and zero-delay and low skew are provided between the outputs, and the second buffer 32 increases the synchronization of the circuit clock in a one-to-many manner, thereby ensuring that two second signals serving as the clock control signals can be transmitted synchronously all the time.
The receiving end of the second buffer 32 is connected to the signal output end of the frequency multiplier 40, and the receiving end of the frequency multiplier 40 is connected to the second signal source 2.
Arrangement of frequency multiplier 40, e.g. with input frequency f1Then the output frequency is f0＝nf1The coefficient n is 1/2 or 2, the coefficient n of the frequency-doubled second signal shown in fig. 2a and 2b is set to be 1/2, and of course, the coefficient n may be set according to the actual signal processing condition, and the frequency of the second signal is increased by two times by the general frequency multiplier 40, so as to increase the speed of outputting the same-frequency and same-phase signals of the first and second flip- flops 11 and 12, and further improve the performance of the system.
Referring to fig. 2a, the output of the third and fourth signals obtained by the processing of the apparatus is shown, the delayed first signal is used as the input signal of the first and second flip- flops 11 and 12, the frequency-multiplied second signal is used as the clock control signal of the first and second flip- flops 11 and 12, and the first and second flip- flops 11 and 12 process the delayed first signal based on the frequency-multiplied second signal and output the third and fourth signals.
In the present application, the first and second flip- flops 11 and 12 will be described in detail with reference to fig. 2b to process the delayed first signal based on the frequency-multiplied second signal.
Triggering the jump of the first signal after the delay at each rising edge of the second signal, and maintaining the state of the high-level signal after the jump of the first signal after the rising edge; each falling edge of the second signal and the low level signal following the falling edge maintain the state of the delayed first signal input,
at t0To t1In the interval, a second signal serving as a clock signal comprises a falling edge and a low-level signal after the falling edge, the first and second flip-flops receive the clock signal, and third and fourth signals output by the first and second flip-flops maintain the input state of the delayed first signal;
at t1To t2In the interval, the second signal as clock signal includes rising edge and high level signal after the rising edge, the rising edge of the second signal triggers the jump of the first signal after delay, the high level signal after the rising edge maintains the state after the jump of the first signal, and the first and second flip-flops outputThe third and fourth signals are in low state as shown in fig. 2 b.
At t0To t2The interval between the output of the third and fourth signals is one period, and the interval between t2 and t4 is the sum of the output of the third and fourth signals and t0To t2The outputs of the third and fourth signals within the interval are the same, as shown in fig. 2 b.
Fig. 3 shows a schematic flow chart of a method of phase synchronization according to an embodiment of the present application, including steps 302 to 308.
Step 302: receiving a first signal and a second signal to be processed, wherein the first signal and the second signal are square wave signals with same frequency and different phases.
Step 304: the two first signals are input to the signal receiving ends of the first and second flip- flops 11 and 12.
Step 306: the two second signals are input to the clock signal terminals of the first and second flip- flops 11 and 12.
Step 308: the output ends of the first and second flip- flops 11 and 12 respectively output a third and a fourth signals with the same frequency and phase.
The method carries out phase synchronization processing on two square wave signals with the same frequency and different phases, a receiving end of a first trigger 11 and a receiving end of a second trigger 12 receive a first signal output by a first signal source 1, a clock signal end of the first trigger 11 and the second trigger 12 receive a second signal output by a second signal source 2, the second signal is directly used as a clock control signal and is respectively input to the first trigger 11 and the second trigger 12, and output ends of the first trigger 11 and the second trigger 12 respectively output a third signal and a fourth signal with the same frequency and phase, so that on one hand, the condition that the system performance is reduced due to different phases of the two signals is avoided, and the working performance of the system is ensured; on the other hand, the square wave is additionally generated as a clock control signal without arranging components such as a crystal oscillator, a filter and the like, so that the purchase of the components is reduced, and the cost of signal processing is reduced.
Fig. 4 shows a schematic flow chart of a method of phase synchronization according to another embodiment of the present application, including steps 402 to 412.
Step 402: receiving a first signal and a second signal to be processed, wherein the first signal and the second signal are square wave signals with same frequency and different phases.
Step 404: and converting the first signal into two first signals, and respectively carrying out time delay processing on the two first signals.
The time for inputting the two first signals into the first and second flip- flops 11 and 12 is staggered, so that the condition that the two first signals are input into the first and second flip- flops 11 and 12 to have dead zones is prevented, the first signals and the second signals can be stably phase-synchronized, and the performance of the system is improved.
Step 406: doubling the frequency of the second signal, converting the second signal into two second signals.
The frequency of the second signal can be increased by two times to increase the speed of outputting the same-frequency and same-phase signals of the first and second flip- flops 11 and 12, thereby further improving the performance of the system.
Step 408: the two first signals are input to the signal receiving ends of the first and second flip- flops 11 and 12.
Step 410: the two second signals are input to the clock signal terminals of the first and second flip- flops 11 and 12.
Step 412: the output ends of the first and second flip- flops 11 and 12 respectively output a third and a fourth signals with the same frequency and phase.
An embodiment of the present application further provides an antenna array transmitter of a cellular network, including the phase synchronization apparatus as described above.
An embodiment of the present application further provides an antenna array receiver of a cellular network, including the phase synchronization apparatus as described above.
An embodiment of the present application further provides a wireless multi-antenna array electronic device, including the phase synchronization apparatus as described above.
The device is suitable for various wireless multi-antenna communication systems, reduces beam directivity deviation in the array antenna, improves gain in the array antenna, and reduces baseband desynchronization risk in the multi-input multi-output communication system.
The above is a schematic solution of the antenna array transmitter of the cellular network, the antenna array receiver of the cellular network, and the wireless multi-antenna array electronic device of the present embodiment. It should be noted that the above technical solution and the technical solution of the phase synchronization apparatus belong to the same concept, and details that are not described in detail in the above technical solution can be referred to the description of the technical solution of the phase synchronization apparatus.
The preferred embodiments and examples of the present application have been described in detail with reference to the accompanying drawings, but the present application is not limited to the embodiments and examples described above, and various changes can be made within the knowledge of those skilled in the art without departing from the concept of the present application.
Claims (10)
1. A phase synchronization apparatus, characterized in that: the receiving end of the first trigger (11) is connected with the first signal source (1), the clock signal end of the first trigger (11) is connected with the second signal source (2), the receiving end of the second trigger (12) is connected with the first signal source (1), and the clock signal end of the second trigger (12) is connected with the second signal source (2).
2. The phase synchronization apparatus according to claim 1, wherein: the signal source circuit further comprises a first delayer (21) and a second delayer (22), wherein the output end of the first delayer (21) is connected with the receiving end of the first trigger (11), the output end of the second delayer (22) is connected with the receiving end of the second trigger (12), and the receiving ends of the first delayer (21) and the second delayer (22) are connected with the first signal source (1).
3. The phase synchronization apparatus according to claim 2, wherein: the receiving ends of the first delayer (21) and the second delayer (22) are respectively connected with the output end of the first buffer (31), and the receiving end of the first buffer (31) is connected with the first signal source (1).
4. The phase synchronization device according to any one of claims 1 to 3, characterized in that: the clock signal ends of the first trigger (11) and the second trigger (12) are respectively connected with the output end of the second buffer (32), and the receiving end of the second buffer (32) is connected with a second signal source (2).
5. The phase synchronization apparatus according to claim 4, wherein: the receiving end of the second buffer (32) is connected with the output end of the frequency multiplier (40), and the receiving end of the frequency multiplier (40) is connected with the second signal source (2).
6. A method of phase synchronization for use in a phase synchronization apparatus according to any one of claims 1 to 5, characterized by:
receiving a first signal and a second signal to be processed, wherein the first signal and the second signal are square wave signals with same frequency and different phases;
inputting the two first signals to signal receiving ends of a first trigger (11) and a second trigger (12);
inputting two second signals to clock signal ends of the first flip-flop and the second flip-flop (11 and 12);
the output ends of the first and second triggers (11, 12) respectively output a third and a fourth signals with same frequency and phase.
7. The method according to claim 6, wherein before inputting the two first signals to the signal receiving ends of the first and second flip-flops (11, 12), further comprising:
converting the first signal into two first signals;
respectively carrying out time delay processing on the two first signals;
before inputting the two second signals to the clock signal terminals of the first and second flip-flops (11, 12), the method further includes:
doubling the frequency of the second signal;
the second signal is converted into two second signals.
8. An antenna array transmitter for a cellular network, comprising: comprising a phase synchronization device according to any one of claims 1 to 5.
9. An antenna array receiver for a cellular network, characterized by: comprising a phase synchronization device according to any one of claims 1 to 5.
10. A wireless multiple antenna array electronic device, comprising: comprising a phase synchronization device according to any one of claims 1 to 5.
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| CN201910612126.7A CN112202446A (en) | 2019-07-08 | 2019-07-08 | Phase synchronization device and method |
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