CN112201288A

CN112201288A - Storage unit structure and array structure of SRAM

Info

Publication number: CN112201288A
Application number: CN202011083820.3A
Authority: CN
Inventors: 周晓君
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2020-10-12
Filing date: 2020-10-12
Publication date: 2021-01-08

Abstract

The invention discloses a storage unit structure of SRAM, comprising: a main body circuit, a write port circuit and a read port circuit; the main body circuit comprises a pair of first storage nodes and second storage nodes which are mutually inverted and mutually latched; the read port circuit comprises a first MOS transistor, the grid electrode of the first MOS transistor is connected with one of the first storage node and the second storage node, and two source-drain regions of the first MOS transistor are respectively connected with a read bit line and a read word line; in the reading operation process, the reading bit line is at a low level, and the reading word line is at a high level; during the write operation and standby, both the read bit line and the read word line are held low. The invention also discloses an array structure of the SRAM. The invention can improve the static noise tolerance and the write-in allowance of the SRAM and reduce the circuit area at the same time.

Description

Storage unit structure and array structure of SRAM

Technical Field

The present invention relates to semiconductor integrated circuits, and more particularly, to a memory cell structure of an SRAM; the invention also relates to an array structure of the SRAM.

Background

Currently, the read-write separation SRAM circuit is commonly used in the industry, and the conventional read-write separation SRAM circuit usually uses the memory cell of 8T2P type SRAM shown in fig. 1, where 8T indicates that there are 8 transistors in the memory cell, and 2P indicates that there are two ports (ports), i.e., a write port and a read port. As shown in fig. 1, the memory cell of the conventional 8T2P SRAM includes a write port circuit composed of

select transistors

101 and 102, P-type pull-

up transistors

103 and 104, and N-type pull-

down transistors

105 and 106, in fig. 1, the select transistor 101 is also denoted by PG1, the select transistor 102 is also denoted by PG2, the P-type pull-up transistor 103 is also denoted by PU1, the P-type pull-up transistor 104 is also denoted by PU2, the N-type pull-down transistor 105 is also denoted by PD1, and the N-type pull-down transistor 106 is also denoted by PD 2. It can be seen that the write port circuit is a conventional 6T-SRAM memory cell. The P-type pull-up tube 103 and the N-type pull-down tube 105 form a CMOS inverter, the P-type pull-up tube 104 and the N-type pull-down tube 106 also form a CMOS inverter, the two CMOS inverters are connected end to form a latch, and the latch comprises a first storage node Q and a second storage node Qb which are mutually opposite in phase and interlocked. The sources of the P-type pull-

up transistors

103 and 104 are both connected to a power supply voltage Vdd, the sources of the N-type pull-

down transistors

105 and 106 are both connected to ground Vss, the gates of the

selection transistors

101 and 102 are both connected to a write word line WWL, the selection transistor 101 connects and disconnects the first storage node Q and the first write bit line WBL, and the selection transistor 102 connects and disconnects the second storage node Qb and the second write bit line WBLB under the control of the write word line WWL.

The write port circuit enables a single write operation. The read port circuit in fig. 1 further includes a read port circuit for performing a separate read operation, the read port circuit in fig. 1 includes two NMOS transistors, i.e., a read select transistor 107 and a read pull-down transistor 108, respectively, in fig. 1, the read select transistor 107 is also denoted by RPG, and the read pull-down transistor 108 is also denoted by RPD. The gate of the read pull-down tube 108 is connected to the second storage node Qb, and the source is connected to Vss. The drain of the read pull-down tube 108 is connected to the source of the read select tube 107, and the drain of the select tube 107 is connected to the read bit line RBL.

In the circuit shown in FIG. 1, during a read operation, the read word line RWL is connected to a high level, such as Vdd, and the read select transistor 107 is turned on; the read bit line RBL is also connected to a high level, so that when the information stored on the second storage node Qb is different, the conduction states of the read pull-down tube 108 are different, and when the read pull-down tube 108 is conducted, the potential of the read bit line RBL is lowered; when the read pull-down tube 108 is turned off, the potential of the read bit line RBL is kept high.

During the write operation and standby, the read word line RWL is connected to a low level, such as ground Vss, and the read select transistor 107 is turned off, so that the high level on the read bit line RBL does not adversely affect the first storage node Q and the second storage node Qb. Finally, the static noise margin (SNW) and the Write Margin (WM) of the circuit can be improved. In contrast, if the read select pipe 107 is not provided when the read bit line RBL is at a high level, the high level of the read bit line RBL easily interferes with the first storage node Q and the second storage node Qb, thereby lowering SNW and WM. That is, in the conventional SRAM, two NMOS shown in fig. 1, i.e., the read select transistor 107 and the read pull-down transistor 108, must be used to obtain better SNW and WM.

In the prior art circuit shown in fig. 1, the port settings under various operations are shown in table one:

watch 1

Operation of	Port voltage setting
		Read	RBL＝RWL＝Vdd，WWL＝Gnd，WBL＝WBLB＝Vdd
Write	Vdd, inverse WBL and WBLB, Gnd, Vdd, and RBL
		Standby	WWL＝RWL＝Gnd，WBL＝WBLB＝RBL＝Vdd

In the first table, Read represents Read operation, Write represents Write operation, and Standby represents Standby;

RBL denotes a read bitline, RWL denotes a read wordline, WWL denotes a write wordline, WBL denotes a first write bitline, and WBLB denotes a second write bitline. Vdd denotes the supply voltage and the high levels in table one are all Vdd. Gnd is expressed as Vss.

With the development of technology, chip size is expected to be smaller, and 8 transistors are included in the memory cell of the SRAM shown in fig. 1, which increases the circuit area. As shown in fig. 2, is a layout of the memory cell shown in fig. 1; in fig. 2, two adjacent columns of memory cells in the same row are shown, the two memory cells are respectively outlined by dashed-

line boxes

201a and 201b, and the

memory cells

201a and 201b have a left-right symmetric structure. The transistors in fig. 1 are indicated in fig. 2 by corresponding dashed boxes. The layout shown in fig. 2 shows 4 levels, which are: an active region 202, a polysilicon gate 203, a contact hole 204, and a first metal layer pattern 205. In fig. 2, the same memory cell includes 5 active regions, wherein the read select transistor 107 and the read pull-down transistor 108 are formed in the same active region 202, the select transistor 101 and the N-type pull-down transistor 105 are located in the same active region 202, the P-type pull-

up transistors

103 and 104 are respectively located in separate active regions, and the select transistor 102 and the N-type pull-down transistor 106 are located in the same active region 202.

Each transistor includes a polysilicon gate 203 composed of polysilicon, and source and drain regions formed in active regions on both sides of the polysilicon gate 203, and tops of the polysilicon gate 203, the source and drain regions are connected to corresponding first-layer metal layer patterns 205 through corresponding contact holes 204.

As shown in FIG. 2, the read select transistor 107 and the read pull-down transistor 108 need to occupy one active region 202 separately, which increases the circuit area. Therefore, the conventional 8T2P SRAM shown in fig. 1 is effective in improving SNM and WM as compared with the conventional 6T SRAM, but is disadvantageous in reducing the circuit area.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a storage unit structure of an SRAM, which can realize read-write separation and minimize the number of transistors of a read port under the condition that a circuit has better SNW and WM performances, thereby saving the circuit area. Therefore, the invention also discloses an array structure of the SRAM.

In order to solve the above technical problem, the present invention provides a memory cell structure of an SRAM, wherein the memory cell includes: the circuit comprises a main body circuit, a write port circuit and a read port circuit.

The body circuit includes a pair of first and second storage nodes that are inverted and latched with each other.

The read port circuit comprises a first MOS transistor, the grid electrode of the first MOS transistor is connected with one of the first storage node and the second storage node, the first source drain region of the first MOS transistor is connected with a read bit line, and the second source drain region of the first MOS transistor is connected with a read word line.

The operation of the memory cell includes a write operation, a read operation, and a standby.

In the process of reading operation, the reading bit line is at low level, and the reading word line is at high level.

In the process of writing operation and standby, the reading bit line and the reading word line are both kept at low level, so that interference of the reading bit line and the reading word line on the main circuit through the first MOS transistor is eliminated, and the static noise tolerance and the writing allowance of the SRAM are improved.

In a further improvement, the main body circuit is formed by connecting a first CMOS inverter and a second CMOS inverter, an output terminal of the first CMOS inverter and an input terminal of the second CMOS inverter are connected together and serve as the second storage node, and an output terminal of the second CMOS inverter and an input terminal of the first CMOS inverter are connected together and serve as the first storage node.

In a further refinement, the write port circuit includes a first select pipe and a second select pipe.

The grid electrode of the first selection tube and the grid electrode of the second selection tube are connected to a write word line.

And a first source drain region of the first selection tube is connected with a first writing bit line, and a second source drain region of the first selection tube is connected with the first storage node.

And the first source drain region of the second selection tube is connected with a second write bit line, and the second source drain region of the first selection tube is connected with the second storage node.

In a further improvement, the main body circuit and the write port circuit form a 6T circuit.

The first CMOS phase inverter consists of a first PMOS pull-up tube and a first NMOS pull-down tube.

The second CMOS phase inverter consists of a second PMOS pull-up tube and a second NMOS pull-down tube.

The first selection tube and the second selection tube are both NMOS tubes.

In a further improvement, the main body circuit, the write port circuit and the read port circuit form a 7T circuit.

In a further improvement, the first MOS transistor is an NMOS transistor;

or, the first MOS transistor is a PMOS tube.

In order to solve the above technical problem, the array structure of the SRAM provided by the present invention is formed by arranging the memory cell rows and columns.

In the same row, the read port circuits of the memory cells of two adjacent columns are formed in the same first active region.

In a further improvement, the second source drain regions of the first MOS transistors in two adjacent columns in the same first active region are shared, and the read word line is shared.

The layout of the memory cells sharing the same first active region and two adjacent columns in the same row is in a central symmetry structure with the center of the shared second source drain region as a symmetry center.

The first selection tube and the second selection tube are both NMOS tubes.

In a further improvement, the first MOS transistor is an NMOS transistor;

or, the first MOS transistor is a PMOS tube.

In a further improvement, the write word lines of the same row are all connected together, the first write bit lines of the same column are all connected together, and the second write bit lines of the same column are all connected together.

Different from the prior 8T2P type SRAM memory cell, the read port of the memory cell of the SRAM of the invention further reduces one MOS transistor, and can be realized by adopting one first MOS transistor, meanwhile, in order to avoid the adverse effect on SNW and WM of the memory cell generated when the read bit line BL directly reads the drain electrode of the pull-down tube 108 in the prior structure shown in figure 1, the invention also makes special arrangement on the connection relationship of the first MOS transistor, the read bit line and the read word line, connects the first source drain region of the first MOS transistor with the read bit line and connects the second source drain region of the first MOS transistor with the read word line, and sets the voltage of the read bit line and the read word line in the processes of writing operation, reading operation and standby, the invention can ensure the read operation of the read bit line and the read word line, and simultaneously keeps the read bit line and the read word line at low level in the processes of writing operation and standby, therefore, the memory cell still has better SNW and WM performances; that is, the invention can use one transistor as the read port to realize the SNW and WM performance improvement effect of the prior 8T2P SRAM memory cell which uses 2 transistors, but the invention can save one transistor, thereby reducing the circuit area finally.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a circuit diagram of a memory cell of a conventional 8T2P type SRAM;

FIG. 2 is a layout of the memory cell shown in FIG. 1;

FIG. 3 is a circuit diagram of a memory cell of an SRAM according to an embodiment of the present invention;

fig. 4 is a layout of the memory cell shown in fig. 3.

Detailed Description

FIG. 3 is a circuit diagram of a memory cell of an SRAM according to an embodiment of the present invention; the memory cell structure of the SRAM of the present invention comprises: the circuit comprises a main body circuit, a write port circuit and a read port circuit.

The main body circuit includes a pair of first and second storage nodes Q and Qb that are inverted and latched with each other.

The read port circuit comprises a first MOS transistor 7, wherein the grid electrode of the first MOS transistor 7 is connected with one of the first storage node Q and the second storage node Qb, the first source-drain region of the first MOS transistor 7 is connected with a read bit line RBL, and the second source-drain region of the first MOS transistor 7 is connected with a read word line RWL.

In a read operation, the read bit line RBL is at a low level and the read word line RWL is at a high level.

In the process of writing operation and standby, the read bit line RBL and the read word line RWL are both kept at a low level, so that the interference of the read bit line RBL and the read word line RWL on the main body circuit through the first MOS transistor 7 is eliminated, and the static noise tolerance and the write margin of the SRAM are improved.

In an embodiment of the present invention, the main body circuit is formed by connecting a first CMOS inverter and a second CMOS inverter, an output terminal of the first CMOS inverter and an input terminal of the second CMOS inverter are connected together and serve as the second storage node Qb, and an output terminal of the second CMOS inverter and an input terminal of the first CMOS inverter are connected together and serve as the first storage node Q.

The write port circuit includes a first select tube 1 and a second select tube 2.

The grid electrode of the first selection tube 1 and the grid electrode of the second selection tube 2 are both connected to a write word line WWL.

The first source drain region of the first selection tube 1 is connected with a first write bit line WBL, and the second source drain region of the first selection tube 1 is connected with the first storage node Q.

And a first source-drain region of the second selection tube 2 is connected with a second write bit line WBLB, and a second source-drain region of the first selection tube 1 is connected with the second storage node Qb.

The main body circuit and the write port circuit form a 6T circuit.

The first CMOS phase inverter is composed of a first PMOS pull-up tube 3 and a first NMOS pull-down tube 5.

The second CMOS phase inverter is composed of a second PMOS pull-up tube 4 and a second NMOS pull-down tube 6.

The first selection tube 1 and the second selection tube 2 are both NMOS tubes.

The main body circuit, the write port circuit and the read port circuit form a 7T circuit.

In the embodiment of the present invention, the first MOS transistor 7 is an NMOS transistor. In other embodiments can also be: the first MOS transistor 7 is a PMOS transistor.

The array structure of the SRAM provided by the embodiment of the invention is formed by arranging the memory cell rows and columns.

And the second source-drain regions of the first MOS transistors 7 in two adjacent columns in the same first active region are shared, and the read word line RWL is shared.

The layout of the memory cells sharing the same two adjacent columns of the first active region in the same row is of a central symmetry structure taking the center of the shared second source drain region as a symmetry center.

The write word lines WWL of the same row are all connected together, the first write bit lines WBL of the same column are all connected together, and the second write bit lines WBLB of the same column are all connected together.

Unlike the conventional 8T2P SRAM cell shown in fig. 1, the SRAM cell according to the embodiment of the present invention is 7T2P, which can separate the read port from the write port and reduce the area by reducing one transistor, and the SRAM cell according to the embodiment of the present invention can also have the same performance of SNW and WM as the conventional 8T2P SRAM cell by setting the voltage of the port.

In the SRAM memory cell of the embodiment of the present invention shown in fig. 3, the port settings under various operations are shown in table two:

watch two

Operation of	Port voltage setting
		Read	RWL＝Vdd，RBL＝Gnd，WWL＝Gnd，WBL＝WBLB＝Vdd
Write	Vdd, WBL inverted from WBLB, Gnd, and Gnd
		Standby	WWL＝RWL＝Gnd，WBL＝WBLB＝Vdd，RBL＝Gnd

Comparing with the table one, the RBLs in the embodiment of the present invention are always connected to low level, i.e. ground, and the settings of the RBLs in table one are exactly opposite, and the settings of other ports are the same. It can be seen that the embodiments of the present invention only need to set the voltage of the RBL to a low level to achieve the same SNW and WM performance as the prior art circuit shown in fig. 1.

The read port circuit of the storage unit of the SRAM provided by the embodiment of the invention can reduce the circuit area due to the fact that one transistor is reduced. As shown in fig. 4, is a layout of the memory cell shown in fig. 3; in fig. 4, two adjacent columns of memory cells in the same row are shown, the two memory cells are respectively outlined by dashed-

line boxes

301a and 301b, and the

memory cells

301a and 301b have a centrosymmetric structure. The transistors in fig. 3 are indicated in fig. 4 by corresponding dashed boxes. The layout shown in fig. 4 shows 4 levels, which are: an active region 302, a polysilicon gate 303, a Contact hole 304, and a first-level metal layer pattern 305, wherein in fig. 4, expressions corresponding to 4 levels are shown on the left side of two

memory cells

301a and 301b, the active region 302 is also denoted by AA, the polysilicon gate 303 is also denoted by PO, the Contact hole 304 is also denoted by Contact, and the first-level metal layer pattern 305 is also denoted by M1. In fig. 4, the same memory cell includes 4.5 active regions, where the first MOS transistors 7 of two

adjacent memory cells

301a and 301b share the same active region, so that on average, the first MOS transistor 7 in the next memory cell occupies only 0.5 active regions; the first selection tube 1 and the first NMOS pull-down tube 5 are located in the same active region 302, the first PMOS pull-up tube 3 and the second PMOS pull-up tube 4 are located in separate active regions respectively, and the second selection tube 2 and the second NMOS pull-down tube 6 are located in the same active region 302.

Each transistor includes a polysilicon gate 303 made of polysilicon and source and drain regions formed in active regions at both sides of the polysilicon gate 303, and tops of the polysilicon gate 303, the source and drain regions are connected to corresponding first-layer metal layer patterns 305 through corresponding contact holes 304.

As can be seen from comparison with fig. 2, in the layout of the embodiment of the present invention corresponding to fig. 4, the first MOS transistor 7 of the next memory cell occupies only 0.5 active regions 302 on average, so that the circuit area is reduced. Meanwhile, the embodiment of the invention can also effectively improve SNM and WM.

Different from the prior 8T2P type SRAM memory cell, the read port of the memory cell of the SRAM of the invention further reduces one MOS transistor, and can be realized by adopting one first MOS transistor 7, meanwhile, in order to avoid the adverse effect on SNW and WM of the memory cell generated when the read bit line RBLBL directly reads the drain electrode of the pull-down tube 108 in the prior structure shown in figure 1, the invention also makes special arrangement on the connection relation of the first MOS transistor 7, the read bit line RBL and the read word line RWL, connects the first source-drain region of the first MOS transistor 7 with the read bit line RBL and connects the second source-drain region of the first MOS transistor 7 with the read word line RWL, and sets the voltage of the read bit line RBL and the read word line RWL in the processes of writing operation, reading operation and standby, and the invention ensures that the read bit line RBL and the read word line RWL can realize the reading operation, and the read bit line RBL and the read word line RWL can keep the low standby level in the processes of writing operation and the standby level, therefore, the memory cell still has better SNW and WM performances; that is, the invention can use one transistor as the read port to realize the SNW and WM performance improvement effect of the prior 8T2P SRAM memory cell which uses 2 transistors, but the invention can save one transistor, thereby reducing the circuit area finally.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. A memory cell structure of SRAM, wherein the memory cell comprises: a main body circuit, a write port circuit and a read port circuit;

the main body circuit comprises a pair of first storage nodes and second storage nodes which are mutually inverted and mutually latched;

the read port circuit comprises a first MOS transistor, the grid electrode of the first MOS transistor is connected with one of the first storage node and the second storage node, the first source drain region of the first MOS transistor is connected with a read bit line, and the second source drain region of the first MOS transistor is connected with a read word line;

the operation of the storage unit comprises writing operation, reading operation and standby;

in the reading operation process, the reading bit line is at a low level, and the reading word line is at a high level;

2. The memory cell structure of SRAM of claim 1, wherein: the main body circuit is formed by connecting a first CMOS phase inverter and a second CMOS phase inverter, the output end of the first CMOS phase inverter and the input end of the second CMOS phase inverter are connected together and used as the second storage node, and the output end of the second CMOS phase inverter and the input end of the first CMOS phase inverter are connected together and used as the first storage node.

3. The memory cell structure of the SRAM of claim 2, wherein: the write port circuit comprises a first selection pipe and a second selection pipe;

the grid electrode of the first selection tube and the grid electrode of the second selection tube are connected to a write word line;

a first source drain region of the first selection tube is connected with a first writing bit line, and a second source drain region of the first selection tube is connected with the first storage node;

4. The memory cell structure of SRAM of claim 3, wherein: the main body circuit and the write port circuit form a 6T circuit;

the first CMOS phase inverter consists of a first PMOS pull-up tube and a first NMOS pull-down tube;

the second CMOS phase inverter consists of a second PMOS pull-up tube and a second NMOS pull-down tube;

the first selection tube and the second selection tube are both NMOS tubes.

5. The memory cell structure of the SRAM of claim 4, wherein: the main body circuit, the write port circuit and the read port circuit form a 7T circuit.

6. The memory cell structure of the SRAM of claim 5, wherein: the first MOS transistor is an NMOS transistor;

or, the first MOS transistor is a PMOS tube.

7. An array structure of an SRAM, characterized in that: the array structure is formed by arranging rows and columns of the memory cells of claim 1;

8. The array structure of the SRAM of claim 7, wherein: and the second source-drain regions of the first MOS transistors in two adjacent columns in the same first active region are shared, and the read word line is shared.

9. The array structure of the SRAM of claim 8, wherein: the layout of the memory cells sharing the same two adjacent columns of the first active region in the same row is of a central symmetry structure taking the center of the shared second source drain region as a symmetry center.

10. The array structure of the SRAM of claim 7, 8, or 9, wherein: the main body circuit is formed by connecting a first CMOS phase inverter and a second CMOS phase inverter, the output end of the first CMOS phase inverter and the input end of the second CMOS phase inverter are connected together and used as the second storage node, and the output end of the second CMOS phase inverter and the input end of the first CMOS phase inverter are connected together and used as the first storage node.

11. The array structure of the SRAM of claim 10, wherein: the write port circuit comprises a first selection pipe and a second selection pipe;

12. The array structure of the SRAM of claim 11, wherein: the main body circuit and the write port circuit form a 6T circuit;

the first selection tube and the second selection tube are both NMOS tubes.

13. The array structure of the SRAM of claim 12, wherein: the main body circuit, the write port circuit and the read port circuit form a 7T circuit.

14. The array structure of the SRAM of claim 13, wherein: the first MOS transistor is an NMOS transistor;

or, the first MOS transistor is a PMOS tube.

15. The array structure of the SRAM of claim 11, wherein: the write word lines of the same row are all connected together, the first write bit lines of the same column are all connected together, and the second write bit lines of the same column are all connected together.