CN112200806A - Wafer defect analysis method and system - Google Patents
Wafer defect analysis method and system Download PDFInfo
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Abstract
The invention discloses a wafer defect analysis method and a system, wherein the method comprises the following steps: establishing a defect automatic identification system of the wafer; collecting the lethality data of various defects of the wafer to form a lethality calculation library; automatically identifying and classifying the wafer surface defect sample pictures scanned by the machine according to the automatic defect identification system; calculating and analyzing the classified wafer surface defect sample pictures according to the mortality calculation library; data information of the analysis conclusions and/or reference decisions is formed. The method can reduce the problems of subjective error, low efficiency of mutual cooperation and overall planning and the like of different engineers in the analysis process.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing technologies, and in particular, to a method and a system for analyzing defects of a semiconductor wafer.
Background
During the processing of semiconductor wafers, defects (defects) may occur due to the problems of imperfect processes, lack of maintenance of the equipment, contamination of the manufacturing materials, etc., thereby reducing the yield of the wafers. This requires companies to have their own defect analysis decision system that requires engineers to perform relevant analyses on defects. For example: and judging the influence of the size of the defect on the chip function of the area where the defect is located. Due to the fact that the number of sources of defect generation is large, the types of generated defects are large, and a company needs to arrange engineers to manually classify the generated defects. The defect images are scanned by the machine, and after obtaining the relevant images, engineers are required to classify each defect image and input the category of each image into a database for further analysis and decision-making.
At present, with the continuous improvement of semiconductor production capacity, defect image data generated every day is more and more, and often a thousand defect images are generated by one process, and manual image classification is clumsy and inefficient in analyzing different defects.
The problems of the current defect analysis system are as follows: 1) the production capacity of the company is continuously improved, the defect image data to be processed become more, and the current manpower cannot meet the requirement. 2) Different engineers cannot completely accord with the image judgment standard, and the image classification is inaccurate due to more subjective factors. 3) The engineer can only calculate the relevant indexes on the manual calculation level, the time consumption is long, the decision cannot be given in time, the calculated amount is large, and the artificial errors are easy to occur. 4) The whole analysis system is cooperated by a plurality of engineers, the tasks are dispersed, the uniformity harmony is poor, and the system efficiency is low.
Disclosure of Invention
The invention mainly solves the technical problems in the prior art, and provides the defect analysis method and the defect analysis system for the semiconductor wafer, which have the advantages of high analysis speed, high accuracy and good uniformity and harmony.
The technical problem of the invention is mainly solved by the following technical scheme:
the invention provides a defect analysis method of a wafer, which comprises the following steps:
establishing a defect automatic identification system of the wafer;
collecting the lethality data of various defects of the wafer to form a lethality calculation library;
automatically identifying and classifying the wafer surface defect sample pictures scanned by the machine according to the automatic defect identification system; and
according to the mortality calculation library, calculating and analyzing the classified wafer surface defect sample pictures;
data information of the analysis conclusions and/or reference decisions is formed.
Further, the establishing step of the automatic defect identification system comprises the following steps:
collecting various types of wafer surface defect picture data;
preprocessing the wafer surface defect picture data, and classifying and labeling according to defect types;
and forming a defect identification model, and performing parameter training by using a neural network method.
Further, the step of forming the mortality calculation library comprises:
collecting defect information of the wafer in a current chip area, wherein the current chip area comprises a central chip area, a first adjacent chip area and a second adjacent chip area, and the first adjacent chip area and the second adjacent chip area are arranged on the periphery of the central chip area in a staggered mode;
respectively counting yield loss conditions of the central chip area, the first adjacent chip area and the second adjacent chip area, and calculating corresponding fatality rate data;
the current calculated library of mortality for defects is: the fatality rates of the central chip area, the first adjacent chip area and the second adjacent chip area are respectively multiplied by the defect number of the corresponding area, and the sum is divided by the total defect number of the current chip area.
Further, according to the automatic defect identification system, the step of automatically identifying and classifying the wafer surface defect sample picture comprises:
and re-labeling the defect type information of the wafer surface defect sample pictures which are identified incorrectly or not classified, and performing parameter training of the defect identification model.
Further, the step of automatically identifying and classifying the wafer surface defect sample picture further comprises:
feeding back the accurately identified wafer surface defect sample picture to the defect identification model;
through the defect identification model, sample collection is carried out on the wafer surface defect sample picture which is accurately identified, and a sample label is added according to the defect type;
performing parameter training on the defect identification model;
model parameters in the sample labels are derived.
Further, the content of performing computational analysis on the classified wafer surface defect sample picture includes:
calculating whether the total defect number of each wafer exceeds a set reference line or not;
calculating the predicted yield loss data of each wafer;
calculating the lethality data of each defect on the wafer with different densities and sizes;
collecting the defect information and the station passing information of the wafer to perform machine station difference analysis processing;
and identifying the wafer image with the special shape of the good product rate.
Further, the step of calculating the mortality data for each defect on the wafer with different density and different size comprises:
collecting defect information of the wafer;
calculating the defect size or defect density information of each defect on the wafer in groups;
obtaining a grouping standard of the defect size or the defect density, and counting the number of the defects with different defect sizes or defect densities;
the mortality of the defects was calculated under a grouping criterion of different defect sizes or defect densities.
Further, the step of performing grouping calculation on the defect size or defect density information includes:
randomly selecting k points as a clustering center, wherein k is less than 10;
calculating the clustering of each point to k clustering centers respectively;
assigning the point to the nearest cluster center, thus forming k clusters;
recalculating the centroid of each cluster;
repeating the step of recalculating the centroid of each cluster for 2-4 times until the position of the centroid is no longer changed or a set number of iterations is reached;
the k value for the best group is obtained and the range of values for each group is given.
Further, the content of the data information forming the analysis conclusion and/or the reference decision comprises:
forming prompt early warning information according to whether the defect number of the wafer exceeds a set reference line;
according to the fatality rate calculation library of various defects of the wafer, early warning is carried out on the scrappage of the wafer, and scrappage suggestion information is provided;
analyzing according to the yield loss, defect type, defect density and defect size data of the wafer to form mortality report information;
forming machine early warning and maintenance suggestion information according to machine difference analysis;
and calculating and analyzing the cause information of low yield according to the wafer surface defect picture matched with the wafer picture of the special shape of the yield.
The invention provides a system for analyzing defects of a wafer, comprising:
the automatic defect identification unit comprises a model training module and an identification classification module, wherein the model training module is used for forming a defect identification model and performing parameter training according to the classified wafer surface defect pictures, and the identification classification module is used for identifying and classifying wafer surface defect sample pictures scanned by a machine;
the calculation unit comprises a mortality calculation base module and a calculation module, wherein the mortality calculation base module is used for collecting the mortality data of various defects of the wafer to form a mortality calculation base; the calculation module is respectively connected with the mortality calculation base module and the identification and classification module, and is used for calculating and analyzing the classified wafer surface defect sample pictures according to the mortality calculation base;
and the analysis decision unit is connected with the calculation module and is used for forming an analysis conclusion and/or data information of a reference decision according to the calculation analysis of the calculation module.
The invention can improve the analysis speed and the analysis accuracy of the original semiconductor defect analysis system, and the automatic defect identification system of the semiconductor wafer is added to replace the original manual identification classification method, and the death rate calculation library can be used for automatic index calculation, so that the analysis result can be fed back in time and a corresponding decision can be made. Moreover, the whole defect analysis system can be coordinated uniformly, and the problems of subjective error of different engineers in the analysis process, low efficiency of mutual cooperation and overall planning and the like are avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a method flow diagram of a method for analyzing defects on a wafer according to the present invention;
FIG. 2 is a wafer mortality report under the grouping criteria for different defect sizes in an embodiment of the present invention;
FIG. 3 is a wafer mortality report under different defect density grouping criteria in accordance with an embodiment of the present invention;
FIG. 4 is a functional block diagram of a defect analysis system for a semiconductor wafer of the present invention;
FIG. 5 is a functional block diagram of the electronic device of the present invention;
fig. 6 is a schematic block diagram of the structure of the storage medium of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, and the scope of the present invention will be more clearly and clearly defined.
Referring to fig. 1, the method for analyzing defects of a semiconductor wafer according to the present invention includes the following steps:
s1, establishing a defect automatic identification system of the wafer;
s2, collecting the lethality data of various defects of the wafer to form a lethality calculation library;
s3, automatically identifying and classifying the wafer surface defect sample pictures scanned by the machine according to the automatic defect identification system; and
s4, calculating and analyzing the classified wafer surface defect sample pictures according to the mortality calculation library;
and S5, forming analysis conclusion and/or data information of reference decision.
The method for analyzing the defects of the wafer according to the present embodiment will be described in more detail below.
According to step S1, an automatic defect recognition system for the wafer is established. The semiconductor defect automatic identification system avoids manual identification through the classification mode of automatic image identification, and has the advantages of high identification accuracy, high working efficiency and the like.
Specifically, in this embodiment, the step of establishing the semiconductor defect automatic identification system includes:
collecting various types of semiconductor wafer surface defect picture data; the wafer surface defect picture data can be different types of defects generated by the wafer in different processes, and can also be different types of defects generated in the same process.
Preprocessing the wafer surface defect picture data, and classifying and labeling according to defect types;
and forming a defect identification model, and performing parameter training by using a neural network method.
The neural network method adopted by the embodiment can slowly learn to identify similar images through a self-learning function, has the capability of searching an optimal solution at a high speed, and provides guarantee for continuous optimization training of the subsequent defect identification model.
The step of forming the mortality calculation library according to step S2 includes:
collecting defect information of the wafer in a current chip area, wherein the current chip area comprises a central chip area, a first adjacent chip area and a second adjacent chip area, and the first adjacent chip area and the second adjacent chip area are arranged on the periphery of the central chip area in a staggered mode; in other embodiments of the present invention, the first adjacent chip region and the second adjacent chip region may be adjacently disposed at the outer periphery of the central chip region;
respectively counting yield loss conditions of the central chip area, the first adjacent chip area and the second adjacent chip area, and calculating corresponding fatality rate data;
the current calculated library of mortality for defects is: the fatality rates of the central chip area, the first adjacent chip area and the second adjacent chip area are respectively multiplied by the defect number of the corresponding area, and the sum is divided by the total defect number of the current chip area.
In different embodiments of the present invention, since one defect affects not only the yield of the current chip but also the yield of the peripheral chips, the common effect of the current chip and the peripheral chips needs to be considered comprehensively in order to improve the calculation accuracy of the mortality calculation library.
In one embodiment of the invention, the mortality is calculated by taking defect type code10, data with defect size in the range of 0-0.51 as an example, and a mortality calculation library is formed:
first, collect the defect information of the wafer in the current chip area, such as: the defect number of the central chip area is 9, the defect number of the first adjacent chip area is 1, and the defect number of the second adjacent chip area is 4, wherein the central chip area, the first adjacent chip area and the second adjacent chip area can enclose a nine-grid shape, the central chip area is located at the center position of the nine-grid shape, the first adjacent chip area is located on the extension line of the diagonal of the central chip area (on four corners of the nine-grid shape), and the second adjacent chip area is located on the axis of the central chip area.
Secondly, counting the yield loss conditions of the chips (die) in the central chip area, the first adjacent chip area and the second adjacent chip area, wherein the chip with normal yield is good, the chip with abnormal yield is bad, and the fatality rates (Kill rates) of the central chip area, the first adjacent chip area and the second adjacent chip area can be calculated by adopting the following calculation formula:
Kill ratio=bad die count/total die；
wherein, bad die count is the number of chips with abnormal yield, and total die is the total number of chips in the central chip region, the first adjacent chip region or the second adjacent chip region.
Next, the defect type code10 was counted, and the fatality rate (Kill ratio) of the defect size in the range of 0 to 0.51 was calculated as follows:
Kill ratio = Kill ratio1*1/14+ Kill ratio2*4/14+ Kill ratio3*9/14
wherein Kill ratio1 indicates the defect mortality of the first adjacent chip region, Kill ratio2 indicates the defect mortality of the second adjacent chip region, and Kill ratio3 indicates the defect mortality of the center chip region.
In the present invention, after finishing, a calc library of the lethality of the current defect can be obtained, and part of the calc library is shown in the following table.
According to step S3, the step of automatically recognizing and classifying the wafer surface defect sample picture according to the defect automatic recognition system includes:
and re-labeling the defect type information of the wafer surface defect sample pictures which are identified incorrectly or not classified, and performing parameter training of the defect identification model.
In the invention, the problems of defect type loss, insufficient sample amount, indefinite classification of class information and the like exist in the establishing process of the defect identification model, and the model training is carried out after the defect class information is re-labeled on the wafer surface defect sample picture with wrong identification or unclassified identification, so that the identification capability of the defect identification model on the wafer surface defect sample picture can be improved, and meanwhile, the accuracy of the defect identification model on the classification of the wafer surface defect sample picture can also be improved.
In another embodiment of the present invention, the step of automatically identifying and classifying the wafer surface defect sample picture further includes:
feeding back the accurately identified wafer surface defect sample picture to the defect identification model;
through the defect identification model, sample collection is carried out on the wafer surface defect sample picture which is accurately identified, and a sample label is added according to the defect type;
performing parameter training on the defect identification model;
model parameters in the sample labels are derived.
In an embodiment of the invention, the wafer surface defect sample picture with accurate identification is fed back to the defect identification model again, and sample collection and label addition are separately performed, which can improve the identification precision and accuracy of the wafer surface defect sample picture through parameter training again.
According to step S4, the content of performing calculation analysis on the classified wafer surface defect sample picture according to the mortality calculation library includes:
calculating whether the total defect number of each wafer exceeds a set reference line or not; and the calculation result can be transmitted to a yield promotion department for providing reference for decision making.
Calculating the predicted yield loss data of each wafer; and can transmit the scrapping suggestions to a yield promotion department for providing reference for decision-making.
Calculating the lethality data of each defect on the wafer with different densities and sizes; and transmitting the result to a yield promotion department for providing reference for decision making.
Collecting the defect information and the station passing information of the wafer to perform machine station difference analysis processing; and analyzing the machine which is most likely to generate the defects, and feeding the machine back to an on-line production responsible person and a yield promotion department for providing reference for decision making.
And identifying the wafer image with the special shape of the good product rate.
Specifically, whether the total defect number of each wafer exceeds the set reference line is calculated, and as shown in the following table two, the wafer exceeding the set reference line can be subjected to early warning processing.
From the second table, it can be seen that the total number of defects of wafer-02 is 72, the total number of defects of wafer-25 is 47, if the reference line is set such that the total number of defects is less than 47 (e.g. 40), then both wafer-02 and wafer-25 exceed the set reference line, and the total number of defects of wafer-02 and wafer-25 can be marked as red, so as to facilitate the yield promotion department to distinguish and analyze them subsequently.
In the present invention, the step of calculating the predicted yield loss data of each wafer comprises:
and measuring the defects of each wafer to obtain information such as defect types, defect sizes, defect quantity and the like, and combining data calculated by a lethality calculation library to predict the yield of the chips on the wafer. In an embodiment of the present invention, taking 100 chips on a wafer as an example, the defect information of the wafer is shown in table three.
In the invention, the calculation result of Yield loss (Yield loss) of the wafer is as follows:
Yield loss=（10+1+1+1+5+3）/100*100%=21%
in the invention, the step of calculating the mortality data of each defect on the wafer with different densities and sizes comprises the following steps:
collecting defect information of the wafer;
calculating the defect size or defect density information of each defect on the wafer in groups;
obtaining a grouping standard of the defect size or the defect density, and counting the number of the defects with different defect sizes or defect densities;
the mortality of the defects was calculated under a grouping criterion of different defect sizes or defect densities.
In the present invention, the step of calculating the defect size or defect density information of each defect on the wafer in groups comprises:
randomly selecting k points as a clustering center, wherein k is less than 10;
calculating the clustering of each point to k clustering centers respectively;
assigning the point to the nearest cluster center, thus forming k clusters;
re-calculating the centroid (mean) of each cluster;
repeating the step of recalculating the centroid of each cluster for 2-4 times until the position of the centroid is no longer changed or a set number of iterations is reached;
the k value for the best grouping is obtained and the range of values for each group (grouping criteria) is given.
In an embodiment of the present invention, a mortality report may be generated by calculating the fatality rate of each defect on the wafer under the grouping criteria of different defect sizes or defect densities, so as to facilitate the reference and analysis of decision makers.
In this embodiment, the fatality rate of each defect on the wafer under the grouping criteria of different defect sizes can be as shown in fig. 2. As can be seen from fig. 2, for wafer 1, the mortality rate for group 1 is greater than the mortality rate for group 2, and the mortality rate for group 3 is greater than the mortality rate for group 1. For wafer 2, the mortality rate for group 1 is less than the mortality rate for group 2, and the mortality rate for group 2 is less than the mortality rate for group 3. For wafer 3, the mortality rate for group 1 is less than the mortality rate for group 2. It can therefore be seen from fig. 2 that larger defect sizes increase the wafer fatality rate. Note that the defect sizes of the groups 1 to 4 are increased stepwise.
The fatality rate of each defect on the wafer under the different defect density grouping criteria is shown in fig. 3. As can be seen from fig. 3, for wafer 1, the mortality rate decreased first and then increased in density group 1 to density group 5. For wafer 2, the mortality rate tends to increase in density group 1 to density group 5. For wafer 3, the mortality rate substantially increases in density group 1 to density group 1. It can therefore be seen from fig. 3 that a greater defect density increases wafer fatality. According to step S5, the content of the data information forming the analysis conclusion and/or the reference decision includes:
forming prompt early warning information according to whether the defect number of the wafer exceeds a set reference line;
according to the fatality rate calculation library of various defects of the wafer, early warning is carried out on the scrappage of the wafer, and scrappage suggestion information is provided;
analyzing according to the yield loss, defect type, defect density and defect size data of the wafer to form mortality report information;
forming machine early warning and maintenance suggestion information according to machine difference analysis; specifically, which machines generate a larger number of defects can be judged through the box line graph, and other machines with higher fatality rates and generating defects can be judged through the method.
And calculating and analyzing the cause information of low yield according to the wafer surface defect picture matched with the wafer picture of the special shape of the yield. Specifically, by searching the wafer surface defect pictures of different defect types of each process and matching the wafer surface defect picture most similar to the yield map, the method can quickly find out the specific reason for forming the special shape in the yield map and lock the defect type and the process generated by the defect type.
The invention can realize the unified analysis and decision of the wafer defects through the steps.
Referring to fig. 4, the system for analyzing defects of a wafer according to the present invention includes:
the automatic defect identification unit 1 comprises a model training module 11 and an identification classification module 12, wherein the model training module 11 is used for forming a defect identification model according to the classified wafer surface defect pictures and performing parameter training, and the identification classification module 12 is used for identifying and classifying the wafer surface defect sample pictures scanned by a machine;
the calculating unit 2 comprises a mortality calculating library module 21 and a calculating module 22, wherein the mortality calculating library module 21 is used for collecting the mortality data of various defects of the wafer to form a mortality calculating library; the calculation module 22 is respectively connected with the lethality calculation library module 21 and the identification classification module 12, and the calculation module 22 is used for calculating and analyzing the classified wafer surface defect sample pictures according to the lethality calculation library; specifically, the contents of the computational analysis include: calculating whether the total defect number of each wafer exceeds a set reference line or not; calculating the predicted yield loss data of each wafer; calculating the lethality data of each defect on the wafer with different densities and sizes; collecting the defect information and the station passing information of the wafer to perform machine station difference analysis processing; and identifying the wafer image with the special shape in the yield.
And the analysis decision unit 3 is connected with the calculation module 22, and the analysis decision unit 3 is used for forming an analysis conclusion and/or data information of a reference decision according to the calculation analysis of the calculation module 22. In an embodiment of the present invention, the data information of the analysis conclusion and/or the reference decision includes: whether the defect number of the wafer exceeds the early warning information of the set datum line or not; a rejection suggestion for early warning the rejection of the wafer; mortality report information; forming machine early warning and maintenance suggestion information; cause information of low yield of the wafer, and the like.
Referring to fig. 5, the electronic device of the present invention includes a processor 4 and a memory 5, where the memory 5 stores program instructions, and the processor 4 executes the program instructions to implement the defect analysis method for the wafer. The Processor 4 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component; the Memory 5 may include a Random Access Memory (RAM), and may also include a Non-Volatile Memory (Non-Volatile Memory), such as at least one disk Memory. The Memory 5 may also be an internal Memory of Random Access Memory (RAM) type, and the processor 4 and the Memory 5 may be integrated into one or more independent circuits or hardware, such as: application Specific Integrated Circuit (ASIC). It should be noted that the computer program in the memory 5 can be implemented in the form of software functional units and stored in a computer readable storage medium when the computer program is sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention.
Referring to fig. 6, a storage medium 6 of the present invention has stored thereon computer instructions 7, wherein the computer instructions 7 are used for causing a computer to execute the method for analyzing the defects of the wafer. The computer-readable storage medium 6 may be: an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system or propagation medium. The computer-readable storage medium 6 may also include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Optical disks may include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-RW), and DVD.
In summary, the invention can improve the analysis speed and the analysis accuracy of the original defect analysis system, and the automatic defect identification system added with the wafer replaces the original manual identification classification method, and can utilize the lethality calculation library to perform automatic index calculation, which can feed back the analysis result in time and make a corresponding decision. Moreover, the whole defect analysis system can be coordinated uniformly, and the problems of subjective error of different engineers in the analysis process, low efficiency of mutual cooperation and overall planning and the like are avoided.
The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that are not thought of through the inventive work should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope defined by the claims.
Claims (10)
1. A method for analyzing defects of a wafer is characterized by comprising the following steps:
establishing a defect automatic identification system of the wafer;
collecting the lethality data of various defects of the wafer to form a lethality calculation library;
automatically identifying and classifying the wafer surface defect sample pictures scanned by the machine according to the automatic defect identification system; and
according to the mortality calculation library, calculating and analyzing the classified wafer surface defect sample pictures;
data information of the analysis conclusions and/or reference decisions is formed.
2. The method for analyzing the defects of the wafer according to claim 1, wherein the step of establishing the automatic defect recognition system comprises:
collecting various types of wafer surface defect picture data;
preprocessing the wafer surface defect picture data, and classifying and labeling according to defect types;
and forming a defect identification model, and performing parameter training by using a neural network method.
3. The method for analyzing defects of a wafer according to claim 2, wherein the step of forming the mortality calculation library comprises:
collecting defect information of the wafer in a current chip area, wherein the current chip area comprises a central chip area, a first adjacent chip area and a second adjacent chip area, and the first adjacent chip area and the second adjacent chip area are arranged on the periphery of the central chip area in a staggered mode;
respectively counting yield loss conditions of the central chip area, the first adjacent chip area and the second adjacent chip area, and calculating corresponding fatality rate data;
the current calculated library of mortality for defects is: the fatality rates of the central chip area, the first adjacent chip area and the second adjacent chip area are respectively multiplied by the defect number of the corresponding area, and the sum is divided by the total defect number of the current chip area.
4. The method for analyzing the defects of the wafer according to claim 2, wherein the step of automatically identifying and classifying the sample pictures of the defects on the surface of the wafer according to the automatic defect identification system comprises:
and re-labeling the defect type information of the wafer surface defect sample pictures which are identified incorrectly or not classified, and performing parameter training of the defect identification model.
5. The method for analyzing the defects of the wafer according to claim 4, wherein the step of automatically identifying and classifying the wafer surface defect sample picture further comprises:
feeding back the accurately identified wafer surface defect sample picture to the defect identification model;
through the defect identification model, sample collection is carried out on the wafer surface defect sample picture which is accurately identified, and a sample label is added according to the defect type;
performing parameter training on the defect identification model;
model parameters in the sample labels are derived.
6. The method for analyzing the defects of the wafer according to claim 1, wherein the content of the calculation analysis of the classified wafer surface defect sample pictures comprises:
calculating whether the total defect number of each wafer exceeds a set reference line or not;
calculating the predicted yield loss data of each wafer;
calculating the lethality data of each defect on the wafer with different densities and sizes;
collecting the defect information and the station passing information of the wafer to perform machine station difference analysis processing;
and identifying the wafer image with the special shape of the good product rate.
7. The method of claim 6, wherein the step of calculating the mortality data for each defect on the wafer for different densities and sizes comprises:
collecting defect information of the wafer;
calculating the defect size or defect density information of each defect on the wafer in groups;
obtaining a grouping standard of the defect size or the defect density, and counting the number of the defects with different defect sizes or defect densities;
the mortality of the defects was calculated under a grouping criterion of different defect sizes or defect densities.
8. The method of analyzing defects of a wafer according to claim 7, wherein the step of performing a group calculation on the defect size or defect density information comprises:
randomly selecting k points as a clustering center, wherein k is less than 10;
calculating the clustering of each point to k clustering centers respectively;
assigning the point to the nearest cluster center, thus forming k clusters;
recalculating the centroid of each cluster;
repeating the step of recalculating the centroid of each cluster for 2-4 times until the position of the centroid is no longer changed or a set number of iterations is reached;
the k value for the best group is obtained and the range of values for each group is given.
9. The method of claim 8, wherein forming the data information of the analysis conclusion and/or the reference decision comprises:
forming prompt early warning information according to whether the defect number of the wafer exceeds a set reference line;
according to the fatality rate calculation library of various defects of the wafer, early warning is carried out on the scrappage of the wafer, and scrappage suggestion information is provided;
analyzing according to the yield loss, defect type, defect density and defect size data of the wafer to form mortality report information;
forming machine early warning and maintenance suggestion information according to machine difference analysis;
and calculating and analyzing the cause information of low yield according to the wafer surface defect picture matched with the wafer picture of the special shape of the yield.
10. A system for using the method for analyzing a defect of a wafer according to any one of claims 1 to 9, comprising:
the automatic defect identification unit comprises a model training module and an identification classification module, wherein the model training module is used for forming a defect identification model and performing parameter training according to the classified wafer surface defect pictures, and the identification classification module is used for identifying and classifying wafer surface defect sample pictures scanned by a machine;
the calculation unit comprises a mortality calculation base module and a calculation module, wherein the mortality calculation base module is used for collecting the mortality data of various defects of the wafer to form a mortality calculation base; the calculation module is respectively connected with the mortality calculation base module and the identification and classification module, and is used for calculating and analyzing the classified wafer surface defect sample pictures according to the mortality calculation base;
and the analysis decision unit is connected with the calculation module and is used for forming an analysis conclusion and/or data information of a reference decision according to the calculation analysis of the calculation module.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112991268A (en) * | 2021-02-09 | 2021-06-18 | 上海众壹云计算科技有限公司 | Rapid screening method for target defects on wafer, device and system thereof, storage medium and electronic equipment |
| CN113077462A (en) * | 2021-04-30 | 2021-07-06 | 上海众壹云计算科技有限公司 | Wafer defect classification method, device, system, electronic equipment and storage medium |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556598A (en) * | 2009-05-08 | 2009-10-14 | 中国矿业大学 | Radiographic testing weld image management system and auxiliary film viewing method |
| CN103187329A (en) * | 2011-12-28 | 2013-07-03 | 无锡华润上华科技有限公司 | Analytical method of wafer yield |
| CN103745234A (en) * | 2014-01-23 | 2014-04-23 | 东北大学 | Band steel surface defect feature extraction and classification method |
| CN105990170A (en) * | 2015-01-28 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Wafer yield analysis method and device |
| CN110414538A (en) * | 2019-07-24 | 2019-11-05 | 京东方科技集团股份有限公司 | Defect classification method, defect classification based training method and device thereof |
| CN110456003A (en) * | 2019-08-23 | 2019-11-15 | 武汉新芯集成电路制造有限公司 | Wafer defect analysis method and system, analytical method of wafer yield and system |
| CN110766660A (en) * | 2019-09-25 | 2020-02-07 | 上海众壹云计算科技有限公司 | Integrated circuit defect image recognition and classification system based on fusion depth learning model |
| CN111052332A (en) * | 2017-09-01 | 2020-04-21 | 科磊股份有限公司 | Training learning-based defect classifier |
-
2020
- 2020-12-03 CN CN202011391617.2A patent/CN112200806A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556598A (en) * | 2009-05-08 | 2009-10-14 | 中国矿业大学 | Radiographic testing weld image management system and auxiliary film viewing method |
| CN103187329A (en) * | 2011-12-28 | 2013-07-03 | 无锡华润上华科技有限公司 | Analytical method of wafer yield |
| CN103745234A (en) * | 2014-01-23 | 2014-04-23 | 东北大学 | Band steel surface defect feature extraction and classification method |
| CN105990170A (en) * | 2015-01-28 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Wafer yield analysis method and device |
| CN111052332A (en) * | 2017-09-01 | 2020-04-21 | 科磊股份有限公司 | Training learning-based defect classifier |
| CN110414538A (en) * | 2019-07-24 | 2019-11-05 | 京东方科技集团股份有限公司 | Defect classification method, defect classification based training method and device thereof |
| CN110456003A (en) * | 2019-08-23 | 2019-11-15 | 武汉新芯集成电路制造有限公司 | Wafer defect analysis method and system, analytical method of wafer yield and system |
| CN110766660A (en) * | 2019-09-25 | 2020-02-07 | 上海众壹云计算科技有限公司 | Integrated circuit defect image recognition and classification system based on fusion depth learning model |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112991268A (en) * | 2021-02-09 | 2021-06-18 | 上海众壹云计算科技有限公司 | Rapid screening method for target defects on wafer, device and system thereof, storage medium and electronic equipment |
| CN115115564A (en) * | 2021-03-09 | 2022-09-27 | 中国科学院微电子研究所 | Wafer defect classification method and wafer defect classification device |
| CN113157666A (en) * | 2021-04-15 | 2021-07-23 | 筏渡(上海)科技有限公司 | Method and device for establishing wafer yield problem database |
| CN113077462A (en) * | 2021-04-30 | 2021-07-06 | 上海众壹云计算科技有限公司 | Wafer defect classification method, device, system, electronic equipment and storage medium |
| CN113077462B (en) * | 2021-04-30 | 2024-05-10 | 上海众壹云计算科技有限公司 | Wafer defect classification method, device, system, electronic equipment and storage medium |
| CN113222967A (en) * | 2021-05-28 | 2021-08-06 | 长江存储科技有限责任公司 | Wafer detection method and system |
| CN113487548A (en) * | 2021-06-29 | 2021-10-08 | 嵊州市浙江工业大学创新研究院 | Product defect detection method based on YOLO-v3 |
| CN113626497A (en) * | 2021-08-03 | 2021-11-09 | 上海哥瑞利软件股份有限公司 | Box diagram-based semiconductor problem machine positioning system and positioning method |
| CN113610155A (en) * | 2021-08-06 | 2021-11-05 | 上海众壹云计算科技有限公司 | Wafer defect classification method and device based on similarity comparison model, electronic equipment and storage medium |
| CN113610155B (en) * | 2021-08-06 | 2024-05-31 | 上海众壹云计算科技有限公司 | Wafer defect classification method and device based on similarity comparison model, electronic equipment and storage medium |
| CN115100163A (en) * | 2022-07-05 | 2022-09-23 | 江苏泰治科技股份有限公司 | Wafer defect identification method and device |
| CN117409001A (en) * | 2023-12-14 | 2024-01-16 | 合肥晶合集成电路股份有限公司 | Bubble analysis method and analysis device for wafer bonding |
| CN117409001B (en) * | 2023-12-14 | 2024-04-05 | 合肥晶合集成电路股份有限公司 | Bubble analysis method and analysis device for wafer bonding |
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