CN112187120A - Output circuit of PWM-saving control port - Google Patents
Output circuit of PWM-saving control port Download PDFInfo
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- CN112187120A CN112187120A CN202010846707.XA CN202010846707A CN112187120A CN 112187120 A CN112187120 A CN 112187120A CN 202010846707 A CN202010846707 A CN 202010846707A CN 112187120 A CN112187120 A CN 112187120A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
- H02P7/03—Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
- H02P7/03—Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors
- H02P7/04—Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors by means of a H-bridge circuit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
- H02P7/06—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current
- H02P7/18—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power
- H02P7/24—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices
- H02P7/28—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices
- H02P7/285—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only
- H02P7/29—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only using pulse modulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses an output circuit of a PWM (pulse width modulation) saving control port, which comprises four paths of two-input NOR gate logic chips, wherein the input ends of the fourth paths of NOR gates are connected together, PWM signals are input into the fourth paths of NOR gates, the output end of each PWM signal is electrically connected with the input end of one of the first paths of NOR gates, and the output end of each PWM signal is electrically connected with one of the input ends of the second paths of NOR gates. The invention relates to the technical field of direct current motor control, and discloses an output circuit of a PWM (pulse width modulation) saving control port, which can realize positive and negative rotation of a motor by causing the exchange of output PWM signals and low levels through the conversion of high and low levels, thereby realizing the occupation of one path of PWM control signal port.
Description
Technical Field
The invention relates to the technical field of direct current motor control, in particular to an output circuit of a PWM (pulse width modulation) saving control port.
Background
The motor is widely applied in daily life, the motor is applied to various devices, the motor is divided into a plurality of types, one of the direct current motors is the direct current motor, the direct current motor is a rotating motor which can convert direct current electric energy into mechanical energy (a direct current motor) or convert mechanical energy into direct current electric energy (a direct current generator), the direct current motor can realize the mutual conversion of the direct current electric energy and the mechanical energy, and when the direct current motor is used as a motor to run, the direct current motor converts the electric energy into the mechanical energy; the structure of the direct current motor is composed of a stator and a rotor, the part which is still when the direct current motor runs is called the stator, the stator mainly has the function of generating a magnetic field and is composed of a machine base, a main magnetic pole, a commutating pole, an end cover, a bearing, an electric brush device and the like. The rotating part is called as rotor, which mainly generates electromagnetic torque and induced electromotive force and is the pivot of energy conversion of DC motor, so it is usually called as armature, composed of rotating shaft, armature iron core, armature winding, commutator and fan, the control chip is usually needed to have multi-channel PWM output function in DC motor control, and the motor speed and the exchange of PWM signal in left and right bridge arms are regulated by PWM to realize the control of positive and negative rotation of motor.
However, the existing control scheme of the direct current motor has some defects when in use, and the existing control scheme selects a main chip with abundant peripheral devices, so that although the problem of shortage of the PWM can be solved, the cost is higher, the use on low-cost products is not facilitated, and the defects are not correspondingly improved.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides an output circuit with a PWM (pulse width modulation) saving control port, which solves the problem that the existing control scheme selects a main chip with abundant peripheral equipment, although the problem of PWM shortage can be solved, the use of the output circuit on a low-cost product is not facilitated due to higher cost.
In order to achieve the purpose, the invention is realized by the following technical scheme: the utility model provides an output circuit of province PWM control mouth, includes four ways two input NOR gate logic chip, the input of fourth way NOR gate links together, and inputs the PWM signal in the fourth way NOR gate, the output of PWM signal and one of them input electric connection of first way NOR gate, and the output of PWM signal and one of them input electric connection of second way NOR gate, two inputs of third way NOR gate and another way input of second way NOR gate link together, and two inputs of third way NOR gate and another way input high or low level of second way NOR gate, the output of level and another input electric connection of first way NOR gate.
Preferably, the input of a PWM signal and a high-low level signal does not need to provide any external circuit.
Preferably, the output ends of the first nor gate and the second nor gate simultaneously obtain PWM and low level output signals.
Preferably, the PWM and the low level output signal are used by a driving circuit of the power supply.
Preferably, in the four-way two-input nor gate, the input pin of the first-way nor gate is AB, the output pin is J, in the four-way two-input nor gate, the input pin of the second-way nor gate is CD, the output pin is K, in the four-way two-input nor gate, the input pin of the third-way nor gate is EF, and the output pin is L.
Preferably, in the four-way two-input nor gate, an input pin of a fourth-way nor gate is HG, and an output pin is M.
Preferably, when two input ends HG of the fourth nor gate input PWM signals, and two input ends EF of the third nor gate input high levels, the fourth nor gate output M, the first nor gate input B, and the second nor gate input C obtain PWM signals opposite in phase to the fourth nor gate input HG; the output end L of the third NOR gate and the other input end A of the first NOR gate obtain low level, the output end K of the second NOR gate also obtains low level after internal logic operation, and the output end J of the first NOR gate obtains PWM signals with the same phase as the input end HG of the fourth NOR gate.
Preferably, when two input ends HG of the fourth nor gate input PWM signals, two input ends EF of the third nor gate input PWM signals, the fourth nor gate output M, the first nor gate input end B, and the second nor gate input end C obtain PWM signals opposite in phase to the fourth nor gate input end HG, the third nor gate output L and the first nor gate input end a obtain high levels, the second nor gate output K obtains PWM signals in phase with the fourth nor gate input end HG, and the first nor gate output J obtains low levels after internal logic operation.
Advantageous effects
The invention provides an output circuit of a PWM-saving control port, which has the following beneficial effects compared with the prior art:
this economize output circuit of PWM control mouth, through four ways two input NOR gate collocation PWM signal of the same kind and high-low level signal of the same kind obtain the same phase PWM signal of the same kind and low level of the same kind all the way, the transform of high-low level can arouse the exchange of output PWM signal and low level, realize the motor just reversing, and then realize the occupation of the PWM control signal port of the same kind of province, in general motor control circuit, realize the control of the just reversing of motor and speed, need occupy two way PWM interfaces and two way IO mouths, only occupy PWM of the same kind and IO mouth of the same kind in this design and can realize the control of the motor just reversing and speed, the setting is simple, effectively reduce product manufacturing cost, improve the market competition of product.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides four technical solutions:
example one
The utility model provides an output circuit of province PWM control mouth, includes four ways two input UI, the input HG of fourth way links together, and the input PWM signal of fourth way, the output M and the input B electric connection of first way of PWM signal, and the output and the input C electric connection of second way of PWM signal, third way input EF and second way input D link together, and third way input and second way input high or low level, the output L and the input A electric connection of first way of output of level.
Furthermore, a PWM signal and a high-low level signal are input, and any external circuit is not required to be provided.
Further, the output end J of the first path and the output end K of the second path obtain output signals of PWM and low level at the same time.
Further, the PWM and the low-level output signal are used by a driving circuit of the motor.
Further, in the four-way two-input, the first input pin is AB, the output pin is J, in the four-way two-input, the second input pin is CD, the output pin is K, in the four-way two-input, the third input pin is EF, and the output pin is L.
Further, in the four-way and two-input circuit, the fourth input pin is HG, and the output pin is M.
Further, when the fourth input end HG inputs a PWM signal and the third EF inputs a high level, the fourth output end M, the first input end B, and the second input end C obtain a PWM signal in phase opposite to the fourth input end HG; the third output end L and the first input end A obtain low level, the second output end K also obtains low level after internal logic operation, and the first output end J obtains PWM signals with the same phase as the fourth input end HG.
Further, when two input ends HG of the fourth path input PWM signals, and two input ends EF of the third path input low levels, the output end M of the fourth path, the input end B of the first path, and the input end C of the second path obtain PWM signals in phase opposition to the input end HG of the fourth path, the output end L of the third path and the input end a of the first path obtain high levels, the output end K of the second path obtain PWM signals in phase with the input end HG of the fourth path, and the output end J of the first path obtains low levels after internal logic operation.
Example two
The utility model provides an output circuit who economizes PWM control mouth, including NOR gate logic chip UI, the input HG of NOR gate links together, and input PWM signal in the NOR gate, the output M of PWM signal and the input B electric connection of NOR gate, and the output M of PWM signal and the input C electric connection of NOR gate, the input EF of NOR gate and another way input D of NOR gate link together, and the third route input EF of NOR gate and another way input D input high or low level of NOR gate, the output L of level and another input A electric connection of NOR gate.
Furthermore, a PWM signal and a high-low level signal are input, and any external circuit is not required to be provided.
Further, the output end J of the first path of NOR gate and the output end K of the second path of NOR gate simultaneously obtain PWM and low level output signals.
Further, the PWM and the low-level output signal are used by a driving circuit of the motor.
Further, in the nor gate, an input pin of the nor gate is AB, an output pin of the nor gate is J, in the nor gate, an input pin of the second nor gate is CD, an output pin of the nor gate is K, and in the nor gate, an input pin of the nor gate is EF, and an output pin of the nor gate is L.
Further, in the nor gate, an input pin of the nor gate is HG, and an output pin of the nor gate is M.
Further, when the input end HG of the nor gate inputs a PWM signal, and the input end EF of the nor gate inputs a high level, the output end M of the nor gate and the input end B of the nor gate and the input end C of the nor gate obtain a PWM signal opposite to the input end HG of the nor gate; the output end L of the NOR gate and the other input end A of the NOR gate obtain low level, the output end K of the NOR gate also obtains low level after internal logic operation, and the output end J of the NOR gate obtains PWM signals which are in the same phase with the input end HG of the fourth NOR gate.
Further, when two input ends HG of the nor gate input PWM signals, and two input ends EF of the nor gate input low levels, the input end C of the nor gate output end M of the nor gate input end B of the nor gate obtains a PWM signal opposite to the input end HG of the nor gate, the other input end a of the nor gate output end L of the nor gate obtains a high level, the output end K of the nor gate obtains a PWM signal in phase with the input end HG of the nor gate, and the output end J of the nor gate obtains a low level after internal logic operation.
EXAMPLE III
The utility model provides an output circuit who economizes PWM control mouth, including four ways two input UI, the input HG of NOR gate links together, and input PWM signal in the NOR gate, PWM signal's output M and the input B electric connection of NOR gate, and PWM signal's output and the input C electric connection of NOR gate, input EF of NOR gate and another way input D of NOR gate link together, and input EF of NOR gate and another way input D input high or low level of NOR gate, output L and another input A electric connection of NOR gate.
Furthermore, a PWM signal and a high-low level signal are input, and any external circuit is not required to be provided.
Further, the output end J of the first path of the nor gate and the output end K of the second path of the nor gate simultaneously obtain output signals of PWM and low level.
Further, the PWM and the low-level output signal are used by a driving circuit of the motor.
Further, in the four-way two-input, the first input pin is AB, the output pin is J, in the four-way two-input, the second input pin is CD, the output pin is K, in the four-way two-input, the third input pin is EF, and the output pin is L.
Further, in the four-way and two-input circuit, the fourth input pin is HG, and the output pin is M.
Further, when two input ends HG of the fourth path input PWM signals, and two input ends EF of the third path input high levels, the fourth path output end M and the first path input end B and the nor input end C obtain PWM signals opposite in phase to the nor input end HG; the output end L of the third path and the other input end A of the NOR gate obtain low level, the output end K of the second path also obtains low level after internal logic operation, and the output end J of the first path obtains PWM signals in the same phase with the input end HG of the NOR gate.
Furthermore, when two input ends HG of the fourth path input PWM signals, and two input ends EF of the third path input low levels, the fourth path output end M and the first path input end B and the input end C of the nor gate obtain PWM signals opposite to the nor gate input end HG, the nor gate output end L and the other input end a of the nor gate obtain high levels, the output end K of the nor gate obtains PWM signals in the same phase as the nor gate input end HG, and the output end J of the first path obtains low levels after internal logic operation.
Example four
The utility model provides an output circuit who economizes PWM control mouth, including NOR gate logic chip UI, the input HG of NOR gate links together, and input PWM signal in the NOR gate, PWM signal's output M and the input B electric connection of NOR gate, and PWM signal's output and the input C electric connection of NOR gate, input EF of NOR gate and another way input D of NOR gate link together, and input EF of NOR gate and another way input D input high or low level of NOR gate, the output L of level and another input A electric connection of NOR gate.
Furthermore, a PWM signal and a high-low level signal are input, and any external circuit is not required to be provided.
Further, the output end J of the first path of the nor gate and the output end K of the second path of the nor gate simultaneously obtain output signals of PWM and low level.
Further, the PWM and the low-level output signal are used by a driving circuit of the motor.
Further, in the nor gate, an input pin of the nor gate is AB, an output pin of the nor gate is J, in the nor gate, an input pin of the second nor gate is CD, an output pin of the nor gate is K, in the nor gate, an input pin of the nor gate is EF, and an output pin of the nor gate is L.
Further, in the nor gate, an input pin of the nor gate is HG, and an output pin of the nor gate is M.
Further, when two input ends HG of the fourth path input PWM signals, and two input ends EF of the nor gate input high levels, the nor gate output end M, the nor gate input end B, and the second path input end C obtain PWM signals in phase opposition to the fourth path input end HG; the output end L of the third path and the other input end A of the first path obtain low level, the output end K of the NOR gate obtains low level after internal logic operation, and the output end J of the NOR gate obtains PWM signals with the same phase as the input end HG of the fourth path.
Further, when two input ends HG of the nor gate input PWM signals, and two input ends EF of the nor gate input low levels, the nor gate output end M, the nor gate input end B, and the second input end C obtain PWM signals in phase opposition to the fourth nor gate input end HG; the output end L of the NOR gate and the other input end A of the first path obtain high level; an output end K of the NOR gate obtains a PWM signal which is in the same phase with an input end HG of the NOR gate; and the output end J of the NOR gate obtains low level after internal logic operation.
And those not described in detail in this specification are well within the skill of those in the art.
When the PWM signal input circuit is used, when PWM signals are input to two input ends HG of the fourth NOR gate, and high levels are input to two input ends EF of the third NOR gate, PWM signals opposite to the phase of the PWM signals input by the fourth NOR gate are obtained by the output end M of the fourth NOR gate, the input end B of the first NOR gate and the input end C of the second NOR gate; the output end L of the third NOR gate and the other input end A of the first NOR gate obtain low level, the output end K of the second NOR gate also obtains low level after internal logic operation, and the output end J of the first NOR gate obtains PWM signals with the same phase as the input end HG of the fourth NOR gate.
When two input ends HG of the fourth NOR gate input PWM signals and two input ends EF of the third NOR gate input low level, the output end M of the fourth NOR gate, the input end B of the first NOR gate and the input end C of the second NOR gate obtain PWM signals opposite in phase to the input end HG of the fourth NOR gate; the output end L of the third NOR gate and the other input end A of the first NOR gate obtain high level; the output end K of the second NOR gate obtains PWM signals which are in the same phase with the input end HG of the fourth NOR gate; and the output end J of the first NOR gate obtains low level after internal logic operation.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. An output circuit of a PWM-saving control port comprises a four-path two-input NOR gate logic chip, and is characterized in that: the input ends of the fourth NOR gate are connected together, a PWM signal is input into the fourth NOR gate, the output end of the PWM signal is electrically connected with one input end of the first NOR gate, the output end of the PWM signal is electrically connected with one input end of the second NOR gate, two input ends of the third NOR gate are connected with the other input end of the second NOR gate, high or low levels are input into the two input ends of the third NOR gate and the other input end of the second NOR gate, and the output end of the levels is electrically connected with the other input end of the first NOR gate.
2. The output circuit of the power-saving PWM control port according to claim 1, wherein: and a path of PWM signal and a path of high-low level signal are input without providing any external circuit.
3. The output circuit of the power-saving PWM control port according to claim 1, wherein: and the output ends of the first path of NOR gate and the second path of NOR gate simultaneously obtain PWM and low level signals.
4. The output circuit of the power-saving PWM control port according to claim 3, wherein: the PWM and the low-level output signal are used by a driving circuit of the motor.
5. The output circuit of the power-saving PWM control port according to claim 1, wherein: in the four-way two-input NOR gate, the input pin of the first-way NOR gate is AB, the output pin is J, in the four-way two-input NOR gate, the input pin of the second-way NOR gate is CD, the output pin is K, in the four-way two-input NOR gate, the input pin of the third-way NOR gate is EF, and the output pin is L.
6. The output circuit of the power-saving PWM control port according to claim 1, wherein: in the four-way two-input NOR gate, the input pin of the fourth-way NOR gate is HG, and the output pin is M.
7. The output circuit of the power-saving PWM control port according to claim 1, wherein: when two input ends HG of the fourth NOR gate input PWM signals, and two input ends EF of the third NOR gate input high levels, the output end M of the fourth NOR gate, the input end B of the first NOR gate and the input end C of the second NOR gate obtain PWM signals opposite in phase to the input end HG of the fourth NOR gate; the output end L of the third NOR gate and the other input end A of the first NOR gate obtain low level, the output end K of the second NOR gate also obtains low level after internal logic operation, and the output end J of the first NOR gate obtains PWM signals with the same phase as the input end HG of the fourth NOR gate.
8. The output circuit of the power-saving PWM control port according to claim 1, wherein: when two input ends HG of the fourth NOR gate input PWM signals, two input ends EF of the third NOR gate input low levels, the output end M of the fourth NOR gate, the input end B of the first NOR gate and the input end C of the second NOR gate obtain PWM signals opposite to the input end HG of the fourth NOR gate, the output end L of the third NOR gate and the other input end A of the first NOR gate obtain high levels, the output end K of the second NOR gate obtains PWM signals which are in the same phase with the input end HG of the fourth NOR gate, and the output end J of the first NOR gate obtains low levels after internal logic operation.
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| CN202010846707.XA CN112187120A (en) | 2020-08-21 | 2020-08-21 | Output circuit of PWM-saving control port |
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| CN202010846707.XA CN112187120A (en) | 2020-08-21 | 2020-08-21 | Output circuit of PWM-saving control port |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104202034A (en) * | 2014-08-13 | 2014-12-10 | 深圳市亚泰光电技术有限公司 | Circulating multichannel selection circuit system |
| CN205176527U (en) * | 2015-12-01 | 2016-04-20 | 山东科技大学 | Many rounds of independent driven robot controllers |
| CN206452327U (en) * | 2017-01-11 | 2017-08-29 | 厦门蒙发利电子有限公司 | A kind of H bridges motor driver and motor device |
| CN208754212U (en) * | 2018-10-24 | 2019-04-16 | 重庆友斯成科技有限公司 | Direct current generator multiplex drive circuit |
-
2020
- 2020-08-21 CN CN202010846707.XA patent/CN112187120A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104202034A (en) * | 2014-08-13 | 2014-12-10 | 深圳市亚泰光电技术有限公司 | Circulating multichannel selection circuit system |
| CN205176527U (en) * | 2015-12-01 | 2016-04-20 | 山东科技大学 | Many rounds of independent driven robot controllers |
| CN206452327U (en) * | 2017-01-11 | 2017-08-29 | 厦门蒙发利电子有限公司 | A kind of H bridges motor driver and motor device |
| CN208754212U (en) * | 2018-10-24 | 2019-04-16 | 重庆友斯成科技有限公司 | Direct current generator multiplex drive circuit |
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