CN112186317A - Combiner - Google Patents

Combiner Download PDF

Info

Publication number
CN112186317A
CN112186317A CN202011025732.8A CN202011025732A CN112186317A CN 112186317 A CN112186317 A CN 112186317A CN 202011025732 A CN202011025732 A CN 202011025732A CN 112186317 A CN112186317 A CN 112186317A
Authority
CN
China
Prior art keywords
port
circuit
switch circuit
electrically connected
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011025732.8A
Other languages
Chinese (zh)
Other versions
CN112186317B (en
Inventor
唐剑奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Lixun Technology Co ltd
Original Assignee
Kunshan Luxshare RF Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunshan Luxshare RF Technology Co Ltd filed Critical Kunshan Luxshare RF Technology Co Ltd
Priority to CN202011025732.8A priority Critical patent/CN112186317B/en
Publication of CN112186317A publication Critical patent/CN112186317A/en
Application granted granted Critical
Publication of CN112186317B publication Critical patent/CN112186317B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/20—Frequency-selective devices, e.g. filters
    • H01P1/213—Frequency-selective devices, e.g. filters combining or separating two or more different frequencies
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/50—Circuits using different frequencies for the two directions of communication
    • H04B1/52—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/54—Circuits using the same frequency for two directions of communication
    • H04B1/58—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa

Abstract

The embodiment of the invention discloses a combiner. The combiner comprises a first port, a second port, a third port, a first filter, a second filter, a first switch circuit, a second switch circuit and a logic interlocking control circuit, wherein the first switch circuit is connected between the first port and the third port, the first switch circuit is connected or disconnected between the first port and the third port according to a control signal, the second switch circuit is connected between the second port and the third port, the second switch circuit is connected or disconnected between the second port and the third port according to the control signal, the logic interlocking control circuit is used for collecting the voltages of the first port and the second port, and when the voltage of the first port is different from the voltage of the second port in logic state, a control signal is output to control the first switch circuit or the second switch circuit to be connected. The technical scheme provided by the invention realizes the automatic switching of the power supply and the communication link from the shunt port to the combiner port of the combiner.

Description

Combiner
Technical Field
The embodiment of the invention relates to the technical field of circuits, in particular to a combiner.
Background
With the function upgrade of the communication base station, new requirements are continuously put forward on the combiner of the network optimization system device. The existing active combiner is composed of a passive-passive two-in-one combiner and an active control unit, and the existing combiner can not meet the requirement that a communication base station has an intelligent power supply and a communication channel two-out function on the combiner.
The problem that the existing combiner cannot meet the requirement that a combiner of a communication base station has an intelligent power supply and a communication channel alternative function becomes a problem to be solved urgently in the industry.
Disclosure of Invention
The embodiment of the invention provides a combiner, which is used for solving the problem that the existing combiner cannot meet the requirement that a communication base station has an intelligent power supply and a communication channel for the combiner.
In order to realize the technical problem, the invention adopts the following technical scheme:
an embodiment of the present invention provides a combiner, including: a first port, a second port, and a third port;
a first filter and a second filter, the first filter being connected between the first port and the third port, the second filter being connected between the second port and the third port;
a first switch circuit and a second switch circuit, the first switch circuit being connected between the first port and the third port, the first switch circuit being configured to turn on or off the connection between the first port and the third port according to a control signal; the second switch circuit is connected between the second port and the third port, and is configured to turn on or off the connection between the second port and the third port according to the control signal;
and the logic interlocking control circuit is configured to collect the voltages of the first port and the second port, and output a control signal to control the first switch circuit or the second switch circuit to be conducted when the logic states of the voltage of the first port and the voltage of the second port are different.
Further, the logic interlock control circuit includes: the logic interlock switch circuit, the first voltage sampling circuit and the second voltage sampling circuit;
the first voltage sampling circuit is connected between the first port and the first switch circuit and is configured to collect a voltage signal input by the first port; the second voltage sampling circuit is connected between the second port and the second switch circuit and is configured to collect a voltage signal input by the second port;
and the logic interlocking switch circuit is configured to acquire the voltage of the first port through the first voltage sampling circuit and acquire the voltage of the second port through the second voltage sampling circuit.
Furthermore, the circuit structures of the first voltage sampling circuit and the second voltage sampling circuit are the same;
the first voltage sampling circuit comprises a first resistor and a second resistor;
the first end of the first resistor is electrically connected with the input end of the voltage sampling circuit and the second output end of the first voltage sampling circuit, the second end of the first resistor is electrically connected with the first end of the second resistor and the first output end of the first voltage sampling circuit, and the second end of the second resistor is grounded.
Furthermore, a first input end of the logic interlocking switch circuit is electrically connected with a first output end of the first voltage sampling circuit; the second input end of the logic interlocking switch circuit is electrically connected with the first output end of the second voltage sampling circuit; the third input end of the logic interlocking switch circuit is electrically connected with the input end of the first voltage sampling circuit and the input end of the second voltage sampling circuit;
the first output end of the logic interlocking switch circuit is electrically connected with the control end of the first switch circuit; and the second output end of the logic interlocking switch circuit is electrically connected with the control end of the second switch circuit.
Further, the logic interlock switch circuit is configured to:
when the voltage of the first port and the voltage of the second port are in different logic states and the voltage of the first port is in a high level, a first output end of the logic interlocking switch circuit outputs a control signal to control the first switch circuit to be switched on and control the second switch circuit to be kept in a switched-off state;
when the voltage of the first port and the voltage of the second port are in different logic states and the voltage of the second port is in a high level, the second output end of the logic interlocking switch circuit outputs a control signal to control the second switch circuit to be switched on and control the first switch circuit to keep a switched-off state.
Furthermore, the logic interlocking switch circuit comprises a first comparison unit, a second comparison unit, a first NOT gate, a second NOT gate, a first AND gate and a second AND gate;
the first input end of the first comparison unit is electrically connected with the first input end of the logic interlocking switch circuit; the first input end of the second comparison unit is electrically connected with the second input end of the logic interlocking switch circuit; the second input end of the first comparison unit and the second input end of the second comparison unit are respectively and electrically connected with the third input end of the logic interlocking switch circuit, and the second input end of the first comparison unit and the second input end of the second comparison unit are respectively used for inputting reference voltage;
the output end of the first comparison unit is electrically connected with the first input end of the second AND gate through the second NOT gate, and the second input end of the second AND gate is electrically connected with the output end of the second comparison unit;
the output end of the second comparison unit is electrically connected with the second input end of the first AND gate through the first NOT gate, and the first input end of the first AND gate is electrically connected with the output end of the first comparison unit;
the output end of the first AND gate is electrically connected with the first output end of the logic interlocking switch circuit; and the output end of the second AND gate is electrically connected with the second output end of the logic interlocking switch circuit.
Further, the combiner further includes: a slow start circuit and a DC/DC circuit;
the input end of the slow starting circuit is respectively and electrically connected with the first input end of the first voltage sampling circuit and the first input end of the second voltage sampling circuit; the output end of the slow starting circuit is electrically connected with the third input end of the logic interlocking switch circuit through a DC/DC circuit;
the DC/DC circuit is used for converting the received voltage signal output by the slow starting circuit into a low-voltage electric signal and providing a reference voltage for the third input end of the logic interlocking switch circuit.
Furthermore, the slow starting circuit comprises a fifth switching tube, a seventh resistor, an eighth resistor and a ninth resistor;
the first end of the fifth switching tube is electrically connected with the input end of the slow starting circuit, the second end of the fifth switching tube is electrically connected with the first end of the fifth switching tube through a seventh resistor, and the second end of the fifth switching tube is electrically connected with the output end of the slow starting circuit;
the control end of the fifth switch tube is electrically connected with the first end of the eighth resistor and the first end of the ninth resistor, the second end of the eighth resistor is electrically connected with the input end of the slow starting circuit, and the second end of the ninth resistor is grounded.
Furthermore, the circuit structures of the first switch circuit and the second switch circuit are the same;
the first switching circuit comprises a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;
the first end of the first switching tube is electrically connected with the first end of the second switching tube, and the second end of the first switching tube is electrically connected with the first end of the first switching circuit;
the control end of the first switching tube is electrically connected with the second end of the first switching tube through a third resistor, and the control end of the first switching tube is electrically connected with the first end of the third switching tube through a fourth resistor; the second end of the third switching tube is grounded, and the control end of the third switching tube is electrically connected with the control end of the fourth switching tube and the control end of the first switching circuit;
the first end of the fourth switch tube is electrically connected with the control end of the second switch tube through a sixth resistor, and the control end of the second switch tube is electrically connected with the second end of the second switch tube and the second end of the first switch circuit through a fifth resistor.
Further, the combiner further includes: the lightning protection circuit comprises a first lightning protection circuit, a second lightning protection circuit and a third lightning protection circuit;
the first lightning protection circuit is connected between the first port and the first filter;
the second lightning protection circuit is connected between the second port and the second filter;
the first filter and the second filter are electrically connected with the third port through a third lightning protection circuit.
The combiner provided by the embodiment of the invention comprises a first port, a second port, a third port, a first filter, a second filter, a first switch circuit, a second switch circuit and a logic interlock control circuit, wherein the first filter is connected between the first port and the third port, the second filter is connected between the second port and the third port, the first switch circuit is connected between the first port and the third port, the first switch circuit is configured to turn on or off the connection between the first port and the third port according to a control signal, the second switch circuit is connected between the second port and the third port, the second switch circuit is configured to turn on or off the connection between the second port and the third port according to the control signal, the logic interlock control circuit is configured to collect the voltages of the first port and the second port, and when the voltage of the first port is different from the logic state of the voltage of the second port, the output control signal controls the first switch circuit or the second switch circuit to be conducted. The combiner realizes the automatic switching of the power supply and the communication link from the branch port to the combiner port, and solves the problem that the existing combiner can not meet the requirement that a communication base station has an intelligent power supply and a communication channel for the combiner.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a combiner according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another combiner according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another combiner according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another combiner provided in the embodiment of the present invention;
fig. 5 is a schematic structural diagram of another combiner provided in the embodiment of the present invention;
fig. 6 is a schematic structural diagram of a logic interlock switch circuit of a combiner according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another combiner according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a slow start circuit of a combiner according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a slow start circuit of another combiner according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a first switch circuit of a combiner according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of another combiner according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a first lightning protection circuit of a combiner according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a combiner according to an embodiment of the present invention. Referring to fig. 1, a combiner according to an embodiment of the present invention includes a first port 1, a second port 2, a third port 3, a first filter 4, a second filter 5, a first switch circuit 6, a second switch circuit 7, and a logic interlock control circuit 8, where the first filter 4 is connected between the first port 1 and the third port 3, the second filter 5 is connected between the second port 2 and the third port 3, the first switch circuit 6 is connected between the first port 1 and the third port 3, the first switch circuit 6 is configured to turn on or off a connection between the first port 1 and the third port 3 according to a control signal, the second switch circuit 7 is connected between the second port 2 and the third port 3, the second switch circuit 7 is configured to turn on or off a connection between the second port 2 and the third port 3 according to the control signal, the logic interlock control circuit 8 is configured to collect voltages of the first port 1 and the second port 2, and when the logic states of the voltage of the first port 1 and the voltage of the second port 2 are different, the control signal is output to control the first switch circuit 6 or the second switch circuit 7 to be conducted. In an embodiment, fig. 2 is a schematic structural diagram of another combiner provided in the embodiment of the present invention. On the basis of the above-described embodiment, referring to fig. 2, the first switch circuit 6 is connected to the logic interlock control circuit 8 through the control terminal 61, the second switch circuit 7 is connected to the logic interlock control circuit 8 through the control terminal 71, the logic interlock control circuit 8 does not output a control signal or outputs a control signal according to the logic state of the voltages of the first port 1 and the second port 2, the first switch circuit 6 is configured to turn on or off the connection between the first port 1 and the third port 3 according to the control signal of the control terminal 61, and the second switch circuit 7 is configured to turn on or off the connection between the second port 2 and the third port 3 according to the control signal of the control terminal 71.
Specifically, the first port 1, the first filter 4, and the third port 3 constitute a passive filter path, and the second port 2, the second filter 5, and the third port 3 constitute a passive filter path. The first switch circuit 6, the first port 1 and the third port 3 form an active circuit, the second switch circuit 7, the second port 2 and the third port 3 form an active circuit, the logic interlock control circuit 8 can collect the voltages of the first port 1 and the second port 2, and output a control signal to the first switch circuit 6 and the second switch circuit 7 when the logic states of the voltage of the first port 1 and the voltage of the second port 2 are different, when the first switch circuit 6 conducts the connection between the first port 1 and the third port 3 according to the control signal of the control terminal 61, the second switch circuit 7 cuts off the connection between the second port 2 and the third port 3 according to the control signal of the control terminal 71; alternatively, when the first switch circuit 6 turns off the connection between the first port 1 and the third port 3 according to the control signal of the control terminal 61, the second switch circuit 7 turns on the connection between the second port 2 and the third port 3 according to the control signal of the control terminal 71.
The combiner provided by this embodiment is connected between the first port and the third port by setting the first switch circuit, the second switch circuit is connected between the second port and the third port, the voltages of the first port and the second port are collected by the logic interlock control circuit, and when the voltage of the first port is different from the logic state of the voltage of the second port, the output control signal controls the first switch circuit or the second switch circuit to be turned on, so as to realize the automatic switching of the power supply and the communication link from the shunt port to the combiner port of the combiner, and solve the problem that the existing combiner cannot meet the requirement that the communication base station has the alternative function of the intelligent power supply and the communication path.
Optionally, fig. 3 is a schematic structural diagram of another combiner provided in the embodiment of the present invention. On the basis of the above-mentioned embodiment, referring to fig. 3, the logic interlock control circuit 8 includes a first voltage sampling circuit 81 and a second voltage sampling circuit 82, and a logic interlock switch circuit 83, the first voltage sampling circuit 81 is connected between the first port 1 and the first switch circuit 6, the first voltage sampling circuit 81 is configured to collect a voltage signal input by the first port 1, the second voltage sampling circuit 82 is connected between the second port 2 and the second switch circuit 7, the second voltage sampling circuit 82 is configured to collect a voltage signal input by the second port 2, and the logic interlock switch circuit 83 is configured to collect a voltage of the first port 1 by the first voltage sampling circuit 81 and a voltage of the second port 2 by the second voltage sampling circuit 82.
Specifically, the logic interlock control circuit 8 implements communication through the logic interlock switch circuit 83, and the logic interlock switch circuit 83 outputs a control signal to control the first switch circuit 6 and the second switch circuit 7 to be turned on or off according to the logic states of the voltage of the first port 1 collected by the first voltage sampling circuit 81 and the voltage of the second port 2 collected by the second voltage sampling circuit 82.
Optionally, fig. 4 is a schematic structural diagram of another combiner provided in the embodiment of the present invention. On the basis of the above-described embodiment, referring to fig. 4, the circuit structures of the first voltage sampling circuit 81 and the second voltage sampling circuit 82 may be the same. The first voltage sampling circuit 81 may include a first resistor 84 and a second resistor 85, a first end 841 of the first resistor 84 is electrically connected to the input terminal 811 of the first voltage sampling circuit 81 and the second output terminal 813 of the first voltage sampling circuit 81, a second end 842 of the first resistor 84 is electrically connected to the first end 851 of the second resistor 85 and the first output terminal 812 of the first voltage sampling circuit 81, and a second end 852 of the second resistor 85 is grounded. The second output terminal 813 is connected to the first switch circuit 6, and the first output terminal 812 is connected to the logic interlock switch circuit 83.
Specifically, the first resistor 84 and the second resistor 85 perform voltage division, the voltage division ratio of the first resistor 84 and the second resistor 85 may be set to 10:1, and the voltage of the power supply is divided by the first resistor 84 and the second resistor 85 and then output from the second output terminal 813 and the first output terminal 812 of the first voltage sampling circuit 81. With continued reference to fig. 4, the second voltage sampling circuit 82 may also include a first resistor 84 and a second resistor 85, a first end 841 of the first resistor 84 is electrically connected to the input terminal 821 of the second voltage sampling circuit 82 and the second output terminal 823 of the second voltage sampling circuit 82, a second end 842 of the first resistor 84 is electrically connected to the first end 851 of the second resistor 85 and the first output terminal 822 of the second voltage sampling circuit 82, and a second end 852 of the second resistor 85 is grounded. The second output 823 of the second voltage sampling circuit 82 is connected to the second switch circuit 7, and the first output 822 is connected to the logic interlock switch circuit 83. The first voltage sampling circuit 81 and the second voltage sampling circuit 82 may have the same circuit structure, and the voltage of the power supply is divided by the first resistor 84 and the second resistor 85 and then output from the second output end 823 and the first output end 822 of the second voltage sampling circuit 82.
Optionally, fig. 5 is a schematic structural diagram of another combiner provided in the embodiment of the present invention. On the basis of the above embodiment, referring to fig. 5, the first input 831 of the logic interlock switch circuit 83 is electrically connected to the first output 812 of the first voltage sampling circuit 81, the second input 832 of the logic interlock switch circuit 83 is electrically connected to the first output 822 of the second voltage sampling circuit 82, the third input 833 of the logic interlock switch circuit 83 is electrically connected to the input 811 of the first voltage sampling circuit 81 and the input 821 of the second voltage sampling circuit 82, the first output 834 of the logic interlock switch circuit 83 is electrically connected to the control terminal 61 of the first switch circuit 6, and the second output 835 of the logic interlock switch circuit 83 is electrically connected to the control terminal 71 of the second switch circuit 7.
Specifically, the logic interlock switch circuit 83 collects the voltage of the first port 1 through the first input end 831, the logic interlock switch circuit 83 collects the voltage of the second port 2 through the second input end 832, and when the logic states of the voltage of the first port 1 and the voltage of the second port 2 are different, the logic interlock switch circuit 83 outputs a control signal to the first switch circuit 6 through the first output end 834, and outputs a control signal to the second switch circuit 7 through the second output end 835 of the logic interlock switch circuit 83, and when the first switch circuit 6 switches on the connection between the first port 1 and the third port 3 according to the control signal of the control end 61, the second switch circuit 7 switches off the connection between the second port 2 and the third port 3 according to the control signal of the control end 71; alternatively, when the first switch circuit 6 turns off the connection between the first port 1 and the third port 3 according to the control signal of the control terminal 61, the second switch circuit 7 turns on the connection between the second port 2 and the third port 3 according to the control signal of the control terminal 71.
Optionally, with reference to fig. 5, the logic interlock switch circuit 83 is configured to output a control signal at a first output end 834 of the logic interlock switch circuit 83 to control the first switch circuit 6 to be turned on and control the second switch circuit 7 to be kept in an off state when the logic states of the voltage of the first port 1 and the voltage of the second port 2 are different and the logic state of the voltage of the first port 1 is a high level, and output a control signal at a second output end 835 of the logic interlock switch circuit 83 to control the second switch circuit 7 to be turned on and control the first switch circuit 6 to be kept in the off state when the logic states of the voltage of the first port 1 and the voltage of the second port 2 are different and the logic state of the voltage of the second port 2 is a high level.
Specifically, when the logic states of the voltage of the first port 1 and the voltage of the second port 2 are the same, the logic interlock switch circuit 83 outputs a control signal to the first switch circuit 6 through the first output end 834 of the logic interlock switch circuit 83, and outputs a control signal to the second switch circuit 7 through the second output end 835 of the logic interlock switch circuit 83, and when the first switch circuit 6 turns off the connection between the first port 1 and the third port 3 according to the signal of the control end 61, the second switch circuit 7 turns off the connection between the second port 2 and the third port 3 according to the signal of the control end 71.
Optionally, fig. 6 is a schematic structural diagram of a logic interlock switch circuit of a combiner according to an embodiment of the present invention. On the basis of the above-described embodiment, with reference to fig. 5 and 6, the logic interlock switch circuit 83 includes a first comparison unit 836, a second comparison unit 837, a first not gate 838, a second not gate 839, a first and gate 840, and a second and gate 850; the first input terminal 8361 of the first comparing unit 836 is electrically connected to the first input terminal 831 of the logic interlock switch circuit 83; a first input terminal 8371 of the second comparing unit 837 is electrically connected with the second input terminal 832 of the logic interlock switch circuit 83; a second input terminal 8362 of the first comparing unit 836 and a second input terminal 8372 of the second comparing unit are electrically connected to the third input terminal 833 of the logic interlock switch circuit 83, respectively, and the second input terminal 8362 of the first comparing unit 836 and the second input terminal 8372 of the second comparing unit 837 are used for inputting a reference voltage, respectively; an output port 8363 of the first comparing unit 836 is electrically connected to a first input port 8501 of the second and gate 850 through a second not gate 839, and a second input port 8502 of the second and gate 850 is electrically connected to an output port 8373 of the second comparing unit 837; an output terminal 8373 of the second comparing unit 837 is electrically connected to the second input terminal 8402 of the first and gate 840 through the first not gate 838, and a first input terminal 8401 of the first and gate 840 is electrically connected to an output terminal 8363 of the first comparing unit 836; the output 8403 of the first and gate 840 is electrically connected to the first output 834 of the logic interlock switch circuit 83; the output 8503 of the second and gate 850 is electrically connected to the second output 835 of the logic interlock switch circuit 83.
Specifically, the reference voltage may be set to 0.6V, the reference voltages input to the second input terminal 8362 of the first comparing unit 836 and the second input terminal 8372 of the second comparing unit 837 may be the same, the voltage VinADC input to the first input terminal 8361 of the first comparing unit 836 is compared with the reference voltage input to the second input terminal 8362 of the first comparing unit 836, when VinADC > 0.6V, that is, Vin > 6.6V, the first comparing unit 836 outputs a high level, otherwise, outputs a low level; the voltage VinADC input from the first input terminal 8371 of the second comparing unit 837 is compared with the reference voltage input from the second input terminal 8372 of the second comparing unit 837, and when VinADC > 0.6V, that is, Vin > 6.6V, the second comparing unit 837 outputs a high level, otherwise, it outputs a low level, wherein the high level may be 3.3V, and the low level may be 0V. The level value output by the first comparing unit 836 is input to the first input terminal 8401 of the first and gate 840, the level value output by the second comparing unit 837 is inverted by the first not gate 838 and input to the second input terminal 8402 of the first and gate 840, the level value output by the second comparing unit 837 is input to the second input terminal 8502 of the second and gate 850, and the level value output by the first comparing unit 836 is inverted by the second not gate 839 and input to the first input terminal 8501 of the second and gate 850. When the logic states of the first port 1 and the second port 2 are opposite, the first and gate 840 outputs a high level and the second and gate 850 outputs a low level, or the first and gate 840 outputs a low level and the second and gate 850 outputs a high level.
Illustratively, when the first and gate 840 outputs a high level, that is, the control signal output by the first output 834 of the logic interlock switch circuit 83 is a high level, the first switch circuit 6 switches on the connection between the first port 1 and the third port 3 according to the high level signal of the control terminal 61; when the second and gate 850 outputs a low level, that is, the control signal output by the second output end 835 of the logic interlock switch circuit 83 is a low level, the second switch circuit 7 turns off the connection between the second port 2 and the third port 3 according to the low level signal of the control end 71. When the first and gate 840 outputs a low level, that is, the control signal output by the first output end 834 of the logic interlock switch circuit 83 is a low level, the first switch circuit 6 turns off the connection between the first port 1 and the third port 3 according to the low level signal of the control end 61; when the second and gate 850 outputs a high level, that is, the control signal output by the second output end 835 of the logic interlock switch circuit 83 is a high level, the second switch circuit 7 switches on the connection between the second port 2 and the third port 3 according to the high level signal of the control end 71. When the logic states of the first port 1 and the second port 2 are the same, the first and gate 840 and the second and gate 850 each output a low level. The first switch circuit 6 and the second switch circuit 7 are both turned off.
Optionally, fig. 7 is a schematic structural diagram of another combiner provided in the embodiment of the present invention. On the basis of the foregoing embodiments, referring to fig. 7, the combiner provided in this embodiment further includes a slow start circuit 9 and a DC/DC circuit 10, an input terminal 95 of the slow start circuit 9 is electrically connected to a first input terminal 811 of the first voltage sampling circuit 81 and a first input terminal 821 of the second voltage sampling circuit 82, respectively, an output terminal 96 of the slow start circuit 9 is electrically connected to a third input terminal 833 of the logic interlock switch circuit 83 through the DC/DC circuit 10, and the slow start circuit 9 is configured to suppress an inrush current of a power supply and protect the DC/DC circuit 10 from being started normally; the DC/DC circuit 10 is used to convert the received voltage signal outputted from the slow start circuit 9 into a low voltage electrical signal, and provide a reference voltage for the third input 833 of the logic interlock switch circuit 83.
Specifically, the slow start circuit 9 can effectively suppress power supply inrush current and protect the normal start of the rear-stage circuit. The DC/DC circuit 10 is used for voltage conversion, converting an input voltage of 7-32V into a system voltage of 3.3V through the chip XL 1509. It should be noted that, the combiner provided in this embodiment has no splitting function, and if a voltage signal is input from the third port 3, the voltage signal input from the third port 3 cannot be connected to the DC/DC circuit 10, and the system cannot be powered on, so that the combiner cannot work.
Optionally, fig. 8 is a schematic structural diagram of a slow start circuit of a combiner according to an embodiment of the present invention. On the basis of the above embodiment, with reference to fig. 7 and 8, the slow start circuit 9 includes a fifth switch tube 91, a seventh resistor 92, an eighth resistor 93, and a ninth resistor 94; a first terminal 911 of the fifth switching tube 91 is electrically connected to the input terminal 95 of the slow start circuit 9, a second terminal 912 of the fifth switching tube 91 is electrically connected to the first terminal 911 of the fifth switching tube 91 through a seventh resistor 92, and the second terminal 912 of the fifth switching tube 91 is electrically connected to the output terminal 96 of the slow start circuit 9; the control terminal 913 of the fifth switch tube 91 is electrically connected to the first terminal 931 of the eighth resistor 93 and the first terminal 941 of the ninth resistor 94, the second terminal 932 of the eighth resistor 93 is electrically connected to the input terminal 95 of the slow start circuit 9, and the second terminal 942 of the ninth resistor 94 is grounded.
Specifically, the fifth switch tube 91 may be a field effect tube, and a seventh resistor 92 is connected in parallel between the source S and the drain D of the field effect tube, and is used for charging a large capacitor in the subsequent circuit through the seventh resistor 92 when the power supply is just connected.
Optionally, fig. 9 is a schematic structural diagram of another slow start circuit of a combiner according to an embodiment of the present invention. Based on the above embodiment, with reference to fig. 7 and fig. 9, the slow start circuit 9 may further include an RC delay circuit 97, the RC delay circuit 97 is disposed between the second terminal 912 of the fifth switch tube 91 and the control terminal 913 of the fifth switch tube 91, and the RC delay circuit 97 is used for power-on delay. Illustratively, when the power is switched on, the fifth switching tube 91 is turned on with a delay due to an RC delay circuit between the second terminal 912 of the fifth switching tube 91 and the control terminal 913 of the fifth switching tube 91, during this delay, the power enters the subsequent circuit from the seventh resistor 92 to charge the subsequent circuit large capacitor, and after the delay is over, the fifth switching tube 91 is turned on.
Optionally, fig. 10 is a schematic structural diagram of a first switch circuit of a combiner according to an embodiment of the present invention. On the basis of the above-described embodiment, in conjunction with fig. 7 and 10, the circuit configurations of the first switch circuit 6 and the second switch circuit 7 may be the same. Illustratively, the first switch circuit 6 includes a first switch tube 601, a second switch tube 602, a third switch tube 603, a fourth switch tube 64, a third resistor 65, a fourth resistor 66, a fifth resistor 67, and a sixth resistor 68, a first end 6011 of the first switch tube 601 is electrically connected to a first end 6021 of the second switch tube 602, and a second end 6012 of the first switch tube 601 is electrically connected to the first end 62 of the first switch circuit 6; a control end 6013 of the first switch tube 601 is electrically connected to a second end 6012 of the first switch tube 601 through a third resistor 65, and the control end 6013 of the first switch tube 601 is electrically connected to a first end 6031 of a third switch tube 603 through a fourth resistor 66; the second terminal 6032 of the third switching tube 603 is grounded, and the control terminal 6033 of the third switching tube 603 is electrically connected to the control terminal 643 of the fourth switching tube 64 and the control terminal 61 of the first switching circuit 6; the first terminal 641 of the fourth switching tube 64 is electrically connected to the control terminal 6023 of the second switching tube 602 through the sixth resistor 68, and the control terminal 6023 of the second switching tube 602 is electrically connected to the second terminal 6022 of the second switching tube 602 and the second terminal 63 of the first switching circuit 6 through the fifth resistor 67.
Specifically, the first switch tube 601 and the second switch tube 602 may be field effect transistors, and the first end 6011 of the first switch tube 601, i.e., the drain D, and the first end 6021 of the second switch tube 602, i.e., the drain D, are connected in series to form a bidirectional switch, so as to prevent the voltage from being reversely conducted along with the body diode of the field effect transistor when the switch is turned off. The third switch tube 603 and the fourth switch tube 64 may be triodes, the third switch tube 603 is connected between the control end 6013, i.e. the gate G, of the first switch tube 601 and the first end 6012, i.e. the source S, to control the turn-on voltage V of the first switch tube 601GS(th)The fourth switching transistor 64 is connected between the control terminal 6023, i.e. the gate G, and the first terminal 6022, i.e. the source S of the second switching transistor 602 to control the turn-on voltage V of the second switching transistor 602GS(th)Thereby achieving the purpose of controlling the on-off of the bidirectional switch.
Optionally, fig. 11 is a schematic structural diagram of another combiner provided in the embodiment of the present invention. On the basis of the foregoing embodiment, referring to fig. 11, the combiner further includes a first lightning protection circuit 11, a second lightning protection circuit 12, and a third lightning protection circuit 13, where the first lightning protection circuit 11 is connected between the first port 1 and the first filter 4, the first lightning protection circuit 11 is configured to protect lightning strike energy of the first port 1, the second lightning protection circuit 12 is connected between the second port 2 and the second filter 5, the second lightning protection circuit 12 is configured to protect lightning strike energy of the second port 2, the first filter 4 and the second filter 5 are electrically connected to the third port 3 through the third lightning protection circuit 13, and the third lightning protection circuit 13 is configured to protect lightning strike energy of the third port 3.
Specifically, the first lightning protection circuit 11, the second lightning protection circuit 12 and the third lightning protection circuit 13 may have the same structure, the first lightning protection circuit 11, the second lightning protection circuit 12 and the third lightning protection circuit 13 include three stages, the first stage is protected by the gas discharge tube against lightning stroke impact energy, can be conducted to the ground instantaneously to release lightning stroke energy, the second stage is suppressed by decoupling inductance against lightning stroke impact current, the third stage is suppressed by the transient state against diode against lightning stroke residual voltage, so that voltage is limited within a certain range. The circuit structures of the first lightning protection circuit, the second lightning protection circuit and the third lightning protection circuit may be the same, and fig. 12 is a schematic diagram of the first lightning protection circuit structure of the combiner according to the embodiment of the present invention. On the basis of the above embodiment, referring to fig. 12, the first lightning protection circuit 11 includes the gas discharge tube 111, the decoupling inductor 112 and the transient suppression diode 113, the first end 1111 of the gas discharge tube 111 is electrically connected to the first end 1121 of the decoupling inductor 112 and the signal input end 110 of the first lightning protection circuit 11, the second end 1122 of the decoupling inductor 112 is electrically connected to the cathode of the transient suppression diode 113 and the signal output end 1100 of the first lightning protection circuit 11, and the second end 1112 of the gas discharge tube 111 and the anode of the transient suppression diode 113 are grounded.
Optionally, the first lightning protection circuit 11 further includes a capacitor 114, a first end 1141 of the capacitor 114 is electrically connected to the first end 1121 of the decoupling inductor 112, and a second end 1142 of the capacitor 114 is grounded. The gas discharge tube 111 is used for protecting the impact energy of lightning stroke, can be conducted to the ground instantly to release the energy of lightning stroke, the decoupling inductor 112 is used for inhibiting the impact current of lightning stroke, and the transient suppression diode 113 is used for protecting the residual voltage of lightning stroke, so that the voltage is limited in a certain range.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A combiner, comprising: a first port, a second port, and a third port;
a first filter and a second filter, the first filter connected between the first port and the third port, the second filter connected between the second port and the third port;
a first switch circuit and a second switch circuit, the first switch circuit being connected between the first port and the third port, the first switch circuit being configured to turn on or off the connection between the first port and the third port according to a control signal; the second switch circuit is connected between the second port and the third port, and is configured to turn on or off the connection between the second port and the third port according to a control signal;
the logic interlocking control circuit is configured to collect the voltages of the first port and the second port, and output the control signal to control the first switch circuit or the second switch circuit to be conducted when the logic states of the voltage of the first port and the voltage of the second port are different.
2. The combiner of claim 1, wherein the logic interlock control circuit comprises: the logic interlock switch circuit, the first voltage sampling circuit and the second voltage sampling circuit;
the first voltage sampling circuit is connected between the first port and the first switch circuit, and is configured to collect a voltage signal input by the first port; the second voltage sampling circuit is connected between the second port and the second switch circuit, and is configured to collect a voltage signal input by the second port;
the logic interlock switch circuit is configured to collect the voltage of the first port through the first voltage sampling circuit and collect the voltage of the second port through the second voltage sampling circuit.
3. The combiner of claim 2,
the first voltage sampling circuit and the second voltage sampling circuit have the same circuit structure;
the first voltage sampling circuit comprises a first resistor and a second resistor;
the first end of the first resistor is electrically connected with the input end of the voltage sampling circuit and the second output end of the first voltage sampling circuit, the second end of the first resistor is electrically connected with the first end of the second resistor and the first output end of the first voltage sampling circuit, and the second end of the second resistor is grounded.
4. The combiner of claim 2, wherein a first input of the logic interlock switch circuit is electrically connected to a first output of the first voltage sampling circuit; the second input end of the logic interlocking switch circuit is electrically connected with the first output end of the second voltage sampling circuit; the third input end of the logic interlocking switch circuit is electrically connected with the input end of the first voltage sampling circuit and the input end of the second voltage sampling circuit;
the first output end of the logic interlocking switch circuit is electrically connected with the control end of the first switch circuit; and the second output end of the logic interlocking switch circuit is electrically connected with the control end of the second switch circuit.
5. The combiner of claim 4,
the logic interlock switch circuit is configured to:
when the voltage of the first port and the voltage of the second port are in different logic states and the logic state of the voltage of the first port is a high level, a first output end of the logic interlocking switch circuit outputs a control signal to control the first switch circuit to be switched on and control the second switch circuit to be kept in a switched-off state;
when the voltage of the first port and the voltage of the second port are in different logic states and the voltage of the second port is in a high level, the second output end of the logic interlocking switch circuit outputs a control signal to control the second switch circuit to be switched on and control the first switch circuit to keep a switched-off state.
6. The combiner of claim 4,
the logic interlocking switch circuit comprises a first comparison unit, a second comparison unit, a first NOT gate, a second NOT gate, a first AND gate and a second AND gate;
the first input end of the first comparison unit is electrically connected with the first input end of the logic interlocking switch circuit; the first input end of the second comparison unit is electrically connected with the second input end of the logic interlocking switch circuit; a second input end of the first comparing unit and a second input end of the second comparing unit are respectively and electrically connected with a third input end of the logic interlock switch circuit, and the second input end of the first comparing unit and the second input end of the second comparing unit are respectively used for inputting reference voltage;
the output end of the first comparison unit is electrically connected with the first input end of the second AND gate through the second NOT gate, and the second input end of the second AND gate is electrically connected with the output end of the second comparison unit;
the output end of the second comparison unit is electrically connected with the second input end of the first AND gate through the first NOT gate, and the first input end of the first AND gate is electrically connected with the output end of the first comparison unit;
the output end of the first AND gate is electrically connected with the first output end of the logic interlocking switch circuit; and the output end of the second AND gate is electrically connected with the second output end of the logic interlocking switch circuit.
7. The combiner of claim 4, further comprising: a slow start circuit and a DC/DC circuit;
the input end of the slow starting circuit is respectively and electrically connected with the first input end of the first voltage sampling circuit and the first input end of the second voltage sampling circuit; the output end of the slow starting circuit is electrically connected with the third input end of the logic interlocking switch circuit through the DC/DC circuit;
the DC/DC circuit is used for converting the received voltage signal output by the slow starting circuit into a low-voltage electric signal and providing reference voltage for the third input end of the logic interlocking switch circuit.
8. The combiner of claim 7,
the slow starting circuit comprises a fifth switching tube, a seventh resistor, an eighth resistor and a ninth resistor;
the first end of the fifth switching tube is electrically connected with the input end of the slow starting circuit, the second end of the fifth switching tube is electrically connected with the first end of the fifth switching tube through the seventh resistor, and the second end of the fifth switching tube is electrically connected with the output end of the slow starting circuit;
the control end of the fifth switching tube is electrically connected with the first end of the eighth resistor and the first end of the ninth resistor, the second end of the eighth resistor is electrically connected with the input end of the slow starting circuit, and the second end of the ninth resistor is grounded.
9. The combiner of claim 1,
the circuit structures of the first switch circuit and the second switch circuit are the same;
the first switching circuit comprises a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;
the first end of the first switch tube is electrically connected with the first end of the second switch tube, and the second end of the first switch tube is electrically connected with the first end of the first switch circuit;
the control end of the first switching tube is electrically connected with the second end of the first switching tube through the third resistor, and the control end of the first switching tube is electrically connected with the first end of the third switching tube through the fourth resistor; the second end of the third switching tube is grounded, and the control end of the third switching tube is electrically connected with the control end of the fourth switching tube and the control end of the first switching circuit;
the first end of the fourth switch tube is electrically connected with the control end of the second switch tube through the sixth resistor, and the control end of the second switch tube is electrically connected with the second end of the second switch tube and the second end of the first switch circuit through the fifth resistor.
10. The combiner of claim 1, further comprising: the lightning protection circuit comprises a first lightning protection circuit, a second lightning protection circuit and a third lightning protection circuit;
the first lightning protection circuit is connected between the first port and the first filter;
the second lightning protection circuit is connected between the second port and the second filter;
and the first filter and the second filter are electrically connected with the third port through the third lightning protection circuit.
CN202011025732.8A 2020-09-25 2020-09-25 Combiner Active CN112186317B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011025732.8A CN112186317B (en) 2020-09-25 2020-09-25 Combiner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011025732.8A CN112186317B (en) 2020-09-25 2020-09-25 Combiner

Publications (2)

Publication Number Publication Date
CN112186317A true CN112186317A (en) 2021-01-05
CN112186317B CN112186317B (en) 2022-03-18

Family

ID=73944028

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011025732.8A Active CN112186317B (en) 2020-09-25 2020-09-25 Combiner

Country Status (1)

Country Link
CN (1) CN112186317B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11154804A (en) * 1997-11-20 1999-06-08 Hitachi Ltd High frequency circuit device
JP2001274723A (en) * 2000-03-23 2001-10-05 Murata Mfg Co Ltd Mobile communication unit and high-frequency compound component used therefor
CN107359894A (en) * 2017-06-30 2017-11-17 广东欧珀移动通信有限公司 Radio circuit, antenna assembly and electronic equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11154804A (en) * 1997-11-20 1999-06-08 Hitachi Ltd High frequency circuit device
JP2001274723A (en) * 2000-03-23 2001-10-05 Murata Mfg Co Ltd Mobile communication unit and high-frequency compound component used therefor
CN107359894A (en) * 2017-06-30 2017-11-17 广东欧珀移动通信有限公司 Radio circuit, antenna assembly and electronic equipment

Also Published As

Publication number Publication date
CN112186317B (en) 2022-03-18

Similar Documents

Publication Publication Date Title
EP2768102A1 (en) Circuit interruption device
CN107534438A (en) DC solid circuit breaker and distribution system
CN110581541A (en) surge current suppression circuit with isolation control
CN1913353B (en) Dc solid-state relay
CN102222874B (en) Direct-current solid-state circuit breaker
CN112039028B (en) Remote control instruction and bus under-voltage protection circuit with strong anti-jamming capability
CN112186317B (en) Combiner
US10498135B2 (en) Switch protection device
CN109347466B (en) Switching circuit and electronic equipment
CN219145262U (en) Bidirectional power supply
CN113852051B (en) Direct-current solid-state circuit breaker with bidirectional switching-on and switching-off and soft starting functions and control method
CN212751784U (en) Electronic system
CN109449880A (en) A kind of high-power aerospace modular power source input undervoltage protection circuit
CN214380048U (en) Surge protection circuit and battery power supply circuit
KR101734215B1 (en) Bidirectional non-isolation dc-dc converter with improved in stability
CN112054485A (en) Electronic system
CN209217707U (en) The surge suppressor of function is kept with power down
CN108429244B (en) Electronic switch and hybrid high-voltage direct-current circuit breaker
CN112803526A (en) Charging control circuit of robot
CN101854115B (en) Time retention circuit for preventing current from back pumping and power inverter
CN205453284U (en) Take voltage clamp controller of seamless handover function
CN109921648A (en) A kind of GaN high current self-powered bidirectional, dc solid circuit breaker and DC power system
US11539326B2 (en) Photovoltaic direct-current breaking apparatus
CN107579547B (en) Aircraft power distribution system based on integrated solid state relay module
CN219304474U (en) Input anti-reflection device and DC-DC three-level circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20220106

Address after: 239000 No. 8, Yong Yang Road, national economic and Technological Development Zone, Chuzhou, Anhui

Applicant after: LUXSHARE PRECISION INDUSTRY (CHUZHOU) Co.,Ltd.

Address before: No. 158, Jinchang Road, Jinxi Town, Kunshan City, Suzhou City, Jiangsu Province

Applicant before: KUNSHAN LIXUN RF TECHNOLOGY CO.,LTD.

GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20240324

Address after: Building 3, 5, and auxiliary buildings of the second phase standard factory building, No. 99 Xubang Road, Wuzhong Economic Development Zone, Suzhou City, Jiangsu Province, 215124

Patentee after: Suzhou Lixun Technology Co.,Ltd.

Country or region after: China

Address before: 239000 No. 8, Yong Yang Road, national economic and Technological Development Zone, Chuzhou, Anhui

Patentee before: LUXSHARE PRECISION INDUSTRY (CHUZHOU) Co.,Ltd.

Country or region before: China