CN112185662B - Eight-path fully-symmetrical distributed on-chip transformer - Google Patents

Eight-path fully-symmetrical distributed on-chip transformer Download PDF

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CN112185662B
CN112185662B CN202011057011.5A CN202011057011A CN112185662B CN 112185662 B CN112185662 B CN 112185662B CN 202011057011 A CN202011057011 A CN 202011057011A CN 112185662 B CN112185662 B CN 112185662B
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voltage output
output port
current
mutual inductor
coil
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CN112185662A (en
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兰俊
王希云
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Shenyang Shenxi Transformer Manufacture Co ltd
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Taojiang Fengguan Motor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F29/00—Variable transformers or inductances not covered by group H01F21/00
    • H01F29/02—Variable transformers or inductances not covered by group H01F21/00 with tappings on coil or winding; with provision for rearrangement or interconnection of windings

Abstract

The invention relates to an eight-path completely symmetrical distributed on-chip transformer, which comprises a primary coil which is symmetrical along an x axis and a y axis and is provided with eight signal ports and a secondary coil which is formed by coils which are symmetrical along the x axis and the y axis and is provided with two signal ports, wherein two signal ports connected with the primary coil are connected with inductors with equal size, a pair of suspended metal strips are arranged at the positions which are symmetrical with the centers of the two signal ports on the secondary coil, the primary coil and the secondary coil of the transformer are both arranged into symmetrical structures, and the balance of each port of the transformer is effectively improved through the arrangement of the completely symmetrical structures, so that the transformer can effectively prevent the overvoltage damage of the transformer caused by overlarge current, and according to the selection method provided by the embodiment of the invention, the voltage output selected at any time is relatively safe and meets the output requirement, and is relatively safe, and the service life of the transformer is prolonged.

Description

Eight-path fully-symmetrical distributed on-chip transformer
Technical Field
The invention relates to the field of transformers, in particular to an eight-path fully-symmetrical distributed on-chip transformer.
Background
As is well known, the on-chip transformer can realize impedance transformation, power synthesis and power distribution, has the advantages of small insertion loss, small area, capability of realizing multi-path power synthesis and distribution, and the like, and plays an important role in the fields of radio frequency, microwave and millimeter wave integrated circuits, and the like.
The secondary coil in the existing on-chip transformer has a shape identical to that of the primary coil. Although the on-chip transformer with the conventional structure can realize impedance conversion, power synthesis and power distribution, the imbalance of each port of the transformer is very serious due to the asymmetry of the structure of the on-chip transformer, which is mainly characterized in that the impedance difference of each port is large when the on-chip transformer is used for impedance conversion, and the power loss is large when the on-chip transformer is used for power synthesis and power distribution.
Disclosure of Invention
Therefore, the invention provides the eight-path fully-symmetrical distributed on-chip transformer, which can effectively reduce the power loss of the transformer.
In order to achieve the above object, the present invention provides an eight-path fully symmetric distributed on-chip transformer, comprising: the coil comprises a primary coil which is symmetrical along an x axis and a y axis and is provided with eight signal ports and a secondary coil which is formed by coils which are symmetrical along the x axis and the y axis and is provided with two signal ports, wherein inductors with the same size are connected between every two connected signal ports on the primary coil, and a pair of suspended metal strips are arranged at positions which are symmetrical with the centers of the two signal ports on the secondary coil; the suspended metal strip and the metal strip of the signal port form an electric structure which is symmetrical along the x axis and the y axis; the transformer comprises a primary coil, a secondary coil and a transformer coil, and is characterized by further comprising a main control circuit, wherein a current control unit is arranged in the main control circuit and used for adjusting current in each mutual induction coil, the primary coil is used for outputting, and the corresponding secondary coil is used for inputting; a first voltage output port U1, a second voltage output port U2, a third voltage output port U3 and a fourth voltage output port U4 are arranged on the primary coil, a first mutual inductor is arranged between the first voltage output port U1 and the second voltage output port U2, the current of the first mutual inductor is phi 1, a second mutual inductor is arranged between the second voltage output port U2 and the third voltage output port U3, the current of the second mutual inductor is phi 2, a third mutual inductor is arranged between the third voltage output port U3 and the fourth voltage output port U4, the current of the third mutual inductor is phi 3, and a fourth mutual inductor is arranged between the fourth voltage output port U3 and the first voltage output port, and the current of the fourth mutual inductor is phi 4; at any moment, a port voltage difference matrix (U120, U230, U340, U410) is preset in the main control circuit, wherein U120 represents a standard deviation value of the first voltage output port and the second voltage output port, U230 represents a standard deviation value of the second voltage output port and the third voltage output port, U340 represents a standard deviation value of the third voltage output port and the fourth voltage output port, and U410 represents the fourth voltage output port, an absolute value U12 of a difference value between the first voltage output port U1 and the second voltage output port U2, an absolute value U23 of a difference value between the second voltage output port U2 and the third voltage output port U3, an absolute value U34 of a difference value between the third voltage output port U3 and the fourth voltage output port U4, an absolute value U41 of a difference value between the fourth voltage output port U4 and the first voltage output port U1 are compared, and if | U1-U2 is smaller than U120, selecting a first voltage output port as output, linearly increasing the corresponding current phi 1 of the first mutual inductor, selecting a second voltage output port as output if | U1-U2| is equal to U120, sinusoidally changing the corresponding current phi 2 of the second mutual inductor, determining whether | U2-U3| is less than or equal to U230 if | U1-U2| is greater than U120, selecting a second voltage output port as output if | U2-U3| is less than or equal to U230, and sinusoidally changing the corresponding current phi 2 of the second mutual inductor; if the | U2-U3| is larger than U230, determining whether the | U3-U4| is smaller than or equal to U340, if so, selecting a third voltage output port as output, and enabling the current phi 3 of the corresponding third mutual inductor to adopt exponential change; if the | U3-U4| is larger than U340, determining whether the | U4-U1| is smaller than or equal to U410, if so, adopting a fourth voltage output port as output, and adopting cosine change for the corresponding current Φ 4 of the fourth mutual inductor, otherwise, adopting a first voltage output port as output, and adopting linear change for the corresponding current Φ 1 of the first mutual inductor.
Further, the current Φ 1 of the first mutual inductor is k × t, where t represents the operating time of the first mutual inductor, and k is a constant coefficient; the current Φ 2 of the second mutual inductor is Im2 × sin (ω t + ji0), where Im2 represents the maximum current of the second mutual inductor, ω represents the frequency of the current, ji0 represents the initial phase of the current, both fixed values;
current Φ 3 of the third mutual inductor is a × ejθWherein a is a constant coefficient, and theta represents a current phase; the current Φ 4 of the fourth mutual inductor is Im4 × cos (ω t + ji0), where Im4 represents the maximum current of the fourth mutual inductor, ω represents the frequency of the current, ji0 represents the initial phase of the current, both of which are fixed values; the primary coils comprise a first group of primary coils, a second group of primary coils, a third group of primary coils and a fourth group of primary coils which are sequentially arranged and respectively provided with a signal port at two ends.
Further, the main control circuit is provided with four preset time periods T (T1, T2, T3, T4), wherein T1 represents a first time length in the preset period, T2 represents a second time length in the preset period, T3 represents a third time length in the preset period, T4 represents a fourth time length in the preset period, and the first time length T1> the second time length T2> the third time length T3> the fourth time length T4, when in use, the second voltage output port is started to work after the working time of the first voltage output port is longer than or equal to a first time period T1, after the second voltage output port works for a second time period T2, the third voltage output port is started to work, and when the third voltage output port works for a third time period T3, starting the fourth voltage output port to work, and when the fourth voltage output port works for a complete cycle.
Furthermore, a first path coil of the secondary coil enters the center of the primary coil from the first path signal port, crosses with the terminal connecting line at the center of the primary coil, extends outwards to the middle of the first group of primary coils, extends to one end of the first group of primary coils, then reaches one end of the second group of primary coils, crosses with the second path coil, extends to the other end of the second group of primary coils, then reaches one end of the third group of primary coils, extends to the other end of the third group of primary coils, then reaches one end of the fourth group of primary coils, crosses with the second path coil, extends to the other end of the fourth group of primary coils, then reaches the other end of the first group of primary coils, extends to the middle of the first group of primary coils, then returns to the center of the primary coils, and is the terminal of the first path coil, and the first path coil continuously extends from the terminal point to a position symmetrical to the first path signal port by the Y axis to form a second path signal port, the terminal connecting line is a line connecting the terminal of the first path of coil and the terminal of the second path of coil.
Furthermore, the secondary coil is a symmetrical structure with two parallel-connected crossed circles, a center tap is respectively arranged at a virtual point of each path of signal on the primary coil, and a feeding point for direct current feeding is arranged at a virtual point on the primary coil.
Further, within the first time period T1, the first voltage output port is preferentially used, and after the operating time period of the first voltage output port is met, the next output is selected; in a second time period T2, the second voltage output port is preferentially used, and after the working time period of the second voltage output port is met, the next output is selected; in a third time period T3, the third voltage output port is preferentially used, and after the working time period of the third voltage output port is met, the next output is selected; during the fourth time period T4, the fourth voltage output port is preferentially used, and the next output is selected after the operating time period of the third voltage output port is satisfied.
Further, a standard sloshing current matrix I (I10, I20, I30, I40) is further arranged in the main control circuit, wherein I10 represents a standard sloshing current of a first mutual inductor, I20 represents a standard sloshing current of a second mutual inductor, I30 represents a standard sloshing current of a third mutual inductor, I40 represents a standard sloshing current of a fourth mutual inductor, if the current Φ 1 of the first mutual inductor is compared with the standard sloshing current of the first mutual inductor, and if an error range is not within a preset range, the current Φ 2 of the second mutual inductor and the standard sloshing current of the second mutual inductor are detected, if the error after comparison is within the preset range, a second voltage output port is adopted for outputting, otherwise, the current Φ 3 of the third mutual inductor and the standard sloshing current of the third mutual inductor are continuously detected, and if the error is not within the error range, selecting the voltage output port where the coil with the minimum error is located as the voltage output port.
Further, the primary coil and the secondary coil are arranged in a circular shape.
Further, the primary coil and the secondary coil are arranged in a square or regular polygon shape.
Further, the primary coil and the secondary coil are concentrically arranged.
Compared with the prior art, the eight-path fully-symmetrical distributed on-chip transformer provided by the embodiment of the invention has the beneficial effects that the eight-path fully-symmetrical distributed on-chip transformer has multiple paths of voltage outputs, which path needs to be taken as an output, and different voltage outputs are selected at different moments, so that the efficient utilization of the transformer is realized.
Further, different voltage output ports are selected to be output at any time, the currents of the corresponding mutual inductors are different, when the first voltage output port is selected to be output, the corresponding current phi 1 of the first mutual inductor is linearly increased, so that the voltage of the first voltage output port is slowly changed, overvoltage damage caused by overlarge current is prevented, when the second voltage output port is selected to be output, the corresponding current phi 2 of the second mutual inductor is sinusoidally changed, so that the voltage of the second voltage output port is slowly changed, overvoltage damage caused by overlarge current is prevented, the corresponding current phi 3 of the third mutual inductor is exponentially changed, the voltage of the third voltage output port is slowly changed, and overvoltage damage caused by overlarge current is prevented, when the fourth voltage output port is selected to be output, the corresponding current phi 4 of the fourth mutual inductor adopts cosine change, so that the voltage of the fourth voltage output port also changes slowly, and the transformer is prevented from being damaged by overvoltage caused by overlarge current.
The eight-path fully-symmetrical distributed on-chip transformer provided by the embodiment of the invention realizes the change of the voltages of the first voltage output port, the second voltage output port, the third voltage output port and the fourth voltage output port by utilizing the current on the first mutual inductor, the current on the second mutual inductor, the current on the third mutual inductor and the current on the fourth mutual inductor to carry out the agitation, and four currents of linear change, sine change, exponential change and cosine change are adopted to carry out the agitation, so that the change of the output voltage is slowly increased or reduced, the stability of the output voltage is improved, and the safety and the stability of the transformer are met.
In the embodiment of the invention, a standard sloshing current matrix I (I10, I20, I30 and I40) is arranged in a main control circuit, after the current phi 1 of a first mutual inductor is compared with the standard sloshing current of the first mutual inductor, if the error range is not in the preset range, the current phi 2 of a second mutual inductor and the standard sloshing current of the second mutual inductor are detected, if the error after comparison is in the preset range, a second voltage output port is adopted for outputting, otherwise, the current phi 3 of a third mutual inductor and the standard sloshing current of the current of a third mutual inductor are continuously detected, if the error range is not in the preset range, the current phi 4 of a fourth mutual inductor and the standard sloshing current of the current of a fourth mutual inductor are continuously detected, and if the error range is not in the preset range, the voltage output port at which the coil with the smallest error is located is selected, the output of each voltage output port is selected according to the standard of the surge current, so that the selection of the voltage output ports is more intelligent and accords with the actual condition of the transformer, the output voltages of the first voltage output port, the second output voltage port, the third output voltage port and the fourth output voltage port are all safe, and the safety and the stability of the transformer in the use process are ensured.
Furthermore, the primary coil and the secondary coil of the transformer are both arranged to be symmetrical structures, and a pair of suspended metal strips which are symmetrical to the electric structure of the primary coil and the secondary coil are arranged on the symmetrical surfaces of the two signal ports of the secondary coil, so that the balance of each port of the transformer is effectively improved through the arrangement of the completely symmetrical structure, the transformer provided by the invention has smaller loss when used for power synthesis, power distribution, impedance conversion and other operations, and has a better effect in practical application.
Drawings
Fig. 1 is a schematic structural diagram of an eight-path fully-symmetric distributed on-chip transformer according to an embodiment of the present invention.
Detailed Description
In order that the objects and advantages of the invention will be more clearly understood, the invention is further described below with reference to examples; it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only for explaining the technical principle of the present invention, and do not limit the scope of the present invention.
It should be noted that in the description of the present invention, the terms of direction or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, which are only for convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Furthermore, it should be noted that, in the description of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, the present invention provides an eight-path fully symmetric distributed on-chip transformer, which includes: the coil comprises a primary coil (shown by square frame lines in figure 1) which is symmetrical along an x axis and a y axis and is provided with eight signal ports and a secondary coil (shown by chain lines in figure 1) which is composed of coils with symmetrical structures along the x axis and the y axis and is provided with two signal ports, wherein inductors with the same size are connected between every two signal ports connected to the primary coil, and a pair of suspended metal strips are arranged at positions on the secondary coil which are symmetrical with the centers of the two signal ports; the suspended metal strip and the metal strip of the signal port form an electric structure which is symmetrical along the x axis and the y axis; the transformer comprises a primary coil, a secondary coil and a transformer coil, and is characterized by further comprising a main control circuit, wherein a current control unit is arranged in the main control circuit and used for adjusting current in each mutual induction coil, the primary coil is used for outputting, and the corresponding secondary coil is used for inputting; a first voltage output port U1, a second voltage output port U2, a third voltage output port U3 and a fourth voltage output port U4 are arranged on the primary coil, a first mutual inductor is arranged between the first voltage output port U1 and the second voltage output port U2, the current of the first mutual inductor is phi 1, a second mutual inductor is arranged between the second voltage output port U2 and the third voltage output port U3, the current of the second mutual inductor is phi 2, a third mutual inductor is arranged between the third voltage output port U3 and the fourth voltage output port U4, the current of the third mutual inductor is phi 3, and a fourth mutual inductor is arranged between the fourth voltage output port U3 and the first voltage output port, and the current of the fourth mutual inductor is phi 4; at any moment, a port voltage difference matrix (U120, U230, U340, U410) is preset in the main control circuit, wherein U120 represents a standard deviation value of the first voltage output port and the second voltage output port, U230 represents a standard deviation value of the second voltage output port and the third voltage output port, U340 represents a standard deviation value of the third voltage output port and the fourth voltage output port, and U410 represents the fourth voltage output port, an absolute value U12 of a difference value between the first voltage output port U1 and the second voltage output port U2, an absolute value U23 of a difference value between the second voltage output port U2 and the third voltage output port U3, an absolute value U34 of a difference value between the third voltage output port U3 and the fourth voltage output port U4, an absolute value U41 of a difference value between the fourth voltage output port U4 and the first voltage output port U1 are compared, and if | U1-U2 is smaller than U120, selecting a first voltage output port as output, linearly increasing the corresponding current phi 1 of the first mutual inductor, selecting a second voltage output port as output if | U1-U2| is equal to U120, sinusoidally changing the corresponding current phi 2 of the second mutual inductor, determining whether | U2-U3| is less than or equal to U230 if | U1-U2| is greater than U120, selecting a second voltage output port as output if | U2-U3| is less than or equal to U230, and sinusoidally changing the corresponding current phi 2 of the second mutual inductor; if the | U2-U3| is larger than U230, determining whether the | U3-U4| is smaller than or equal to U340, if so, selecting a third voltage output port as output, and enabling the current phi 3 of the corresponding third mutual inductor to adopt exponential change; if the | U3-U4| is larger than U340, determining whether the | U4-U1| is smaller than or equal to U410, if so, adopting a fourth voltage output port as output, and adopting cosine change for the corresponding current Φ 4 of the fourth mutual inductor, otherwise, adopting a first voltage output port as output, and adopting linear change for the corresponding current Φ 1 of the first mutual inductor.
The eight-path fully-symmetrical distributed on-chip transformer provided by the embodiment of the invention has multiple paths of voltage outputs, and in the actual use process, which path needs to be used as an output, and different voltage outputs are selected at different moments to realize the efficient utilization of the transformer, and as can be understood by those skilled in the art, by comparing the voltages of the paths, one path of the multiple paths of voltage outputs is selected to be used with the highest priority, the selection of the path of voltage output is considered according to the safety and energy saving performance of the whole circuit, a port voltage difference matrix (U120, U230, U340 and U410) is preset in the main control circuit, wherein U120 represents the standard difference value between a first voltage output port and a second voltage output port, U230 represents the standard difference value between the second voltage output port and a third voltage output port, and U340 represents the standard difference value between the third voltage output port and a fourth voltage output port, u410 denotes a fourth voltage output port, and compares an absolute value U12 of a difference value between the first voltage output port U1 and the second voltage output port U2, an absolute value U23 of a difference value between the second voltage output port U2 and the third voltage output port U3, an absolute value U34 of a difference value between the third voltage output port U3 and the fourth voltage output port U4, and an absolute value U41 of a difference value between the fourth voltage output port U4 and the first voltage output port U1, respectively, if | U1-U2| is smaller than U120, the first voltage output port is selected as an output, a current Φ 1 of the corresponding first mutual inductor is linearly increased, if | U1-U2| is equal to U120, the second voltage output port is selected as an output, a current Φ 2 of the corresponding second mutual inductor is sinusoidally varied, if | U1-U2| is larger than U230, it is determined whether U | 2-U3| is smaller than U230, if the current phi 2 of the second mutual inductor is smaller than the preset value, selecting a second voltage output port as output, wherein the current phi 2 of the corresponding second mutual inductor adopts sinusoidal change; if the | U2-U3| is larger than U230, determining whether the | U3-U4| is smaller than or equal to U340, if so, selecting a third voltage output port as output, and enabling the current phi 3 of the corresponding third mutual inductor to adopt exponential change; if the | U3-U4| is larger than U340, determining whether | U4-U1| is smaller than or equal to U410, if so, adopting a fourth voltage output port as output, adopting cosine change for the current Φ 4 of the corresponding fourth mutual inductor, otherwise, adopting a first voltage output port as output, adopting linear change for the current Φ 1 of the corresponding first mutual inductor, selecting different voltage output ports as output at any time, adopting different currents of the corresponding mutual inductors, adopting linear increase for the current Φ 1 of the corresponding first mutual inductor when selecting the first voltage output port as output, so that the voltage of the first voltage output port also changes slowly, preventing overvoltage damage to the transformer caused by overlarge current, adopting sine change for the current Φ 2 of the corresponding second mutual inductor when selecting the second voltage output port as output, when the third voltage output port is selected as output, the corresponding current phi 3 of the third mutual inductor changes in an exponential mode, the voltage of the third voltage output port also changes in a slow mode, the transformer is prevented from being damaged by overvoltage caused by overlarge current, and when the fourth voltage output port is selected as output, the corresponding current phi 4 of the fourth mutual inductor changes in a cosine mode, the voltage of the fourth voltage output port also changes in a slow mode, and the transformer is prevented from being damaged by overvoltage caused by overlarge current.
Specifically, the current Φ 1 of the first mutual inductor is k × t, where t represents the operating time of the first mutual inductor, and k is a constant coefficient; the current Φ 2 of the second mutual inductor is Im2 × sin (ω t + ji0), where Im2 represents the maximum current of the second mutual inductor, ω represents the frequency of the current, ji0 represents the initial phase of the current, both fixed values; current Φ 3 of the third mutual inductor is a × ejθWherein a is a constant coefficient, and theta represents a current phase; the current Φ 4 of the fourth mutual inductor is Im4 × cos (ω t + ji0), where Im4 represents the maximum current of the fourth mutual inductor, ω represents the frequency of the current, ji0 represents the initial phase of the current, both of which are fixed values; the primary coils comprise a first group of primary coils, a second group of primary coils, a third group of primary coils and a fourth group of primary coils which are sequentially arranged and respectively provided with a signal port at two ends.
The eight-path fully-symmetrical distributed on-chip transformer provided by the embodiment of the invention realizes the change of the voltages of the first voltage output port, the second voltage output port, the third voltage output port and the fourth voltage output port by utilizing the current on the first mutual inductor, the current on the second mutual inductor, the current on the third mutual inductor and the current on the fourth mutual inductor to carry out the agitation, and four currents of linear change, sine change, exponential change and cosine change are adopted to carry out the agitation, so that the change of the output voltage is slowly increased or reduced, the stability of the output voltage is improved, and the safety and the stability of the transformer are met.
Specifically, the master control circuit is provided with a preset time period matrix T (T1, T2, T3, T4), wherein T1 represents a first time length in a preset period, T2 represents a second time length in the preset period, T3 represents a third time length in the preset period, T4 represents a fourth time length in the preset period, and the first time length T1> the second time length T2> the third time length T3> the fourth time length T4, when in use, the second voltage output port is started to work after the working time of the first voltage output port is longer than or equal to a first time period T1, after the second voltage output port works for a second time period T2, the third voltage output port is started to work, and when the third voltage output port works for a third time period T3, starting the fourth voltage output port to work, and when the fourth voltage output port works for a complete cycle.
In the embodiment of the invention, the working time of each voltage output port is limited to a certain extent by controlling the working time of each voltage output port, if the working time limit is reached, other voltage output ports need to be replaced, so that heat accumulation caused by overlong use time is prevented, the voltage output efficiency is prevented from being influenced, and the purpose that the voltage output ports cannot be fully utilized is also prevented from being too short, a preset time period matrix T (T1, T2, T3 and T4) is arranged on a main control circuit, when the working time of a first voltage output port is greater than or equal to a first time period T1, a second voltage output port is started to work, when the second voltage output port works for a second time period T2, a third voltage output port is started to work, and when the third voltage output port works for a third time period T3, and starting the fourth voltage output port to work, and when the fourth voltage output port works in a complete cycle, ensuring the utilization rate of each voltage output port, preventing the voltage output ports from being wasted due to long-time non-use and performing voltage output within a preset time length, and ensuring the safety of the circuit.
Specifically, within the first time period T1, the first voltage output port is preferentially used, and after the operating time period of the first voltage output port is satisfied, the next output is selected; in a second time period T2, the second voltage output port is preferentially used, and after the working time period of the second voltage output port is met, the next output is selected; in a third time period T3, the third voltage output port is preferentially used, and after the working time period of the third voltage output port is met, the next output is selected; during the fourth time period T4, the fourth voltage output port is preferentially used, and the next output is selected after the operating time period of the third voltage output port is satisfied.
According to the eight-path fully-symmetrical distributed on-chip transformer provided by the embodiment of the invention, the corresponding working time length is set for each voltage output port, the corresponding voltage output port is preferentially used in the corresponding working time length range, specifically, if the required working time length is within T1, the first voltage output port is preferentially used, and the first voltage output port is replaced after the working time length of the first voltage output port is met, so that the scheduling of each voltage output port has certain regularity, and the setting of the working time length of each voltage output port is comprehensively considered according to the actual factors of voltage, current, coils and the like, so that the voltage output of each voltage output port of the transformer has certain intelligence and accords with the actual capacity of the transformer.
Specifically, a standard sloshing current matrix I (I10, I20, I30, I40) is further provided in the main control circuit, wherein I10 represents a standard sloshing current of a first mutual inductor, I20 represents a standard sloshing current of a second mutual inductor, I30 represents a standard sloshing current of a third mutual inductor, I40 represents a standard sloshing current of a fourth mutual inductor, if an error range of the current Φ 1 of the first mutual inductor is compared with the standard sloshing current of the first mutual inductor, the current Φ 2 of the second mutual inductor and the standard sloshing current of the second mutual inductor are detected within a preset range, if the error after comparison is within the preset range, a second voltage output port is used for outputting, otherwise, the current 3 of the third mutual inductor and the standard sloshing current of the third mutual inductor are continuously detected, and if the error range is not within the preset range, continuously detecting the current phi 4 of the fourth mutual inductor and the standard surge current of the fourth mutual inductor, and if the error range is not within the preset range, selecting the voltage output port where the coil with the smallest error is located as the voltage output port.
In the embodiment of the invention, a standard sloshing current matrix I (I10, I20, I30 and I40) is arranged in a main control circuit, after the current phi 1 of a first mutual inductor is compared with the standard sloshing current of the first mutual inductor, if the error range is not in the preset range, the current phi 2 of a second mutual inductor and the standard sloshing current of the second mutual inductor are detected, if the error after comparison is in the preset range, a second voltage output port is adopted for outputting, otherwise, the current phi 3 of a third mutual inductor and the standard sloshing current of the current of a third mutual inductor are continuously detected, if the error range is not in the preset range, the current phi 4 of a fourth mutual inductor and the standard sloshing current of the current of a fourth mutual inductor are continuously detected, and if the error range is not in the preset range, the voltage output port at which the coil with the smallest error is located is selected, the output of each voltage output port is selected according to the standard of the surge current, so that the selection of the voltage output ports is more intelligent and accords with the actual condition of the transformer, the output voltages of the first voltage output port, the second output voltage port, the third output voltage port and the fourth output voltage port are all safe, and the safety and the stability of the transformer in the use process are ensured.
The primary coil and the secondary coil of the transformer are both arranged to be symmetrical structures, and the symmetrical surfaces of the two signal ports of the secondary coil are provided with a pair of suspended metal strips which are symmetrical to the electric structure of the primary coil and the secondary coil, so that the balance of each port of the transformer is effectively improved through the arrangement of the completely symmetrical structure, the transformer provided by the invention has smaller loss when used for operations such as power synthesis, power distribution, impedance transformation and the like, and has a better effect in practical application.
Specifically, the primary coils include a first group of primary coils 100, a second group of primary coils 200, a third group of primary coils 300, and a fourth group of primary coils 400, which are sequentially arranged and each of which has one signal port at each of both ends.
The eight-path completely-symmetrical distributed on-chip transformer adopts an up-and-down coupling structure, the primary coil is of one circle and has eight signal ports, the secondary coil is of two circles which are connected in parallel and crossed in a surrounding mode and is provided with two signal ports, a pair of suspended metal strips are arranged on the symmetrical surface of the two signal ports of the secondary coil, and the suspended metal strips and the metal strips of the signal ports are of a centrosymmetric electric structure. The technical performance parameters of the dry-type transformer can be ensured, the reliability is improved, the cost is saved, the service life is long, and the noise can be reduced.
Specifically, a first coil of the secondary coil enters the center of the primary coil from a first signal port 500, crosses with an end point connecting line at the center of the primary coil, extends outwards to the middle of a first group of primary coils 100, extends to one end of the first group of primary coils 100, then reaches one end of a second group of primary coils 200, crosses with a second coil, extends to the other end of a second group of primary coils, then reaches one end of a third group of primary coils, extends to the other end of a third group of primary coils 300, then reaches one end of a fourth group of primary coils 400, crosses with a second coil, extends to the other end of the fourth group of primary coils, then reaches the other end of the first group of primary coils, extends to the middle of the first group of primary coils, then returns to the center of the primary coils, and is the end point of the first coil, the first coil continuously extends from the end point to a position symmetrical to the first signal port by a Y axis, and is provided with a second signal port 600, the terminal connecting line is a line connecting the terminal of the first path of coil and the terminal of the second path of coil.
Specifically, the secondary coil is a symmetrical structure formed by two circles of coils which are connected in parallel and crossed in a surrounding mode.
The secondary coil is converted into a symmetrical structure with two parallel coils, which are crossed and surrounded, so that the proportion of converting differential mode signals into common mode signals in work is effectively reduced, the balance of each port of the transformer is greatly improved, and each port has better impedance consistency when used for impedance conversion, has higher efficiency when used for power synthesis and power distribution, and is suitable for large-scale popularization and application.
Specifically, a center tap is provided at each virtual point of each signal on the original coil.
In order to improve the convenience of direct current feed, inductors with the same size are connected between two signal ports connected to the primary coil, and the inductors at the positions corresponding to the primary coil on the secondary coils which are connected in parallel and surrounded in a crossed mode and the primary coil are in an up-and-down coupling mode, so that the direct current feed has a higher coupling coefficient.
Specifically, a feeding point for dc power feeding is provided at a virtual point on the primary coil. In order to further improve the overall performance, a feeding point of direct current feeding is arranged, the invention can realize high-efficiency power synthesis in a millimeter wave frequency band, has better balance, is suitable for power synthesis, power distribution, impedance conversion and the like, and has higher synthesis efficiency.
Specifically, the primary coil and the secondary coil are provided in a square shape. The coil has the advantages of simple structure, convenience in realizing symmetrical design, convenience in design of the used coil, and convenience and practicability.
Specifically, the primary coil and the secondary coil are provided in a circular shape. By adopting the circular coil design, the specific application scenes are different, the application scenes and the application range of the transformer are increased, more personalized requirements are met, the market is convenient to open, and more market shares are occupied.
Specifically, the primary coil and the secondary coil are provided with a regular polygon. The regular polygonal coil design is adopted, the length of the coil is increased, the circuit design is more complex, the personalized requirements of users are met, the application scene is enlarged, and the product diversity is enriched.
Specifically, the primary coil and the secondary coil are concentrically arranged. The concentric facility enables power matching, loss matching, resistance matching and the like to be more balanced, and the service performance of the transformer is provided.
So far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention; various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. An eight-way fully symmetric distributed on-chip transformer, comprising: the coil comprises a primary coil which is symmetrical along an x axis and a y axis and is provided with eight signal ports, and a secondary coil which is formed by coils which are symmetrical along the x axis and the y axis and is provided with two signal ports, wherein inductance coils with the same size are connected between every two connected signal ports on the primary coil, and a pair of suspended metal strips are arranged at the positions which are symmetrical with the centers of the two signal ports on the secondary coil; the suspended metal strip and the metal strip of the signal port form an electric structure which is symmetrical along the x axis and the y axis;
the first path of coil of the secondary coil enters the center of the primary coil from the first path of signal port, crosses with the terminal connecting wire at the center of the primary coil, extends outwards to the middle of the first group of primary coils, extends to one end of the first group of primary coils, then reaches one end of the second group of primary coils, crosses with the second path of coil, extends to the other end of the second group of primary coils, then reaches one end of the third group of primary coils, extends to the other end of the third group of primary coils, then reaches one end of the fourth group of primary coils, crosses with the second path of coil, extends to the other end of the fourth group of primary coils, then reaches the other end of the first group of primary coils, extends to the middle of the first group of primary coils, then returns to the center of the primary coils, and is the terminal of the first path of coil, the first path of coil extends from the terminal to a position symmetrical to the first path of signal port by the Y axis to be provided with the second path of signal port, the end point connecting line is a line connecting the end point of the first path of coil and the end point of the second path of coil, and the auxiliary coil is of a symmetrical structure formed by two coils which are connected in parallel and crossed in a surrounding mode;
the primary coil and the secondary coil are arranged to be square or regular polygon, and the primary coil and the secondary coil are arranged concentrically;
the transformer is characterized by further comprising a main control circuit, wherein a current control unit is arranged in the main control circuit and used for adjusting currents in the first mutual inductor, the second mutual inductor, the third mutual inductor and the fourth mutual inductor, the primary coil is used for outputting, and the corresponding secondary coil is used for inputting; a first voltage output port U1, a second voltage output port U2, a third voltage output port U3 and a fourth voltage output port U4 are arranged on the primary coil, a first mutual inductor is arranged between the first voltage output port U1 and the second voltage output port U2, the current of the first mutual inductor is phi 1, a second mutual inductor is arranged between the second voltage output port U2 and the third voltage output port U3, the current of the second mutual inductor is phi 2, a third mutual inductor is arranged between the third voltage output port U3 and the fourth voltage output port U4, the current of the third mutual inductor is phi 3, and a fourth mutual inductor is arranged between the fourth voltage output port U3 and the first voltage output port, and the current of the fourth mutual inductor is phi 4;
at any moment, a port voltage difference matrix (U120, U230, U340, U410) is preset in the main control circuit, wherein U120 represents a standard deviation value of the first voltage output port and the second voltage output port, U230 represents a standard deviation value of the second voltage output port and the third voltage output port, U340 represents a standard deviation value of the third voltage output port and the fourth voltage output port, and U410 represents the fourth voltage output port, an absolute value U12 of a difference value between the first voltage output port U1 and the second voltage output port U2, an absolute value U23 of a difference value between the second voltage output port U2 and the third voltage output port U3, an absolute value U34 of a difference value between the third voltage output port U3 and the fourth voltage output port U4, an absolute value U41 of a difference value between the fourth voltage output port U4 and the first voltage output port U1 are compared, and if | U1-U2 is smaller than U120, selecting a first voltage output port as output, linearly increasing the corresponding current phi 1 of the first mutual inductor, selecting a second voltage output port as output if | U1-U2| is equal to U120, sinusoidally changing the corresponding current phi 2 of the second mutual inductor, determining whether | U2-U3| is less than or equal to U230 if | U1-U2| is greater than U120, selecting a second voltage output port as output if | U2-U3| is less than or equal to U230, and sinusoidally changing the corresponding current phi 2 of the second mutual inductor; if the | U2-U3| is larger than U230, determining whether the | U3-U4| is smaller than or equal to U340, if so, selecting a third voltage output port as output, and enabling the current phi 3 of the corresponding third mutual inductor to adopt exponential change; if the | U3-U4| is larger than U340, determining whether the | U4-U1| is smaller than or equal to U410, if so, adopting a fourth voltage output port as output, and adopting cosine change for the corresponding current Φ 4 of the fourth mutual inductor, otherwise, adopting a first voltage output port as output, and adopting linear change for the corresponding current Φ 1 of the first mutual inductor.
2. The eight-way fully symmetric distributed on-chip transformer according to claim 1,
the current phi 1 of the first mutual inductor is k multiplied by t, wherein t represents the working time of the first mutual inductor, and k is a constant coefficient;
the current Φ 2 of the second mutual inductor is Im2 × sin (ω t + ji0), where Im2 represents the maximum current of the second mutual inductor, ω represents the frequency of the current, ji0 represents the initial phase of the current, both fixed values;
current Φ 3 of the third mutual inductor is a × ejθWherein a is a constant coefficient, and theta represents a current phase;
the current Φ 4 of the fourth mutual inductor is Im4 × cos (ω t + ji0), where Im4 represents the maximum current of the fourth mutual inductor, ω represents the frequency of the current, ji0 represents the initial phase of the current, both of which are fixed values;
the primary coils comprise a first group of primary coils, a second group of primary coils, a third group of primary coils and a fourth group of primary coils which are sequentially arranged and respectively provided with a signal port at two ends.
3. The eight-path fully symmetric distributed on-chip transformer according to claim 2, wherein the master control circuit is provided with four preset time periods T (T1, T2, T3, T4), wherein T1 represents a first time duration within the preset period, T2 represents a second time duration within the preset period, T3 represents a third time duration within the preset period, T4 represents a fourth time duration within the preset period, and the first time duration T1> the second time duration T2> the third time duration T3> the fourth time duration T4, when in use, the second voltage output port is enabled to operate after the first time duration T1 is greater than or equal to the first time duration T1, the third voltage output port is enabled to operate after the second time duration T2 is operated, and the fourth voltage output port is enabled to operate after the third voltage output port operates the third time duration T3, a complete cycle of operation when the fourth voltage output port is operational.
4. The eight-way fully symmetric distributed on-chip transformer according to claim 3,
in the first time length T1, the first voltage output port is preferentially used, and after the working time length of the first voltage output port is met, the next output is selected;
in a second time period T2, the second voltage output port is preferentially used, and after the working time period of the second voltage output port is met, the next output is selected;
in a third time period T3, the third voltage output port is preferentially used, and after the working time period of the third voltage output port is met, the next output is selected;
during the fourth time period T4, the fourth voltage output port is preferentially used, and the next output is selected after the operating time period of the third voltage output port is satisfied.
5. The eight-way fully symmetric distributed on-chip transformer according to claim 4,
the main control circuit is also internally provided with a standard sloshing current matrix I (I10, I20, I30 and I40), wherein I10 represents the standard sloshing current of the first mutual inductor, I20 represents the standard sloshing current of the second mutual inductor, I30 represents the standard sloshing current of the third mutual inductor, I40 represents the standard sloshing current of the fourth mutual inductor, if the current phi 1 of the first mutual inductor is compared with the standard sloshing current of the first mutual inductor, and the error range is not within a preset range, the current phi 2 of the second mutual inductor and the standard sloshing current of the second mutual inductor are detected, if the error after comparison is within the preset range, a second voltage output port is adopted for outputting, otherwise, the current phi 3 of the third mutual inductor and the standard sloshing current of the third mutual inductor are continuously detected, and if the error is not within the error range, selecting the voltage output port where the coil with the minimum error is located as the voltage output port.
6. The eight-path fully symmetric distributed on-chip transformer according to claim 1, wherein a center tap is respectively disposed at a virtual location of each signal on the primary coil, and a feeding point for dc feeding is disposed at a virtual location on the primary coil.
CN202011057011.5A 2020-09-29 2020-09-29 Eight-path fully-symmetrical distributed on-chip transformer Active CN112185662B (en)

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CN103247426A (en) * 2013-06-06 2013-08-14 电子科技大学 Fully symmetrical eight-port distributed on-chip transformer
CN103281040A (en) * 2013-06-06 2013-09-04 电子科技大学 On-chip power amplifier synthesized based on power of eight branches of fully symmetrical transformers
CN108269677A (en) * 2017-12-29 2018-07-10 苏州威发半导体有限公司 On-chip transformer

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CN103247426A (en) * 2013-06-06 2013-08-14 电子科技大学 Fully symmetrical eight-port distributed on-chip transformer
CN103281040A (en) * 2013-06-06 2013-09-04 电子科技大学 On-chip power amplifier synthesized based on power of eight branches of fully symmetrical transformers
CN108269677A (en) * 2017-12-29 2018-07-10 苏州威发半导体有限公司 On-chip transformer

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