CN112181893B - Communication method and system between multi-core processor cores in vehicle controller - Google Patents
Communication method and system between multi-core processor cores in vehicle controller Download PDFInfo
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Abstract
The invention discloses a method and a system for communication among multi-core processor cores in a vehicle controller, which relate to the field of development of a vehicle controller, and the method comprises the steps of dividing an internal shared memory of a processor into a plurality of data subunits, wherein each data subunit comprises a recording segment for recording single inter-core communication state information and a data segment for reading and writing data; labeling the divided data subunits, sequencing the data subunits according to a preset sequencing rule, and configuring a preset reading rule for the reading operation of the processor core; based on the sequencing of the data subunits, the kernel with write operation in the processor writes data into the data segments of the data subunits in sequence; based on the sequencing of the data subunits, the kernel with the read operation in the processor sequentially reads the data of the data segments of the data subunits according to a preset read rule. The invention can effectively ensure the self scheduling period of the software without additional delay waiting.
Description
Technical Field
The invention relates to the field of development of automobile controllers, in particular to a method and a system for communication among multi-core processor cores in an automobile controller.
Background
In the field of automobile controller development, along with the increasing complexity of application functions, the requirements on the computing capability and the real-time performance of a processor are higher and higher. The multi-core processor is widely introduced, which aims to solve the defects of a single-core processor in the aspects of main frequency, computing capability and the like in the current technical level and realize higher processing performance in a parallel mode. In the application of the multi-core processor, because different cores operate independently, an additional inter-core communication mechanism is needed to ensure the consistency of data or the synchronism of control flow among different cores, and further ensure that the logic of system software is executed according to the designed target.
The inter-core communication has two schemes, one is that the shared access of a plurality of cores to the same chip memory area is realized through the interlocking mechanism of software or hardware, and most of the cases are matched with a hardware spin lock to ensure the data consistency; the other is based on software interruption among different cores, and is matched with a direct storage access implementation mode, for example, after one core completes write operation of a memory region through direct storage access, one software interruption is triggered to inform other cores, the other cores firstly copy data in the memory into a private memory region of the other cores, and the software interruption also informs that the shared memory region is used completely.
For inter-core communication in a simple shared memory manner, a scenario that many cores wait exists, and the influence on the real-time performance of software operation and the parallelism of a system is large, that is, when one core performs write operation on a shared memory area, if another core needs to perform read operation on the memory area, polling is required to wait until the write operation of other cores is completed. For the scheme of introducing the interrupt, the waiting time of storage access in the former scheme can only be eliminated, and the non-synchronization of reading and writing between different cores still causes that the software of one core needs to delay waiting or introduces an additional processing mechanism to ensure the consistency of data processing during the operation, and the real-time performance of software operation and the parallelism of a system are still influenced.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a method and a system for communication among multi-core processor cores in a vehicle controller, which can effectively ensure the scheduling period of software and do not need extra delay waiting.
In order to achieve the above object, the present invention provides a method for communication between multi-core processor cores in a vehicle controller, comprising the steps of:
dividing an internal shared memory of a processor into a plurality of data subunits, wherein each data subunit comprises a recording segment for recording communication state information among cores at a time and a data segment for reading and writing data;
labeling the divided data subunits, sequencing the data subunits according to a preset sequencing rule, and configuring a preset reading rule for the reading operation of the processor core;
based on the sequencing of the data subunits, the kernel with write operation in the processor writes data into the data segments of the data subunits in sequence;
based on the sequencing of the data subunits, the kernel with the read operation in the processor sequentially reads the data of the data segments of the data subunits according to a preset read rule.
On the basis of the technical proposal, the device comprises a shell,
the preset ordering rule is a cyclic ordering rule which is arranged from small to large according to the label sequence and is connected end to end.
On the basis of the technical proposal, the device comprises a shell,
the recording segments comprise a writing state recording segment and a plurality of groups of reading state recording segments;
the writing state recording segment comprises a writing operation kernel identifier, a writing operation data sequence number and a writing operation writing state;
the read state record segment comprises a read operation kernel identifier, a read operation data sequence number and a read operation read state.
On the basis of the technical proposal, the device comprises a shell,
the writing operation kernel identification is the number of the kernel which performs writing operation on the data subunit;
the serial number of the write operation data is consistent with the label of the data subunit in which the current write operation write state is located;
the write operation write status comprises unwritten, writing in and write complete;
the read operation kernel identifier is the number of a kernel which reads the data subunit;
the serial number of the reading operation data is consistent with the label of the data subunit where the serial number of the reading operation data is located;
the read operation read states include unread, reading, and read complete.
On the basis of the technical proposal, the device comprises a shell,
when data is not written in the data segment of the data subunit, the writing operation writing state of the data subunit is not written;
when the kernel writes data into the data segment of the data subunit, the write operation write state of the data subunit is write-in;
when the kernel finishes writing data into the data segment of the data subunit, the writing operation writing state of the data subunit is writing completion;
when the data in the data segment of the data subunit is not read by the kernel, the reading operation reading state of the data subunit is not read;
when the data in the data segment of the data subunit is being read by the kernel, the reading operation reading state of the data subunit is reading;
after the data in the data segment of the data subunit is read by the kernel, the read operation of the data subunit is read in a read completion state.
On the basis of the technical scheme, based on the sorting of the data subunits, the kernel with write operation in the processor sequentially writes data into the data segments of the data subunits, specifically:
acquiring a write operation data serial number of a data subunit which carries out write operation last time;
based on the obtained write operation data serial number, obtaining the next data subunit adjacent to the data subunit corresponding to the operation data serial number according to the sequence of the data subunits;
and writing data in the acquired data segment of the data subunit, recording a write operation data sequence number of the data subunit after the write operation is finished, setting the write operation write state of the data subunit as write completion, and setting the read operation read state as unread.
On the basis of the technical scheme, before data writing is carried out in the data segment of the acquired data subunit:
when the read operation and read state of the obtained data subunit is read, writing data into the data segment of the data subunit and covering the original data in the data segment;
and when the read operation read state of the acquired data subunit is unread, performing the record operation of the write operation data serial number only on the data subunit, and when the record times of the write operation data serial number of the data subunit reach preset times, and the read operation read state of each time is unread in the preset times, performing error report on the data subunit.
On the basis of the technical proposal, the device comprises a shell,
the preset reading rule comprises a first preset reading rule and a second preset reading rule;
the first preset reading rule is that when a plurality of data subunits with reading states set as unread reading operations are found, the data subunits with data written in the data segments after the last reading operation are selected, and the data of the data subunits are read;
and the second preset reading rule is that when a plurality of reading operation reading states are found and set as unread, the reading operation reading state is continuously found to be the data subunit with finished reading, and the data of the data segment of the data subunit is read.
On the basis of the above technical solution, the data reading of the data segments of the data subunits is sequentially performed by the kernel having a read operation in the processor according to a preset read rule based on the sorting of the data subunits, specifically:
acquiring a write operation data serial number and a read operation data serial number of a data subunit which is subjected to read operation last time;
based on the obtained read operation data serial number, according to the sorting of the data subunits, obtaining the next data subunit adjacent to the data subunit corresponding to the read operation data serial number:
when the reading state of the obtained reading operation of the next data subunit is the reading completion, reading the data of the data segment of the data subunit which is subjected to the reading operation last time again, and recording the serial number of the data of the reading operation of the data subunit;
when the read state of the obtained read operation of the next data subunit is not read and the preset read rule configured by the kernel currently performing the read operation is a first preset read rule, reading the data of the data segment of the data subunit and recording the serial number of the read operation data of the data subunit;
and when the read state of the obtained next data subunit is not read and the preset read rule configured by the kernel currently performing the read operation is a second preset read rule, continuing to obtain the data subunits backwards according to the sequence of the data subunits until the read state of the obtained data subunit is read, reading the data of the data segment of the data subunit, and recording the serial number of the read operation data of the data subunit.
The invention provides a multi-core processor inter-core communication system in a vehicle controller, which comprises:
the data sub-units comprise a recording segment and a data segment, the recording segment comprises a writing state recording segment and a plurality of groups of reading state recording segments, the writing state recording segment comprises a writing operation kernel identifier, a writing operation data sequence number and a writing operation writing state, and the reading state recording segment comprises a reading operation kernel identifier, a reading operation data sequence number and a reading operation reading state;
and the cores are used for carrying out data writing and data reading on the data segments in the data subunits.
Compared with the prior art, the invention has the advantages that: on the basis of adopting the inter-core communication mode of the shared memory, the rules of memory access and the data structure of the shared memory are redefined, so that when a single core accesses the shared memory area, the scheduling period of the software is effectively ensured, extra delay waiting is not needed, and the real-time performance of software operation is further improved.
Drawings
FIG. 1 is a flowchart illustrating a method for communication among multi-core processor cores in a vehicle controller according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an internal structure of a processor according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an internal shared memory structure according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a multi-core processor inter-core communication method in a vehicle controller, which enables a single core to effectively ensure the scheduling period of software when accessing a shared memory area without extra delay waiting through an optimized memory access rule and a shared memory data structure on the basis of adopting a shared memory inter-core communication mode. The embodiment of the invention correspondingly provides a multi-core processor inter-core communication system in the vehicle controller.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, the communication between the multicore processors in the vehicle controller according to the embodiment of the present invention includes the following steps:
s1: the method comprises the steps of dividing an internal shared memory of a processor into a plurality of data subunits, wherein the data subunits comprise a recording segment for recording communication state information among cores at a time and a data segment for reading and writing data. Referring to fig. 2, an internal structure of a processor is shown, in which an internal shared memory is a random storage resource inside the processor, which can be accessed by each core in the processor.
Referring to fig. 3, for the internal shared memory structure after repartitioning, the internal shared memory is partitioned into a plurality of data subunits, each data subunit includes a recording segment and a data segment, and further includes a data verification segment, where the data verification segment is non-essential content and is only used in a usage scenario with special requirements on data security. The content of the data segment is self-defined by application software, and the embodiment of the invention does not limit the specific data structure and meaning thereof.
The recording segment comprises a writing state recording segment and a plurality of groups of reading state recording segments; the writing state recording segment comprises a writing operation kernel identifier, a writing operation data sequence number and a writing operation writing state; the read state record segment comprises a read operation kernel identifier, a read operation data sequence number and a read operation read state.
The writing operation kernel mark is the number of the kernel which carries out writing operation on the data subunit and is used for indicating a specific kernel in the processor; the serial number of the write operation data is consistent with the label of the data subunit in which the current write operation write state is located; the write operation write status comprises unwritten, writing in and writing completed; the read operation kernel identifier is the number of the kernel which performs read operation on the data subunit; the reading operation data sequence number is consistent with the label of the data subunit where the reading operation data sequence number is located. The write operation kernel identifier and the read operation kernel identifier correspond to the number of the kernel performing the write operation or the read operation, for example, the kernel 1 performs the write operation on the current data subunit, and the write operation kernel identifier of the current data subunit is 1. According to the number of the data sub-units, for example, the label of the current data sub-unit is 2, the write operation data serial number and the read operation data serial number of the current data sub-unit are both 2.
In the embodiment of the invention, when data is not written in the data segment of the data subunit, the writing operation writing state of the data subunit is not written; when the kernel writes data into the data segment of the data subunit, the write operation write state of the data subunit is write-in; when the kernel finishes writing data into the data segment of the data subunit, the writing operation writing state of the data subunit is writing completion; when the data in the data segment of the data subunit is not read by the kernel, the reading operation reading state of the data subunit is not read; when the data in the data segment of the data subunit is being read by the kernel, the reading operation reading state of the data subunit is reading; after the data in the data segment of the data subunit is read by the kernel, the read operation of the data subunit is read in a read completion state.
S2: labeling the divided data subunits, sequencing the data subunits according to a preset sequencing rule, and configuring a preset reading rule for the reading operation of the processor core; in the embodiment of the present invention, the preset ordering rule is a circular ordering rule with labels sequentially decreasing from small to large and connected end to end, for example, the number of the data subunits is 3, and the labels are 1, 2, 3, 1, 2, 3 … …, and the circular ordering is performed in a closed circular manner, where the tail number 3 is connected to the head number 1 in the circular ordering, so as to form a circular data cache structure.
In the embodiment of the invention, the space size of the annular data cache formed by annular sequencing is used, the number of the data subunits is configured offline according to a specific inter-core communication application scene, for example, a configurable interface can be provided in an inter-core communication initialization stage, the specific configuration parameters need to consider the application scenes such as the operation performance and specific communication content of different cores so as to ensure the space size of the annular data cache, the number of the data subunits can cover the maximum asynchronous degree of different processor cores, and online change is not supported in a software operation stage.
S3: based on the sequencing of the data subunits, the kernel with write operation in the processor writes data into the data segments of the data subunits in sequence;
s4: based on the sequencing of the data subunits, the kernel with the read operation in the processor sequentially reads the data of the data segments of the data subunits according to a preset read rule.
In the embodiment of the invention, in the process of one inter-core communication, the inter-core communication method physically isolates the read-write operation, namely in the annular data cache, the inner core performing the write operation firstly searches the whole cache region to find the data subunit which is not used recently or has been subjected to the write operation earliest and is not accessed by other inner cores, and the single write operation only performs data update on one data subunit; when other cores need to perform read operation, the whole annular data cache region is searched first, and the data subunits which are updated after the last read or are updated newly and are not read and are written by the designated core are read. By adopting the mode, the atomicity of the write operation can be ensured under the condition that a hardware spin lock is not used, the condition that the same data unit is simultaneously accessed by a plurality of kernels can not be caused, the data consistency is effectively ensured, the asynchronization of the read operation and the write operation among the kernels caused by the asynchronization of the running of the kernels is eliminated, the waiting condition that a certain kernel needs to wait for the completion of the read-write operation of other kernels occurs, and the real-time performance of the system is improved.
The circular data cache search mechanism is implemented based on the write operation data sequence number or the read operation data sequence number in the status information stored in the write operation or the read operation in the data subunit. For example, the total number of the data subunits is N, after the inter-core communication is initialized, all the write operation data sequence numbers or the read operation data sequence numbers are sequentially set to 1-N, and the specific sequence number corresponds to the offset address of the data subunit in the data cache region, so that any one data subunit can be quickly accessed through the head address and the offset address (the sequence number of the write or read data) of the data cache.
When a certain kernel completes the write operation on the first data subunit for the first time, the data subunit with the write operation data sequence number of 1 is operated, the write operation write state in the state information of the write data after the write operation is completed is set to be write-completed, and then the write operation is performed again, the write operation data sequence number is the data subunit corresponding to the write operation data sequence number of the last write plus 1, the write operation write state after the write operation is completed is set to be write-completed, and the read operation read state is unread. And after the serial number of the write operation data of the next write operation reaches N, resetting the serial number of the new write operation data to be 1, and realizing the rolling storage of the write data in the annular data cache corresponding to the data subunit corresponding to the first write operation.
When a certain kernel reads the ring cache data for the first time, the searching is started from the first data subunit, when the write-in state of the write-in operation of the data subunit is 'write-in completed', the data segment in the corresponding data subunit is read, and the read-out state of the read-out operation is set to 'read-out completed', otherwise, the state information which is not established by the inter-kernel communication is returned. And then, when the reading operation is triggered again, searching the next unread data unit or the latest data subunit according to the initialization configuration of the inter-core communication, and setting the reading state of the reading operation as the reading completion state after the reading is completed. And after the serial number of the next reading operation data reaches N, resetting the serial number of the reading operation data to be 1, and realizing the rolling circulation of the reading data in the annular data cache corresponding to the data subunit corresponding to the first writing and reading operation.
In the embodiment of the present invention, based on the sorting of the data subunits, the kernel having a write operation in the processor sequentially writes data into the data segments of the data subunits, specifically:
s301: acquiring a write operation data serial number of a data subunit which carries out write operation last time;
s302: based on the obtained write operation data serial number, obtaining the next data subunit adjacent to the data subunit corresponding to the operation data serial number according to the sequencing of the data subunits;
s303: and writing data in the acquired data segment of the data subunit, recording a write operation data sequence number of the data subunit after the write operation is finished, setting the write operation write state of the data subunit as write completion, and setting the read operation read state as unread.
Before data writing in the data segment of the acquired data subunit:
when the read operation and read state of the obtained data subunit is read, writing data into the data segment of the data subunit and covering the original data in the data segment;
and when the read operation read state of the acquired data subunit is unread, performing the record operation of the write operation data serial number only on the data subunit, and when the record times of the write operation data serial number of the data subunit reach preset times, and the read operation read state of each time is unread in the preset times, performing error report on the data subunit. That is, if the read state of a certain data subunit is unread and is recorded, and when the data subunit is written again, if the read state of the data subunit is still unread, it indicates that the data subunit is not read by other cores for a long time, and at this time, the writing of data into the data subunit is stopped, and an error message is reported.
In the embodiment of the present invention, when a specific write process is performed on a data subunit, a process of data write is indicated by a write state, before the write is started, the write state of the write operation is set to "being written", after a data segment and a data parity segment are updated, the write state of the write operation is set to "being written", and finally, the read state of the read operation is set to "not being read", which is used for indicating to a kernel performing the read operation that data in the data subunit is newly updated.
In the embodiment of the invention, the preset reading rules comprise a first preset reading rule and a second preset reading rule; the first preset reading rule is that when a plurality of data subunits with reading states set as unread reading operations are found, the data subunits with data written in the data segment after the last reading operation are selected, and the data of the data subunits are read; the second preset reading rule is that when the reading states of the plurality of reading operations are found and set as unread, the reading states of the reading operations are continuously found to be the data subunits which are read completely, and the data of the data segments of the data subunits are read.
Based on the sequencing of the data subunits, the kernel with the read operation in the processor sequentially reads the data of the data segments of the data subunits according to a preset read rule, and the method specifically comprises the following steps:
s401: acquiring a write operation data serial number and a read operation data serial number of a data subunit which is subjected to read operation last time;
s402: based on the obtained read operation data sequence number, obtaining the next data subunit adjacent to the data subunit corresponding to the read operation data sequence number according to the sorting of the data subunits:
when the reading state of the obtained reading operation of the next data subunit is the reading completion, reading the data of the data segment of the data subunit which is subjected to the reading operation last time again, and recording the serial number of the data of the reading operation of the data subunit;
when the read state of the obtained read operation of the next data subunit is not read and the preset read rule configured by the kernel currently performing the read operation is a first preset read rule, reading the data of the data segment of the data subunit and recording the serial number of the read operation data of the data subunit;
and when the read state of the obtained next data subunit is not read and the preset read rule configured by the kernel currently performing read operation is a second preset read rule, continuing to obtain the data subunits in the future according to the sequence of the data subunits until the read state of the obtained data subunit is read, reading the data of the data segment of the data subunit, and recording the serial number of the read operation data of the data subunit.
To realize rolling reading, when the data sequence number of the reading operation in the data subunit read last time is N, the operation is started from the data subunit with the data sequence number of the reading operation being 0 next time. In the specific reading process, the reading state of the reading operation is indicated to the data reading process, before reading is started, the reading state of the reading operation is set to be 'reading in progress', and after the reading of the data segment and the data verification segment is finished, the reading state of the reading operation is set to be 'reading finished'.
Before inter-core communication is used, basic configuration parameters are determined according to an actual application scene, and initialization setting is performed. The basic configuration parameters to be determined include a write operation kernel identifier of a write operation, a read operation kernel identifier of a read operation, a single data subunit data size, and a data subunit number (N) in the ring data cache. Through pre-configuration, the size of a shared memory space required by inter-core communication is uniquely determined, and the initial address of the annular data cache is determined through compiling and linking. For the read operation, a preset read rule needs to be configured separately, that is, when a plurality of unread data subunits are found, updated or latest updated data after the last read is selected, and the configuration will determine different software processes in the subsequent inter-core communication read operation.
In the initialization process, the configuration information defined as a constant type is read first, and the annular data cache is initialized according to the read information. The initialization work includes: traversing all the data subunits in the cache, respectively initializing the write-in operation kernel identification and the read-out operation kernel identification in each data subunit to corresponding values according to the configuration information, simultaneously sequentially initializing the read-out operation data serial number and the write-in operation data serial number to 1-N, specifically initializing the read-out operation read state and the write-in operation write state to be 'unread' or 'unwritten' according to the offset of the data subunit relative to the first address of the annular data cache, and finally respectively setting the first data subunit as the initial operation unit of the write operation and the read operation.
According to the communication method between the multi-core processor cores in the vehicle controller, disclosed by the embodiment of the invention, on the basis of adopting the inter-core communication mode of the shared memory, the memory access rule and the data structure of the shared memory are redefined, so that when a single core accesses the shared memory area, the scheduling period of software is effectively ensured, extra delay waiting is not needed, and the real-time performance of software operation is further improved.
The communication system between the multi-core processor cores in the vehicle controller provided by the embodiment of the invention comprises a plurality of data subunits and a plurality of cores. The data subunit comprises a recording segment and a data segment, wherein the recording segment comprises a writing state recording segment and a plurality of groups of reading state recording segments, the writing state recording segment comprises a writing operation kernel identifier, a writing operation data serial number and a writing operation writing state, and the reading state recording segment comprises a reading operation kernel identifier, a reading operation data serial number and a reading operation reading state; the kernel is used for carrying out data writing and data reading on the data segments in the data subunits.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A communication method among multi-core processor cores in a vehicle controller is characterized by comprising the following steps:
dividing an internal shared memory of a processor into a plurality of data subunits, wherein each data subunit comprises a recording segment for recording communication state information among cores at a time and a data segment for reading and writing data;
labeling the divided data subunits, sequencing the data subunits according to a preset sequencing rule, and configuring a preset reading rule for the reading operation of the processor core;
based on the sequencing of the data subunits, the kernel with write operation in the processor writes data into the data segments of the data subunits in sequence;
based on the sequencing of the data subunits, sequentially reading the data segments of the data subunits by an inner core with read operation in the processor according to a preset read rule;
wherein the recording segments include a write status recording segment and a plurality of groups of read status recording segments;
the writing state recording segment comprises a writing operation kernel identifier, a writing operation data sequence number and a writing operation writing state;
the reading state recording segment comprises a reading operation kernel identifier, a reading operation data serial number and a reading operation reading state;
based on the sorting of the data subunits, the kernel with write operation in the processor writes data into the data segments of the data subunits in sequence, specifically:
acquiring a write operation data sequence number of a data subunit which is subjected to the write operation last time;
based on the obtained write operation data serial number, obtaining the next data subunit adjacent to the data subunit corresponding to the operation data serial number according to the sequence of the data subunits;
and writing data in the acquired data segment of the data subunit, recording a write operation data sequence number of the data subunit after the write operation is finished, setting the write operation write state of the data subunit as write completion, and setting the read operation read state as unread.
2. The method for communication among the multiple cores in the vehicle controller according to claim 1, wherein:
the preset ordering rule is a cyclic ordering rule which is arranged from small to large according to the label sequence and is connected end to end.
3. The method for communication among the multiple cores in the vehicle controller according to claim 1, wherein:
the writing operation kernel identification is the number of the kernel which performs writing operation on the data subunit;
the serial number of the write operation data is consistent with the label of the data subunit in which the current write operation write state is located;
the write operation write status comprises unwritten, writing in and write complete;
the read operation kernel identifier is the number of the kernel which performs read operation on the data subunit;
the reading operation data serial number is consistent with the label of the data subunit in which the reading operation data serial number is positioned;
the read operation read states include unread, reading, and read complete.
4. The method for communication among the multiple core processors in the vehicle controller according to claim 3, wherein:
when data is not written in the data segment of the data subunit, the writing operation writing state of the data subunit is not written;
when the kernel writes data into the data segment of the data subunit, the write operation write state of the data subunit is write-in;
when the kernel finishes writing data into the data segment of the data subunit, the writing operation writing state of the data subunit is writing completion;
when the data in the data segment of the data subunit is not read by the kernel, the reading operation reading state of the data subunit is not read;
when the data in the data segment of the data subunit is being read by the kernel, the reading operation reading state of the data subunit is reading;
after the data in the data segment of the data subunit is read by the kernel, the read operation of the data subunit is read in a read completion state.
5. The inter-core communication method in the vehicle controller according to claim 4, wherein before data writing is performed in the data segment of the acquired data subunit:
when the read operation and read state of the obtained data subunit is read, writing data into the data segment of the data subunit and covering the original data in the data segment;
and when the read operation read state of the acquired data subunit is unread, performing the record operation of the write operation data serial number only on the data subunit, and when the record times of the write operation data serial number of the data subunit reach preset times, and the read operation read state of each time is unread in the preset times, performing error report on the data subunit.
6. The method for communication among the multiple core processors in the vehicle controller according to claim 4, wherein:
the preset reading rule comprises a first preset reading rule and a second preset reading rule;
the first preset reading rule is that when a plurality of data subunits with reading states set as unread reading operations are found, the data subunits with data written in the data segments after the last reading operation are selected, and the data of the data subunits are read;
and the second preset reading rule is that when a plurality of reading operation reading states are found and set as unread, the reading operation reading state is continuously found to be the data subunit with finished reading, and the data of the data segment of the data subunit is read.
7. The inter-core processor core communication method in the vehicle controller according to claim 6, wherein based on the sorting of the data subunits, a core having a read operation in the processor sequentially reads data segments of the data subunits according to a preset read rule, specifically:
acquiring a write operation data serial number and a read operation data serial number of a data subunit which is subjected to read operation last time;
based on the obtained read operation data serial number, according to the sorting of the data subunits, obtaining the next data subunit adjacent to the data subunit corresponding to the read operation data serial number:
when the reading state of the obtained reading operation of the next data subunit is the reading completion, reading the data of the data segment of the data subunit which is subjected to the reading operation last time again, and recording the serial number of the data of the reading operation of the data subunit;
when the read state of the obtained next data subunit is not read and the preset read rule configured by the kernel performing read operation currently is a first preset read rule, reading the data of the data segment of the data subunit and recording the serial number of the read operation data of the data subunit;
and when the read state of the obtained next data subunit is not read and the preset read rule configured by the kernel currently performing the read operation is a second preset read rule, continuing to obtain the data subunits backwards according to the sequence of the data subunits until the read state of the obtained data subunit is read, reading the data of the data segment of the data subunit, and recording the serial number of the read operation data of the data subunit.
8. A multi-core processor inter-core communication system in a vehicle controller, for implementing the multi-core processor inter-core communication method in the vehicle controller according to claim 1, comprising:
the data sub-units comprise a recording segment and a data segment, the recording segment comprises a writing state recording segment and a plurality of groups of reading state recording segments, the writing state recording segment comprises a writing operation kernel identifier, a writing operation data sequence number and a writing operation writing state, and the reading state recording segment comprises a reading operation kernel identifier, a reading operation data sequence number and a reading operation reading state;
and the cores are used for carrying out data writing and data reading on the data segments in the data subunits.
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| CN103942178A (en) * | 2014-03-03 | 2014-07-23 | 浙江大学 | Communication method between real-time operating system and non-real-time operating system on multi-core processor |
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