CN112165434B - Method and system for transparent transmission of CBR signal in packet switching system - Google Patents
Method and system for transparent transmission of CBR signal in packet switching system Download PDFInfo
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Abstract
The application provides a method and a system for transmitting CBR signals in a packet switching system, and the method for transmitting CBR signals in the packet switching system comprises the following steps: a source end of the packet signal receives a CBR signal sent by first equipment, converts the CBR signal into a packet signal with a fixed length, counts data volume N corresponding to the CBR signal within a preset time length T, and then sends the packet signal with the fixed length, T and N into a packet switching system; the packet switching system receives the packet signals with fixed length, T and N, and forwards the packet signals with fixed length, T and N to the destination of the packet signals after switching processing; and the sink end of the packet signal receives the packet signal with fixed length, T and N sent by the packet switching system, recovers the data of the CBR signal from the packet signal with fixed length, recovers the rate of the CBR signal according to the T and N, and sends the obtained CBR signal to the second equipment.
Description
Technical Field
The present invention relates to communication technology, and for example, to a method and system for transparent transmission of CBR signals in a packet switching system.
Background
A Constant Bit Rate (CBR) signal refers to a fixed Rate signal, and signals that can be directly transmitted on a physical medium in a communication system are all fixed Rate signals, such as an ethernet physical layer signal, a Synchronous Digital Hierarchy (SDH) signal, an Optical Transport Network (OTN) signal, and the like.
In a communication device, it is often necessary to load a signal a into the payload of a signal B, and to transmit and manage the signal a by transmitting the signal B. Where signal a and signal B are both fixed rate signals, generally signal a is called a client signal, signal B is called a service signal, client signal a and service signal B are different in rate and different in signal format. The client signal a is encapsulated in the service signal B at the source end and starts to be transmitted in some physical medium, and the client signal a is recovered from the service signal B at the sink end, and finally the rate of the client signal a must be guaranteed not to change, i.e. the client signal a must guarantee rate pass-through during transmission through the service signal B.
In order to implement large-scale cross scheduling of many CBR signals of the same type, the CBR signals need to be converted into packet signals at a source end, then the packet signals are introduced into a packet switching system located at an intermediate point, packet switching is performed through the packet switching system, then the packet signals generated at the intermediate point are sent to a sink end, and the packet signals are restored into the CBR signals at the sink end. If the CBR signal implements cross-dispatching through the packet switching system, where the CBR signal corresponds to the client signal a and the packet signal corresponds to the service signal B, the transmission delay of the service signal B is fixed in the first scenario, but the transmission delay of the service signal B is not fixed in the packet switching system. How to implement rate transparent transmission in the packet switching system is an urgent problem to be solved.
Disclosure of Invention
The application provides a method and a system for transmitting CBR signals in a packet switching system, which realize the speed transmission of the CBR signals in the packet switching system.
In a first aspect, an embodiment of the present application provides a method for transparently transmitting a CBR signal in a packet switching system, including:
a source end of the packet signal receives a CBR signal sent by first equipment, converts the CBR signal into a packet signal with a fixed length, counts data volume N corresponding to the CBR signal within a preset time length T, and then sends the packet signal with the fixed length, T and N into a packet switching system;
the packet switching system receives the packet signals with fixed length, T and N, and forwards the packet signals with fixed length, T and N to the destination of the packet signals after switching processing;
and the sink end of the packet signal receives the packet signal with fixed length, T and N sent by the packet switching system, recovers the data of the CBR signal from the packet signal with fixed length, recovers the rate of the CBR signal according to the T and N, and sends the obtained CBR signal to the second equipment.
In a second aspect, an embodiment of the present application provides a CBR signal rate transparent transmission system, including: the system comprises a source line card, a sink line card, a packet switching line card and a backplane, wherein the source line card, the sink line card and the packet switching line card are connected through the backplane;
the source line card is used for receiving the CBR signal sent by the first equipment, converting the CBR signal into a packet signal with a fixed length, counting the data volume N corresponding to the CBR signal within a preset time length T, and then sending the packet signal with the fixed length, the T and the N into the packet switching line card;
the packet switching line card is set to receive the packet signals with fixed length, T and N and forward the packet signals with fixed length, T and N to the sink line card after the switching processing;
and the sink line card is set to receive the packet signals with fixed length, T and N sent by the packet switching line card, recover the data of the CBR signals from the packet signals with fixed length, recover the rate of the CBR signals according to the T and the N, and send the obtained CBR signals to the second equipment.
Drawings
Fig. 1 is a flowchart of a method for transparently transmitting a CBR signal in a packet switching system according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a system for transparently transmitting CBR signals in a packet switching system according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of another system for transparently transmitting CBR signals in a packet switching system according to an embodiment of the present application.
Detailed Description
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
The basic principle of rate-transparent transmission of client signals in a communication device is as follows: firstly, a period T is generated by the rate of the service signal, T is a fixed value, for example, the time that the service signal sends M bits is used as T, T is periodic, namely the T period continuously appears, and the duration of each T period is equal. And calculating the bit number N of the client signal in each T period, wherein N may be in bit or Kbit, and K is an integer. And transmitting the N through overhead, obtaining T by the sink end, and then obtaining N, namely recovering the rate of the client signal according to the T and the N. In the above application scenario, the service signal is generally transmitted in the optical fiber, the service signal has a fixed rate, and the delay of the optical fiber transmission signal is fixed, so the period T generated by the source end according to the service signal rate can be easily obtained at the sink end.
In order to implement large-scale cross scheduling of a plurality of CBR signals of the same type, the CBR signals are required to be converted into packet signals at a source end, then the packet signals are introduced into a packet switching system at a middle point, packet switching is carried out through the packet switching system, then the packet signals generated at the middle point are sent to a destination end, the packet signals are recovered into the CBR signals at the destination end, cross scheduling of the CBR signals between a plurality of source disconnects and a plurality of destination ends is achieved through the packet switching, and the rate transparent transmission of the CBR signals is also required in the above process. Typical application scenarios for implementing cross scheduling of CBR signals through a packet switching system include large-scale SDH electrical cross equipment, large-scale OTN electrical cross equipment, and the like.
If the CBR signal implements cross-dispatching through the packet switching system, where the CBR signal corresponds to the client signal a and the packet signal corresponds to the service signal B, the transmission delay of the service signal B is fixed in the first scenario, but the transmission delay of the service signal B is not fixed in the packet switching system. The principle of the client signal a for implementing rate transparent transmission is the same, but if it is a packet switching scenario, since the transmission delay of the service signal B is not fixed, the T period cannot be generated by the rate of the service signal B according to the transmission fixed bit number N, because the period T is required to be uniform, that is, each period has the same length. Although the packet data can have a fixed rate before entering the packet switching system, the packet data reaches the destination end through the packet switching system, and the destination end cannot obtain a uniform T according to the received packet because the time spent by each packet is different. Therefore, the source end and the sink end are ensured to obtain the same and uniform T by other means in the packet switching system, wherein one implementation mode is that the source end and the sink end obtain the same and uniform T and do not necessarily use a clock card, the source end and the sink end use 1 reference clock respectively, the two reference clocks have the same frequency, namely the source end and the sink end respectively have a synchronous reference clock, M reference clock periods are used as T, M can be defined between the source end and the sink end in advance, and thus the source end and the sink end can obtain the same and uniform T. Then the source end needs to calculate the bit number N of the CBR signal in each T period, then the N value is transmitted to the sink end through a certain method, and the sink end recovers the rate of the CBR signal according to T and N.
In the prior art, the transfer of N is realized by packet length, that is, the number N of bits of a CBR signal in each T period is counted, N is converted into 8 × M which is relatively close, M is an integer, that is, the difference between 8 × M and N is less than plus or minus 8, then a packet of M bytes is generated and sent out, so that the sink can obtain the value N according to the length of the received packet. However, the packet length N obtained by this operation is changed, so the value of M is also changed, and finally, a packet with a variable length is obtained.
Fig. 1 is a flowchart of a method for transparently transmitting a CBR signal in a packet switching system according to an embodiment of the present disclosure, and as shown in fig. 1, the method according to the present disclosure includes the following steps.
Step S1010, a source end of the packet signal receives the CBR signal sent by the first device, converts the CBR signal into a packet signal with a fixed length, counts a data amount N corresponding to the CBR signal within a preset time length T, and then sends the packet signal with the fixed length, T, and N to a packet switching system.
The method for transparently transmitting the CBR signal in the packet switching system provided by this embodiment is applied to a system that converts the CBR signal into a packet signal and forwards the CBR signal. The system comprises a source end of a packet signal, a packet switching system and a sink end of the packet signal. The source end of the packet signal receives CBR signals sent by other equipment and converts the CBR signals into packet signals with fixed length, the packet switching system is used for forwarding the packet signals with fixed length between the source end of the packet signals and the sink end of the packet signals, and the sink end of the packet signals is used for recovering the received packet signals with fixed length into the CBR signals and then sending the CBR signals to other equipment. The device that transmits the CBR signal is referred to as a first device, and the device that receives the CBR signal is referred to as a second device. In the fixed-length packet signal generated at the source end of the packet signal, the length of the fixed-length packet signal is a fixed value, and the length of the fixed-length packet signal may be any integer value.
The packet switching system is arranged at an intermediate point between a source and a sink in the communication system. Since the transmission delay of a fixed-length packet signal in a packet switching system is uncertain, it is difficult to recover the rate of the CBR signal after the sink of the packet signal receives the packet data.
In one embodiment, the source end of the packet signal may send the fixed-length packet signal and the specific packet to the packet switching system after writing T and N into the specific packet. Or the source end of the packet signal may also carry T and N in a specific field in a specific data packet, and then send the specific field and the specific packet to the packet switching system. Writing T and N to a particular packet, including any of the following methods: additionally generating a specific packet containing T and N; writing T and N into a specific overhead of the CBR signal; t and N are written into the specific overhead of the fixed length packet signal corresponding to the CBR signal.
In this embodiment, after receiving the CBR signal sent by the first device, the source end of the packet signal first converts the CBR signal into a packet signal with a fixed length, and counts the data amount N corresponding to the CBR signal within the preset time length T. The preset time length T may be any time length, and the preset time length T may be set according to an actual situation. The predetermined time period T may be granular with reference clock cycles, that is, the predetermined time period T includes a predetermined number of reference clock cycles. The data amount N corresponding to the CBR signal within the preset time length T may be in bit, or may be in Kbit, where K is a positive integer. The CBR signal may be any signal transmitted at a fixed rate, such as an Optical Service Unit (OSU) signal, an Optical channel Data Unit (ODU) signal, and an SDH signal.
In an embodiment, the source end of the packet signal may periodically count m preset time lengths TiEach preset time length T in (i-1, …, m)iData quantity N corresponding to inner CBR signali(i ═ 1, …, m), m is a positive integer, and m can be infinite. Wherein T isi(i-1, …, m) is the same, i.e. m TiThe length of time identified between is equal, where equal is exactly equal. The source end of the packet signal will then Ti(i-1, …, m) and NiAfter writing the specific packet, (i ═ 1, …, m), the fixed-length packet signal and the specific packet are transmitted to the packet switching system. The preset time length TiCan be, for example, 1ms in value, can be realized in practical implementation with U periods of the reference clock V, and T must be greater in value than the packet signal in the packet-switched system from the packet signal sourceThe maximum possible value of the delay experienced by the transmission to the packet signal sink.
In an embodiment, the source end of the packet signal may count p preset time lengths D within the preset time length Dj(j 1, …, p) including a predetermined time period Ti(i is 1, …, m) by the number StjAnd StjA TiData quantity N corresponding to inner CBR signali(i is 1, …, m) and SnjWherein D is greater than T, m and p are positive integers, TiThe time lengths expressed between (i ═ 1, …, m) are equal, D is greater than T, and p is a positive integer. And m and p can be infinite. DjEach D of (j ═ 1, …, p)jAre not required to be exactly equal in length, i.e. DjThe time lengths indicated by (j — 1, …, p) may be equal or different. But each DjAre all greater than T. Then the source of the packet signal StjAnd SnjAfter writing the specific packet, the fixed-length packet signal and the specific packet are transmitted to the packet switching system. The source end of the packet signal may have any period D of separation greater than TjTransmission StjAnd SnjThe interval period D does not require each period to be strictly equal, only each period D needs to be allowedjAll are greater than T according to the interval period DjPeriodically counting p preset time lengths D1，D2，…，DpWithin each preset time length DjT contained in (j-1, …, p)iNumber St ofjAnd StjA TiCorresponding to NiSum of Snj。
In one embodiment, the source of the packet signal is at StjAfter completion and Stj+1Before coming, StjAnd SnjAfter writing the specific packet, the fixed-length packet signal and the specific packet are transmitted to the packet switching system. Wherein DjTo get StjAnd SnjTime interval between corresponding points in time when a particular packet is written, i.e. St, assuming current time a0And Sn0Written into a particular packet, St next occurring at time A + B1And Sn1An act of writing a particular packet, thenB is D1St occurs again at the next time A + B + C2And Sn2The action of writing a particular packet, time C is D2And so on. DjMay not be equal to each other.
Step S1020, the packet switching system receives the packet signals of fixed length, T and N, and forwards the packet signals of fixed length, T and N to the sink of the packet signals after performing switching processing.
The packet switching system has a function of only forwarding data and transmitting a fixed-length packet signal, T, and N to a destination of a corresponding packet signal according to destination address information of the fixed-length packet signal transmitted from a source of the packet data.
Step S1030, the sink of the packet signal receives the fixed-length packet signal, T, and N sent by the packet switching system, recovers the data of the CBR signal from the fixed-length packet signal, recovers the rate of the CBR signal according to T and N, and sends the obtained CBR signal to the second device.
Because the transmission delay of the packet switching system is uncertain, after the sink end of the packet signal receives the packet signal with fixed length, it is difficult to determine the rate of the CBR signal corresponding to the packet signal with fixed length. Thus, in this embodiment, the packet signal system forwards T and N simultaneously. After receiving the packet signals with fixed length, T and N sent by the packet switching system, the destination of the packet signals recovers the data of the CBR signals from the packet signals with fixed length, and recovers the rate of the CBR signals according to the T and the N, wherein the rate of the CBR signals is N/T. The destination of the packet signal can recover the CBR signal according to the rate of the CBR signal and the data of the CBR signal, thereby realizing transparent transmission of the CBR signal in the packet switching system. After the host end of the packet signal recovers the CBR signal, the recovered CBR signal can be sent to the second device, i.e., the receiving end of the CBR signal.
When a particular packet is received by a sink of a packet signal including StjAnd SnjWhere St isjP preset time lengths D in the preset time length Dj(j 1, …, p) including a predetermined time period Ti(i＝1, …, m), SnjIs StjA TiData quantity N corresponding to inner CBR signali(i is 1, …, m). Then the sink of the packet signal first derives St from the particular packetjAnd SnjThen according to StjAnd SnjTo obtain TiAnd NiFinally according to TiAnd NiThe rate of the CBR signal is recovered.
In an embodiment, the predetermined time length T includes a predetermined number of reference clock cycles, and the reference clock cycles of the source end of the packet signal and the sink end of the packet signal are the same. The source end of the packet signal and the sink end of the packet signal can obtain a reference clock period according to the synchronous reference clock, thereby ensuring that the reference clock frequencies of the source end of the packet signal and the sink end of the packet signal are equal. The elapsed time of V reference clock cycles may be used as the preset time length T at the source end of the packet signal and the sink end of the packet signal.
In the method for transparently transmitting a CBR signal in a packet switching system provided by this embodiment, after a source end of a packet signal receives a fixed-rate CBR signal sent by a first device, the CBR signal is converted into a fixed-length packet signal, a data amount N corresponding to the CBR signal within a preset time length T is counted, and then the fixed-length packet signal, T, and N are sent to the packet switching system, the packet switching system forwards the received fixed-length packet signal, T, and N to a sink end of the packet signal, the sink end of the packet signal recovers data of the CBR signal from the fixed-length packet signal, and sends the obtained CBR signal to a second device according to the rate at which the CBR signal is recovered by T and N, so that rate transparent transmission of the CBR signal is realized in the packet switching system, so that the CBR signal sent by the first device is forwarded by the packet switching system, the second device may receive a CBR signal that is correctly recovered from the packet-switched system.
Fig. 2 is a schematic structural diagram of a system for transparently transmitting a CBR signal in a packet switching system according to an embodiment, and as shown in fig. 2, the system for transparently transmitting a CBR signal in a packet switching system according to the embodiment includes: source line card 21, sink line card 22, packet switch line card 23, and backplane 24. The source line card 21, sink line card 22, and packet switch line card 23 are connected through a backplane 24.
The source line card 21 is configured to receive the CBR signal sent by the first device 31, convert the CBR signal into a packet signal with a fixed length, count a data volume N corresponding to the CBR signal within a preset time length T, and send the packet signal with the fixed length, T, and N to the packet switching line card 23;
a packet switching line card 23 configured to receive the fixed-length packet signals, T, and N, and forward the fixed-length packet signals, T, and N to the sink line card 22 after performing switching processing;
the sink line card 22 is configured to receive the fixed length packet signal, T, and N transmitted from the packet switch line card 23, recover data of the CBR signal from the fixed length packet signal, recover the rate of the CBR signal according to T and N, and transmit the obtained CBR signal to the second device 32.
The number of the source line cards 21 and the sink line cards 22 may be plural, and in this embodiment, one source line card 21 and one sink line card 22 are taken as an example for explanation. The first device 31 is a device that transmits a CBR signal, and may also be referred to as a source of the CBR signal, and the second device 32 is a device that receives the CBR signal, and may also be referred to as a sink of the CBR signal.
The specific method for performing CBR signal rate transparent transmission in the system for transparent transmission of CBR signals in the packet switching system has been described in detail in the embodiment shown in fig. 1, and the implementation principle and technical effect are similar, and are not described in detail in this embodiment.
Further, in the embodiment shown in fig. 2, the source line card 21 is specifically configured to send the fixed-length packet signal and the specific packet to the packet switching line card 23 after writing T and N into the specific packet.
Further, in the embodiment shown in fig. 2, the source line card 21 is specifically configured to write T and N into a specific packet by any one of the following methods: additionally generating a specific packet containing T and N; writing T and N into a specific overhead of the CBR signal; t and N are written into the specific overhead of the fixed length packet signal corresponding to the CBR signal.
Further, in the embodiment shown in fig. 2, the source line card 21 is specifically configured to periodically count m preset time lengths TiEach preset time length T in (i-1, …, m)iData quantity N corresponding to inner CBR signali(i-1, …, m), m is a positive integer, Ti(i ═ 1, …, m) are equal in length; will Ti(i-1, …, m) and NiAfter writing the specific packet, (i ═ 1, …, m), the fixed-length packet signal and the specific packet are transmitted to the packet switch line card 23.
Further, in the embodiment shown in fig. 2, the source line card 21 is specifically configured to count p preset time lengths D within the preset time length Dj(j 1, …, p) contains a preset time length Ti(i is 1, …, m) by the number StjAnd StjA TiData quantity N corresponding to inner CBR signali(i is 1, …, m) and SnjD is greater than T, m and p are positive integers, Ti(i ═ 1, …, m) are equal in length; st isjAnd SnjAfter writing the specific packet, the fixed-length packet signal and the specific packet are transmitted to the packet switch line card 23.
Further, in the embodiment shown in FIG. 2, sink line card 22 is specifically configured to derive St from a particular packetjAnd Snj(ii) a According to StjAnd SnjTo obtain TiAnd NiAccording to TiAnd NiThe rate of the CBR signal is recovered.
Further, in the embodiment shown in fig. 2, the source line card 21 is specifically set at StjAfter completion and Stj+1Before coming, StjAnd SnjAfter writing the specific packet, the fixed-length packet signal and the specific packet are transmitted to the packet switch line card 23.
Further, in the embodiment shown in fig. 2, T includes a preset number of reference clock cycles, and the reference clock cycles of the source line card 21 and the sink line card 22 are the same.
Fig. 3 is a schematic structural diagram of another system for transparently transmitting a CBR signal in a packet switching system according to an embodiment, and as shown in fig. 3, the system for transparently transmitting a CBR signal in a packet switching system according to the embodiment further includes, on the basis of fig. 2:
and the clock card 25, the clock card 25 is connected to the backplane 24, the clock card 25 is configured to generate a synchronous reference clock and send the synchronous reference clock to the source line card 21 and the sink line card 22, and the source line card 21 and the sink line card 22 obtain a reference clock cycle according to the synchronous reference clock.
The solid line path in the figure is a CBR signal transmission path, that is, the CBR signal passes through the source line card 21, the backplane 24, the packet switching line card 23, the backplane 24, and the sink line card 22 in sequence from the first device 31 and finally reaches the second device 32. The dashed path is a reference clock path, i.e. clock card 25 sends synchronous reference clocks to source line card 21 and sink line card 22, respectively.
The above are merely exemplary embodiments of the present application, and are not intended to limit the scope of the present application.
It will be clear to a person skilled in the art that the term user terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser or a car mounted mobile station.
In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
Embodiments of the application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages.
Any logic flow block diagrams in the figures of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read-Only Memory (ROM), Random-Access Memory (RAM), optical storage devices and systems (Digital versatile disks (DVD) or Compact Disks (CD)), etc., the computer-readable medium can comprise a non-transitory storage medium, the data processor can be of any type suitable to the local technical environment, such as, but not limited to, general purpose computers, special purpose computers, microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated circuits (SAICs), Programmable logic devices (FGPAs), and processors based on a multi-core processor architecture.
Claims (14)
1. A method for transparent transmission of CBR signals in a packet switched system, comprising:
a source end of a packet signal receives a fixed-rate CBR signal sent by first equipment, the CBR signal is converted into a fixed-length packet signal, data volume N corresponding to the CBR signal in a preset time length T is counted, and then the fixed-length packet signal, the T and the N are sent to a packet switching system;
the packet switching system receives the fixed length packet signals, the T and the N and forwards the fixed length packet signals, the T and the N to a sink end of the packet signals after switching processing;
the destination end of the packet signal receives the packet signal with fixed length, the T and the N which are sent by the packet switching system, recovers the data of the CBR signal from the packet signal with fixed length, and sends the obtained CBR signal to second equipment according to the rate of recovering the CBR signal from the T and the N;
the counting of the data volume N corresponding to the CBR signal within the preset time length T includes:
periodically counting m preset time lengths TiEach preset time length T in (i-1, …, m)iThe data volume N corresponding to the CBR signali(i-1, …, m), m is a positive integer, Ti(i ═ 1, …, m) are equal in length;
after writing the T and the N into a specific packet, the transmitting the fixed-length packet signal and the specific packet to the packet switching system includes:
will be the Ti(i ═ 1, …, m) and said Ni(i-1, …, m) writing a specific packet, and then transmitting the fixed-length packet signal and the specific packet to the packet switching system;
the periodic statistics is carried out on m preset time lengths TiEach preset time length T in (i-1, …, m)iThe data volume N corresponding to the CBR signali(i ═ 1, …, m), comprising:
counting p preset time lengths D in the preset time length Dj(j 1, …, p) contains a preset time length Ti(i is 1, …, m) by the number StjAnd StjA TiThe data volume N corresponding to the CBR signali(i is 1, …, m) and SnjD is greater than T, m and p are positive integers, Ti(i ═ 1, …, m) are equal in length;
the said will be Ti(i ═ 1, …, m) and said Ni(i-1, …, m) writing a specific packet, and then transmitting the fixed-length packet signal and the specific packet to the packet switching system, the packet switching system including:
the St isjAnd said SnjAfter writing a specific packet, transmitting the fixed-length packet signal and the specific packet to the slaveA group switching system.
2. The method of claim 1, wherein said sending said fixed length packet signals, said T and said N into a packet switched system comprises:
after writing the T and the N into a specific packet, the fixed-length packet signal and the specific packet are transmitted to the packet switching system.
3. The method of claim 2, wherein said writing said T and said N into a particular packet comprises any one of:
additionally generating a specific packet containing said T and said N;
writing the T and the N into a specific overhead of the CBR signal;
writing the T and the N into a specific overhead of a fixed-length packet signal corresponding to the CBR signal.
4. The method of claim 1, wherein the rate at which the CBR signal is recovered based on the T and the N comprises:
deriving said St from said specific groupingjAnd said Snj；
According to said StjAnd said SnjObtaining the TiAnd said Ni；
According to the TiAnd said NiRecovering the rate of the CBR signal.
5. Method according to claim 1, characterised in that said St is combinedjAnd said SnjAfter writing a specific packet, transmitting the fixed-length packet signal and the specific packet to the packet switching system, including:
at said StjAfter completion and Stj+1Before coming, the StjAnd said SnjAfter writing a particular packet, the solids are writtenThe packet signal of the fixed length and the specific packet are transmitted to the packet switching system.
6. The method according to any of claims 1-5, wherein T comprises a preset number of reference clock cycles, and the reference clock cycles of the source end of the packet signal and the sink end of the packet signal are the same.
7. The method of claim 6, further comprising:
and generating a synchronous reference clock by a common clock unit, sending the synchronous reference clock to the source end of the packet signal and the sink end of the packet signal, and obtaining the reference clock period by the source end of the packet signal and the sink end of the packet signal according to the synchronous reference clock.
8. A system for transparent transmission of CBR signals in a packet switched system, comprising: the system comprises a source line card, a sink line card, a packet switching line card and a backplane, wherein the source line card, the sink line card and the packet switching line card are connected through the backplane;
the source line card is configured to receive a fixed-rate CBR signal sent by first equipment, convert the CBR signal into a fixed-length packet signal, count a data volume N corresponding to the CBR signal within a preset time length T, and send the fixed-length packet signal, the T and the N to a packet switching line card;
the packet switching line card is configured to receive the fixed length packet signals, the T and the N, and forward the fixed length packet signals, the T and the N to a sink line card after switching processing;
the sink line card is configured to receive the fixed-length packet signal, the T and the N sent by the packet switch line card, recover data of the CBR signal from the fixed-length packet signal, recover a rate of the CBR signal according to the T and the N, and send the obtained CBR signal to a second device;
the source line card is specifically set to periodically count m preset time lengths TiEach preset time length T in (i-1, …, m)iThe data volume N corresponding to the CBR signali(i-1, …, m), m is a positive integer, Ti(i ═ 1, …, m) are equal in length; will be the Ti(i ═ 1, …, m) and said Ni(i-1, …, m) after writing a specific packet, transmitting the fixed-length packet signal and the specific packet to the packet switching line card; the source line card is specifically set to count p preset time lengths D in the preset time lengths Dj(j 1, …, p) contains a preset time length Ti(i is 1, …, m) by the number StjAnd StjA TiThe data volume N corresponding to the CBR signali(i is 1, …, m) and SnjD is greater than T, m and p are positive integers, Ti(i ═ 1, …, m) are equal in length; the St isjAnd said SnjAfter writing a specific packet, the fixed-length packet signal and the specific packet are transmitted to the packet switching line card.
9. The system according to claim 8, wherein said source linecard is specifically configured to send said fixed length packet signals and said specific packets to said packet switch linecard after writing said T and said N into specific packets.
10. The system according to claim 9, wherein the source linecard is specifically configured to write the T and N into a particular packet by any one of:
additionally generating a specific packet containing said T and said N;
writing the T and the N into a specific overhead of the CBR signal;
writing the T and the N into a specific overhead of a fixed-length packet signal corresponding to the CBR signal.
11. System according to claim 8, characterized in that said sink line card is specifically arranged to derive said St from said specific packetsjAnd said Snj(ii) a According to said StjAnd said SnjObtaining the TiAnd said NiAccording to said TiAnd said NiRecovering the rate of the CBR signal.
12. The system according to claim 8, wherein the source linecard is specifically configured to be at the StjAfter completion and Stj+1Before coming, the StjAnd said SnjAfter writing a specific packet, the fixed-length packet signal and the specific packet are transmitted to the packet switching line card.
13. The system according to any of claims 8-12, wherein T comprises a preset number of reference clock cycles, and wherein the reference clock cycles of the source line card and the sink line card are the same.
14. The system of claim 13, further comprising a clock card, wherein the clock card is coupled to the backplane, wherein the clock card is configured to generate a synchronous reference clock and send the synchronous reference clock to the source line card and the sink line card, and wherein the source line card and the sink line card derive the reference clock period according to the synchronous reference clock.
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