CN112165244A - Output current-sharing control method for master-slave parallel inverter - Google Patents

Output current-sharing control method for master-slave parallel inverter Download PDF

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CN112165244A
CN112165244A CN202011155276.9A CN202011155276A CN112165244A CN 112165244 A CN112165244 A CN 112165244A CN 202011155276 A CN202011155276 A CN 202011155276A CN 112165244 A CN112165244 A CN 112165244A
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CN112165244B (en
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王成悦
马兰新
张海明
罗四平
赵艺雷
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Hefei Tongzhi Electrical Control Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques

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Abstract

The invention discloses an output current-sharing control method of a master-slave parallel inverter in the field of parallel control of inverters, which is characterized in that an inverter host machine detects output current fundamental waves and each harmonic wave, and the output current fundamental waves and each harmonic wave are shared to an inverter slave machine in real time through a high-speed CAN communication bus, the inverter slave machine receives output current information shared by the inverter host machine and synthesizes reference current, and the output current tracks the reference current without dead difference through current closed-loop PI control, so that current fundamental waves and each harmonic wave are controlled in a current-sharing manner. The method has the advantages of small computation amount, high computation precision and good real-time performance, and when the output end is suddenly put into a nonlinear load with large capacity, the fundamental wave and each harmonic can also realize dynamic current sharing; the control structure is simple, is not influenced by the difference between the output impedance of the inverter and the line impedance, can realize hot plug in practical application, and can not influence the operation of a control system when one or more inverters are connected or disconnected.

Description

Output current-sharing control method for master-slave parallel inverter
Technical Field
The invention relates to the field of inverter parallel control, in particular to a master-slave parallel inverter output current-sharing control method.
Background
The increasing of various electric equipment leads to higher and higher requirements on the capacity and reliability of a power supply method, the requirement cannot be met by an alternating current power supply method of a single inverter, and the parallel technology of the inverters is required. In order to fully utilize the capacity of the parallel system and maximize the reliability of the parallel system, current sharing among the inverters is required to be realized, so that the parallel connection of the inverters needs corresponding current sharing control.
Compared with the parallel connection of direct current power supplies, the parallel connection of inverters needs to consider the consistency of parameters such as amplitude, frequency, phase, harmonic waves and the like of output voltage. At present, the inverter parallel current sharing control method includes centralized control, master-slave control, distributed logic control and droop control. Wherein, the centralized control sends an output voltage phase synchronization signal and a load current reference value to each inverter through a centralized control unit to realize the balance of the output current of the inverters; in the master-slave control, one inverter is used as a master machine and operates in a voltage control mode, and the rest N-1 inverters are used as slave machines and work in a current control mode, namely, one voltage source is connected with N-1 current sources in parallel; the positions of the inverters in the distributed logic control and the droop control are the same, the inverters do not have a master-slave part, the inverters operate in a voltage control mode, the amplitude and the phase of an output voltage reference are controlled through active power and reactive power output by the inverters, and therefore current sharing of a parallel system is achieved.
The inverter parallel control method has the following problems: the centralized control only has one centralized control unit, if the control unit fails, the whole inverter parallel system is in a breakdown state, redundancy and hot plugging cannot be realized, so that the reliability is low, and the control method is rarely used. Secondly, the reliability of the master-slave control depends heavily on the host, and once the host goes wrong and stops working, the whole method can be forced to be closed. If the master machine is switched out of the method when the master machine has a fault, one slave machine is switched to the master machine, and the working mode of the slave machine is converted from current source output to voltage source output, the problem can be solved. The common defects of the distributed logic control and the droop control are as follows: a power regulation mode is adopted, so that the regulation lags one fundamental wave period, and the dynamic performance is poor; the control target is the amplitude and frequency of the reference voltage, i.e. the current sharing is achieved at the expense of the accuracy of the inverter amplitude and frequency, which affects the power quality of the output voltage.
Particularly, when the inverter parallel system supplies power to the nonlinear load, if the control method adopts distributed logic control or droop control, each inverter operates in a voltage control mode, the harmonic wave carried by the nonlinear load can influence the adjustment of the frequency and voltage of the parallel system, so that the output power between the inverters cannot be well coordinated and controlled, the average accuracy of the fundamental wave and the harmonic wave power of the parallel system is reduced, and particularly, when the output impedance and the line impedance of each parallel inverter have difference, the harmonic wave current average accuracy is difficult to guarantee. When the output end of the parallel system is suddenly put into a large-capacity nonlinear load, if the instantaneous harmonic power difference of each parallel inverter is large, the output current peak value of one inverter may exceed the maximum tolerable current of a power switch tube, so that the switch tube fails, and the safety and reliability of the operation of the parallel system are seriously threatened.
In the thesis, each inverter adopts voltage and current double-loop control, and carries out closed-loop PI regulation on a plurality of currents aiming at current fundamental waves and current harmonics of each frequency at the same time, and then outputs the current loops, and the current loops are subjected to coordinate transformation and superposed on a voltage outer loop to be output as current sharing control quantity. The method has the disadvantages that the control method is complex, the software computation is large, the code execution time is long, the improvement of the system control bandwidth is seriously restricted, and the waveform quality of the output voltage is influenced; in addition, the control method needs to calculate the current mean value according to the number of the inverters which are actually operated in parallel, and once one or more inverters are switched in or out, the current mean value control is influenced, so that hot plug cannot be realized.
The applicant proposes an improvement scheme for realizing accurate extraction of fundamental wave and harmonic component of output current of a host, sharing the fundamental wave and harmonic component to each slave in real time and undistorted manner, reducing the difficulty of architecture and simplifying the calculation amount, and being the difficulty of output current sharing control of a master-slave inverter parallel method.
Disclosure of Invention
The present invention provides a method for controlling output current sharing of a master-slave parallel inverter, so as to solve the problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
a master-slave parallel inverter output current sharing control method comprises the following steps:
step 1: the inverter host samples and reads the output voltage and the inductive current of the inverter host in each control period through a digital signal processor;
step 2: according to the detected output voltage and the detected inductance current value, the inverter host is started in a voltage control mode, and voltage is established on an alternating-current side bus;
and step 3: according to the detected output voltage and inductance current value, the inverter host extracts a current fundamental component i under a two-phase static alpha beta coordinate system through a multi-double-generalized second-order integrator module in the current control periodL1αAnd iL1βThe major subharmonic component i of the currentLhαAnd iLhβH is the harmonic number;
and 4, step 4: according to frequency f and phase angle theta of fundamental component of output reference voltageiThe inverter host calculates the frequency and phase angle of the fundamental wave of the current output in the current control period and the frequency and phase angle of each main subharmonic component of the current;
and 5: in the current control period, the inverter host calculates the active component of the current fundamental wave under the rotating dq coordinate system through the Park conversion moduleiL1dAnd a reactive component iL1qAnd the active component i of each major sub-harmonic of the currentLhdAnd a reactive component iLhq；
Step 6: calculating to obtain the active component average value i of the current fundamental wave in n control periodsL1d_avgAverage value of reactive component iL1q_avgAnd the average value i of the active components of the major sub-harmonics of the currentLhd_avgAnd the average value of reactive components iLhq_avgAnd sharing to each inverter slave machine in real time through CAN bus, wherein
Figure BDA0002742577940000031
TcomIndicating the communication transmission time, T, of the current data of the inverter master to the inverter slavecRepresents a control period;
and 7: inverter slave machine synthesizes self reference current i based on current data shared by inverter master machineL_refAnd the output inductive current of the self-body tracks the reference current i through the control of a current closed loop PI regulatorL_ref。
As a modified scheme of the invention, the step 7 comprises the following steps:
step 7.1: the inverter slave machine samples and reads the output voltage, the inductive current and the alternating-current side bus voltage of the inverter slave machine in each control period through a digital signal processor;
step 7.2: according to the detected AC side bus voltage, the inverter slave machine detects the amplitude, the frequency and the phase angle of the fundamental wave component of the AC side bus voltage through a phase-locked loop module;
step 7.3: the inverter slave machine judges whether the phase-locked loop detection is successful: if yes, the step 7.4 is carried out, and if not, the step 7.2 is carried out;
step 7.4: according to the detected output voltage and the detected inductance current value, the inverter slave machine is started in a current control mode, and inverts and outputs the voltage with the same amplitude and phase angle as the common bus to realize the parallel operation with the inverter host machine;
step 7.5: according to the frequency and the phase angle of the bus voltage at the alternating current side, the inverter slave computer calculates the frequency and the phase angle of the fundamental component of the output reference current and the frequency and the phase angle of each main subharmonic component of the reference current;
step 7.6: the inverter slave machine judges whether current data of current fundamental waves and current major subharmonics from the inverter master machine are received from the CAN bus: if yes, go to step 7.7, if no, go to step 7.5;
step 7.7: in the current period, the inverter slave machine calculates the alpha beta component of the fundamental wave of the reference current and the alpha beta component of each major subharmonic in the two-phase static alpha beta coordinate system through Park inverse transformation, and then the alpha component of the fundamental wave of the reference current and the alpha component of each major subharmonic are superposed to obtain the total reference current i of the inverter slave machineL_ref；
Step 7.8: the inverter slave machine is controlled by a current closed loop PI regulator, so that the output inductive current of the inverter slave machine tracks the reference current iL_ref。
In step 7.2, the inverter slave unit adopts a phase-locked loop module, and controls to enable the fundamental wave reactive component v of the alternating-current side bus voltage to be controlled through a PI regulatorqIs 0.
As an improvement of the present invention, in step 7.3, the condition for determining that the inverter slave phase-locked loop is successfully detected is as follows: simultaneously satisfies the voltage fundamental wave reactive component v of the alternating-current side busq＜2％·UedAnd a voltage fundamental active component vd＞95％·UedAnd maintaining at least one fundamental period, UedAnd outputting rated voltage amplitude for the inverter slave machine.
As a development of the invention, in step 7.5, the phase angle of the bus voltage on the AC side is θu′，
Figure BDA0002742577940000041
Figure BDA0002742577940000042
Wherein the content of the first and second substances,
Figure BDA0002742577940000043
for the initiation of the AC-side bus voltageThe phase angle (f) is the frequency of the fundamental wave component of the AC side bus voltage and the inverter slave machine reference current, and the phase angle theta of the fundamental wave component of the inverter slave machine reference currenti′＝θu', the frequency of each major subharmonic component of the reference current is h.f, the phase angle
Figure BDA0002742577940000044
As a modified solution of the present invention, in step 7.7, the calculation formula of the fundamental wave α β component of the reference current is:
Figure BDA0002742577940000045
the calculation formula of each main subharmonic alpha beta component of the reference current is as follows:
Figure BDA0002742577940000046
total reference current i of inverter slaveL_refThe calculation formula of (2) is as follows:
iL_ref＝iL1α_ref+∑iLhα_ref。
as a development of the invention, in step 5, the active component i of the fundamental wave of the current isL1dAnd a reactive component iL1qThe calculation formula of (2) is as follows:
Figure BDA0002742577940000051
active component i of each major sub-harmonic of the currentLhdAnd a reactive component iLhqThe calculation formula of (2) is as follows:
Figure BDA0002742577940000052
wherein, thetahiThe phase angle of each major sub-harmonic component of the current,
Figure BDA0002742577940000053
the frequency of each major harmonic component of the current is h.f, f is the frequency of the fundamental component of the reference voltage and the output current, and the phase angle theta of the fundamental component of the output currenti＝θu，
Figure BDA0002742577940000054
Is the initial phase angle of the voltage.
As a modification of the invention, in step 6, the average value i of the active components of the major sub-harmonics of the current in n control periodsLhd_avgAnd the average value of reactive components iLhq_avgThe calculation formula of (2) is as follows:
Figure BDA0002742577940000055
when h is 1, the calculation formula is the active component average value i of the current fundamental wave in n control periodsL1d_avgAverage value of reactive component iL1q_avgThe calculation formula of (2).
In a further embodiment of the present invention, in step 6, n is 5.
Has the advantages that: firstly, the inverter host machine adopts a multi-double generalized second order integrator (MSOGI) module to realize the extraction of output current fundamental wave components and main subharmonic wave components under a two-phase static alpha beta coordinate system, the operation amount is small, the calculation precision is high, the real-time performance is good, and if a nonlinear load with large capacity is suddenly input at the output end, the fundamental wave and each subharmonic wave can also realize dynamic current sharing.
Secondly, the inverter host operates in a voltage control mode, the inverter slave operates in a current control mode, the inverter slave receives output current information shared by the inverter host and synthesizes reference current, current sharing of fundamental wave components and main subharmonic components of the output current is realized through control of a current closed-loop PI regulator, and the control architecture is simple and is not influenced by difference of output impedance and line impedance of the inverter.
Thirdly, the inverter host shares the calculated current data to the slave computer in real time through the CAN bus, calculation of the mean value of all the inverter currents is not needed, hot plugging CAN be realized in practical application while the calculated amount is small, one or more inverters are connected or disconnected, the operation of a control system is not influenced, and the calculated amount is greatly reduced compared with the prior art.
Fourthly, the invention is not only suitable for nonlinear loads, but also can be applied to linear loads, when the output is connected with the linear loads, the difference is that the harmonic component of each time of the current detected by the inverter host is extremely small, the current-sharing control of the fundamental wave component is not influenced, the invention has good load adaptability, and the operation stability and reliability of the parallel system of the inverter connected with various linear and nonlinear loads are effectively improved.
Drawings
FIG. 1 is a control block diagram of a master-slave single-phase full-bridge inverter parallel system;
FIG. 2 is a flow chart of the inverter main unit output current fundamental and harmonic detection method of the present invention;
FIG. 3 is a schematic diagram of the present invention for current fundamental and harmonic component extraction by a multiple bigeneralized second order integrator (MSOGI);
FIG. 4 is a flow chart of current sharing control of the slave output current fundamental wave and each harmonic of the inverter of the invention;
FIG. 5 is a test waveform of the output voltage and current when the output of the parallel system is connected to the rated capacity linear load, using the single-phase full-bridge inverter as an example;
fig. 6 shows test waveforms of output voltage and current when the output of the parallel system is connected to a rated capacity nonlinear load, taking a single-phase full-bridge inverter as an example.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a single-phase full-bridge inverter is taken as an example, in the single-phase full-bridge inversion parallel system, an inverter main machine works in a voltage control mode (a voltage outer ring and a current inner ring) to give a voltage of UrefAnd an output voltage Uo1The instantaneous feedback value is compared to obtain an error signal, the error signal passes through a control quantity obtained by a voltage loop controller Gv and is compared with an output load current Io1Is superimposed as a current loop given Iref1，Iref1And the inductive current IL1The instantaneous feedback value is differentiated, modulated by a current loop controller Gi, and the output modulation signal and the output voltage feedforward signal U are outputo1And (4) superposing to obtain a total modulation signal of the control link of the inverter host, and intercepting the modulation signal and the triangular carrier signal to obtain a duty ratio signal of a PWM pulse to drive a power switch tube.
And the voltage loop controller Gv and the current loop controller Gi both adopt PI regulators.
Each inverter slave operates in a current control mode (current inner loop), only one inverter slave is shown in fig. 1, and the number of the inverter slaves can be increased according to practical application. After the inverter master machine is started and output voltage is established on the AC side bus, the inverter slave machine detects the frequency and phase angle information of the AC side bus voltage through a software phase-locked loop (SPLL), and then multiplies the phase angle value detected by the SPLL according to the received master machine current amplitude signal to obtain a current instruction signal Iref2，Iref2And the inductive current IL2And (3) making a difference on the instantaneous feedback value, modulating by a current inner loop PI controller Gi, superposing the output modulation signal with an alternating-current side bus voltage feedforward signal to obtain a total modulation signal of the inverter slave control link, intercepting the signal with a triangular carrier signal to obtain a duty ratio signal of PWM (pulse width modulation) pulse, and driving a power switch tube.
When the output of the single-phase full-bridge inversion parallel system is connected with a nonlinear load, if the master machine of the inverter can accurately detect and obtain the fundamental wave of the load current and the amplitude and the phase information of each major subharmonic component, and the amplitude and the phase information are shared to each slave machine, because the direct control object of the slave machine is the output inductive current, the current sharing of the fundamental wave and the harmonic current output by the master machine and each slave machine is easily realized, and the influence of the difference of the output impedance and the line impedance of the inverter is avoided. Although the master-slave inverter parallel connection needs to be realized by means of communication interconnection lines, in practical application, the parallel inverters need to know the state information of each other, the interconnection lines cannot be avoided, and the use influence on a parallel system cannot be caused.
Therefore, referring to fig. 2, the present embodiment provides a method for controlling output current sharing of a master-slave parallel inverter, and provides a specific step for accurately extracting fundamental wave and harmonic component of output current of a host, where the specific step is as follows:
step 1: the inverter host samples and reads the output voltage and the inductive current of the inverter host in each control period through a Digital Signal Processor (DSP);
step 2: according to the detected output voltage and the detected inductance current value, the inverter host is started in a voltage control mode, and voltage is established on an alternating-current side bus;
and step 3: according to the detected output voltage and inductance current value, the inverter host extracts a current fundamental component i under a two-phase static alpha beta coordinate system through a multi-double generalized second-order integrator (MSOGI) module in the current control periodL1αAnd iL1βThe major subharmonic component i of the currentLhαAnd iLhβAnd h represents the harmonic order.
In this embodiment, the output of the single-phase full-bridge inversion parallel system is connected to a nonlinear load, the nonlinear load is generally a rectification load, the harmonics on the ac side of the single-phase uncontrollable rectification circuit of the capacitive filtering are all odd harmonics, and the lower the harmonic frequency, the larger the harmonic amplitude, and mainly distributed in the frequency band ranges of the 3 rd, 5 th and 7 th harmonics, so that when the current fundamental wave and harmonic component are extracted by a multiple double generalized second-order integrator (MSOGI) in fig. 3, the major harmonic frequency h is 3, 5, 7. However, the number of harmonics is not limited in this embodiment, and in practical applications, the number of harmonics that should be equally divided into odd harmonics or even harmonics may be designated as the primary harmonics, i.e., h may be an odd harmonic or an even harmonic, depending on the characteristics of the load. The number of the harmonic order is not limited, and the number of the major harmonics may be one or more.
And 4, step 4: according to frequency f and phase angle theta of fundamental component of output reference voltageiThe inverter host calculates the frequency and phase angle of the fundamental wave of the current output in the current control period and the frequency and phase angle of each main subharmonic component of the current;
the inverter main machine is in a voltage control mode, the output reference voltage is set through software, the frequency and the phase angle are known, and then
Figure BDA0002742577940000081
f is the frequency of the reference voltage,
Figure BDA0002742577940000082
is the initial phase angle of the voltage. The inverter main machine is controlled by a voltage closed loop PI regulator, so that the actual output voltage completely tracks the reference voltage, and the frequency and the phase angle of the output voltage and the current fundamental wave component of the inverter main machine are the same as those of the reference voltage. Therefore, the fundamental component of the output current has the same frequency f and the phase angle thetai＝θuThe frequency of each major subharmonic component of the current is h.f, the phase angle
Figure BDA0002742577940000083
Figure BDA0002742577940000084
And 5: in the current control period, the inverter host calculates the active component i of the current fundamental wave under the rotating dq coordinate system through a Park conversion moduleL1dAnd a reactive component iL1qAnd the active component i of each major sub-harmonic of the currentLhdAnd a reactive component iLhq；
In particular, the active component i of the fundamental current waveL1dAnd a reactive component iL1qThe calculation formula of (2) is as follows:
Figure BDA0002742577940000085
active component i of each major sub-harmonic of the currentLhdAnd a reactive component iLhqThe calculation formula of (2) is as follows:
Figure BDA0002742577940000086
step 6: calculating to obtain the active component average value i of the current fundamental wave in n periodsL1d_avgAverage value of reactive component iL1q_avgAnd the average value i of the active components of the major sub-harmonics of the currentLhd_avgAnd the average value of reactive components iLhq_avgAnd sharing the signals to each inverter slave machine in real time through a CAN bus;
in particular, the average value i of the active components of the major sub-harmonics of the current in n periodsLhd_avgAnd the average value of reactive components iLhq_avgThe calculation formula of (2) is as follows:
Figure BDA0002742577940000091
when h is 1, the calculation formula can obtain the active component average value i of the current fundamental wave in n periodsL1d_avgAverage value of reactive component iL1q_avg。
The inverter host shares the sent current data to each inverter slave machine in real time through the CAN bus, and is used for ensuring good dynamic current sharing between the inverter host and each inverter slave machine. In practical application, the CAN bus of the TMS320F28335 DSP digital signal processor which is currently mainstream supports a data rate of 1Mbps at most, but the inverter slave cannot receive the latest data from the master in real time in each control cycle, so that the data updating time is prolonged to n control cycles, wherein the data updating time is n control cycles
Figure BDA0002742577940000092
TcomThe communication transmission time (CAN bus data rate 1Mbps) for transmitting the current data of the inverter host to the inverter slave is showncPresentation controlAnd (4) period.
The upper limit of the number n of cycles is not limited, but the excessive number of cycles CAN cause longer control delay of an inverter parallel system and influence dynamic current sharing performance, so that n is preferably 5, on one hand, under the condition that the CAN bus communication efficiency is 1Mbps, an inverter slave machine CAN be ensured to share latest current data information in real time, and the real-time requirement of the inverter slave machine for receiving current data is met; on the other hand, the current fundamental wave and the main subharmonic active and reactive components under the rotating dq coordinate system are direct current quantities, arithmetic mean filtering processing is carried out on the direct current quantities, data distortion cannot be caused, meanwhile, the switching frequency of an inverter parallel system is high, and the control period is short, so that the influence of control delay of 5 control periods on the dynamic response performance of the output current is small.
And 7: inverter slave machine synthesizes self reference current i based on current data shared by inverter master machineL_refAnd the output inductive current of the self-body tracks the reference current i through the control of a current closed loop PI regulatorL_refAnd the current sharing of fundamental waves and harmonic waves between the inverter master machine and each inverter slave machine is realized.
In the embodiment, the inverter main machine works in a voltage control mode, runs in a voltage source mode and establishes voltage on the output alternating current bus; the inverter slave machine works in a current control mode, and the direct control object of the inverter slave machine is output inductive current, so that the current sharing of fundamental wave and harmonic current output by the master machine and each slave machine is easily realized, and the accuracy of the amplitude and the frequency of output voltage is not influenced while the stable and dynamic current sharing effects are good.
Because the inverter host machine adopts a multi-double generalized second order integrator (MSOGI) module to realize the extraction of output current fundamental wave components and main subharmonic wave components under a two-phase static alpha beta coordinate system, the operation amount is small, the calculation precision is high, the real-time performance is good, and dynamic current sharing can be realized for the fundamental wave and each subharmonic wave when a large-capacity nonlinear load is suddenly input at the output end. The invention is not only suitable for nonlinear loads, but also can be applied to linear loads, when the output is connected with the linear loads, the difference is that the harmonic component of each time of the current detected by the inverter host is extremely small, the current-sharing control of the fundamental wave component is not influenced, the invention has good load adaptability, and the operation stability and reliability of the parallel system of the inverter connected with various linear and nonlinear loads are effectively improved.
In addition, the inverter host shares the calculated current data to the slave machine in real time through the CAN bus, calculation of the average value of the output currents of all the inverters is not needed, hot plugging CAN be realized in practical application while the calculated amount is small, one or more inverters are connected or disconnected, the operation of a control system is not influenced, and the calculated amount is greatly reduced compared with the prior art.
Compared with the prior art, the method has the advantages that the calculation is relatively simple, the software implementation is easy, the complex fundamental wave, harmonic power calculation and virtual impedance control are not needed, the higher electric energy quality of the output voltage of the inverter parallel system is ensured, and the operation stability and the reliability of the system accessing various linear and nonlinear loads are improved.
Further, as shown in fig. 4, step 7 includes the following steps:
step 7.1: the inverter slave machine samples and reads the output voltage, the inductive current and the alternating-current side bus voltage of the inverter slave machine in each control period through a Digital Signal Processor (DSP);
step 7.2: according to the detected AC side bus voltage, the inverter slave machine detects the amplitude, the frequency and the phase angle of the fundamental wave component of the AC side bus voltage through a phase-locked loop module (SPLL); since the present embodiment takes a single-phase full-bridge inverse parallel system as an example, the phase-locked loop module uses a single-phase voltage phase-locked technique based on a generalized integrator (SOGI) module, and is capable of generating a two-phase orthogonal signal with the same phase as the input voltage signal v and a phase difference of 90 °, and the two orthogonal components are used to replace a voltage fundamental component v in a two-phase stationary α β coordinate system in a typical three-phase-locked loopαβ。
It should be understood by those skilled in the art that the output current-sharing control method for the master-slave parallel inverter provided in this embodiment can also be applied to a three-phase inverter parallel system, the principle is the same as that applied to a single-phase full-bridge inverter parallel system, and phase locking of three-phase voltages by using a phase-locked loop module is a known technology in the art and will not be described herein.
Step 7.3: the inverter slave machine judges whether the phase-locked loop detection is successful: if yes, the step 7.4 is carried out, and if not, the step 7.2 is carried out;
the inverter slave adopts the phase-locked loop technology of a single-phase generalized integrator (SOGI), and controls to enable the voltage fundamental wave reactive component v of the alternating-current side bus to be controlled by a PI regulatorqIs 0, then the voltage fundamental wave active component vdEqual to the amplitude of the ac side bus voltage. The conditions for judging the success detection of the inverter slave phase-locked loop are as follows: simultaneously satisfies the voltage fundamental wave reactive component v of the alternating-current side busq＜2％·UedAnd a voltage fundamental active component vd＞95％·UedAnd maintaining at least one fundamental period (20ms), UedAnd outputting rated voltage amplitude for the inverter slave machine.
For example, when the inverter slave machine outputs a rated voltage of 220V, the AC side bus voltage fundamental wave reactive component Vq< 5V and voltage fundamental wave active component Vd＞210V。
Step 7.4: according to the detected output voltage and the detected inductance current value, the inverter slave machine is started in a current control mode, and inverts and outputs the voltage with the same amplitude and phase angle as the common bus to realize the parallel operation with the inverter host machine;
step 7.5: according to the frequency and the phase angle of the bus voltage at the alternating current side, the inverter slave computer calculates the frequency and the phase angle of the fundamental component of the output reference current and the frequency and the phase angle of each main subharmonic component of the reference current;
the phase angle of the AC side bus voltage detected in step 7.2 is θu′，
Figure BDA0002742577940000111
Where f is the frequency of the AC side voltage,
Figure BDA0002742577940000112
the initial phase angle of the bus voltage on the alternating current side is f, the frequency of the fundamental wave component of the reference current of the inverter slave machine is f, and the phase angle thetai′＝θu', reference currents each mainFrequency of the sub-harmonic component is h.f, phase angle
Figure BDA0002742577940000113
Figure BDA0002742577940000114
Step 7.6: the inverter slave machine judges whether current data of current fundamental waves and current major subharmonics from the inverter master machine are received from the CAN bus: if yes, go to step 7.7, if no, go to step 7.5;
step 7.7: in the current period, the inverter slave machine calculates the alpha beta component of the fundamental wave of the reference current and the alpha beta component of each major subharmonic in the two-phase static alpha beta coordinate system through Park inverse transformation, and then the alpha component of the fundamental wave of the reference current and the alpha component of each major subharmonic are superposed to obtain the total reference current i of the inverter slave machineL_ref；
The calculation formula of the fundamental wave alpha beta component of the reference current is as follows:
Figure BDA0002742577940000115
the calculation formula of each main subharmonic alpha beta component of the reference current is as follows:
Figure BDA0002742577940000116
total reference current i of inverter slaveL_refThe calculation formula of (2) is as follows:
iL_ref＝iL1α_ref+∑iLhα_ref
in the present embodiment, taking 3 rd, 5 th and 7 th major harmonics as examples, the total reference current is iL_ref＝iL1α_ref+iL3α_ref+iL5α_ref+iL7α_ref。
Step 7.8: the inverter slave operates in a current control mode, and is controlled by a current closed-loop PI regulator to enable the output inductance of the inverter slave to be electrifiedFlow tracking reference current iL_refTherefore, current sharing control of the fundamental component and each major subharmonic component of the output current of the inverter master machine and the slave machine is achieved.
The single-phase voltage phase-locking technology based on the second-order generalized integrator (SOGI) has high frequency and phase angle detection precision, and meanwhile, the current amplitude data from the inverter master machine has no delay and distortion problems, so the reference current fundamental wave and each subharmonic component amplitude and the phase angle of the inverter slave machine completely correspond to the output inductive current of the inverter master machine, and each inverter slave machine enables the output inductive current to track the reference current without dead difference through the conventional current closed-loop PI control, so that the current sharing of the output current fundamental wave and the harmonic wave of the master machine and each slave machine can be realized, and the current sharing is not influenced by the difference of the output impedance of the inverter and the line impedance.
Further, the current sharing control method provided by the embodiment is verified by adopting two single-phase full-bridge inverters with the same capacity of 8KVA in parallel, a resistor box is adopted for a linear load, and a single-phase diode rectifier bridge is adopted for a nonlinear load. Fig. 5 shows output voltage and current waveforms when the inverter master and the slave are provided with linear loads, and fig. 6 shows output voltage and current waveforms when the inverter master and the slave are provided with nonlinear loads. In the figure, the 1 st, 2 nd, 3 th and 4 th measuring channels respectively correspond to the host machine inductive current, the alternating-current side bus voltage, the slave machine output inductive current and the total load current, and it can be seen that when the output is connected to the linear load, the effective value of the inverter host machine output current is 36.9A, and the effective value of the inverter slave machine output current is 36.5A; when the output is connected with the nonlinear load, the effective value of the output current of the inverter host computer is 33A, and the effective value of the output current of the inverter slave computer is 32.8A, which shows that the current sharing control method provided by the invention has good current sharing effect no matter the load is a wiring load or the nonlinear load.
Although the present description is described in terms of embodiments, not every embodiment includes only a single embodiment, and such description is for clarity only, and those skilled in the art should be able to integrate the description as a whole, and the embodiments can be appropriately combined to form other embodiments as will be understood by those skilled in the art.
In the description of the present invention, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.
Therefore, the above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application; all changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims (9)

1. A master-slave parallel inverter output current sharing control method is characterized by comprising the following steps:
step 1: the inverter host samples and reads the output voltage and the inductive current of the inverter host in each control period through a digital signal processor;
step 2: according to the detected output voltage and the detected inductance current value, the inverter host is started in a voltage control mode, and voltage is established on an alternating-current side bus;
and step 3: according to the detected output voltage and inductance current value, the inverter host extracts a current fundamental component i under a two-phase static alpha beta coordinate system through a multi-double-generalized second-order integrator module in the current control periodL1αAnd iL1βThe major subharmonic component i of the currentLhαAnd iLhβH is the harmonic number;
and 4, step 4: according to frequency f and phase angle theta of fundamental component of output reference voltageiThe inverter host calculates the frequency and phase angle of the fundamental wave of the current output in the current control period and the frequency and phase angle of each main subharmonic component of the current;
and 5: in thatIn the current control period, the inverter host calculates the active component i of the current fundamental wave under the rotating dq coordinate system through the Park conversion moduleL1dAnd a reactive component iL1qAnd the active component i of each major sub-harmonic of the currentLhdAnd a reactive component iLhq；
Step 6: calculating to obtain the active component average value i of the current fundamental wave in n control periodsL1d_avgAverage value of reactive component iL1q_avgAnd the average value i of the active components of the major sub-harmonics of the currentLhd_avgAnd the average value of reactive components iLhq_avgAnd sharing to each inverter slave machine in real time through CAN bus, wherein
Figure FDA0002742577930000011
TcomIndicating the communication transmission time, T, of the current data of the inverter master to the inverter slavecRepresents a control period;
and 7: inverter slave machine synthesizes self reference current i based on current data shared by inverter master machineL_refAnd the output inductive current of the self-body tracks the reference current i through the control of a current closed loop PI regulatorL_ref。
2. The output current-sharing control method for the master-slave parallel inverter according to claim 1, wherein the step 7 comprises the following steps:
step 7.1: the inverter slave machine samples and reads the output voltage, the inductive current and the alternating-current side bus voltage of the inverter slave machine in each control period through a digital signal processor;
step 7.2: according to the detected AC side bus voltage, the inverter slave machine detects the amplitude, the frequency and the phase angle of the fundamental wave component of the AC side bus voltage through a phase-locked loop module;
step 7.3: the inverter slave machine judges whether the phase-locked loop detection is successful: if yes, the step 7.4 is carried out, and if not, the step 7.2 is carried out;
step 7.4: according to the detected output voltage and the detected inductance current value, the inverter slave machine is started in a current control mode, and inverts and outputs the voltage with the same amplitude and phase angle as the common bus to realize the parallel operation with the inverter host machine;
step 7.5: according to the frequency and the phase angle of the bus voltage at the alternating current side, the inverter slave computer calculates the frequency and the phase angle of the fundamental component of the output reference current and the frequency and the phase angle of each main subharmonic component of the reference current;
step 7.6: the inverter slave machine judges whether current data of current fundamental waves and current major subharmonics from the inverter master machine are received from the CAN bus: if yes, go to step 7.7, if no, go to step 7.5;
step 7.7: in the current period, the inverter slave machine calculates the alpha beta component of the fundamental wave of the reference current and the alpha beta component of each major subharmonic in the two-phase static alpha beta coordinate system through Park inverse transformation, and then the alpha component of the fundamental wave of the reference current and the alpha component of each major subharmonic are superposed to obtain the total reference current i of the inverter slave machineL_ref；
Step 7.8: the inverter slave machine is controlled by a current closed loop PI regulator, so that the output inductive current of the inverter slave machine tracks the reference current iL_ref。
3. The output current-sharing control method of the master-slave parallel inverter according to claim 2, characterized in that in step 7.2, the inverter slave unit adopts a phase-locked loop module, and the fundamental wave reactive component v of the bus voltage on the alternating current side is controlled by a PI regulator to enable the bus voltage on the alternating current side to have a fundamental wave reactive component vqIs 0.
4. The output current-sharing control method for the master-slave parallel inverter according to claim 3, wherein in step 7.3, the condition for determining the successful detection of the slave phase-locked loop of the inverter is as follows: simultaneously satisfies the voltage fundamental wave reactive component v of the alternating-current side busq<2％·UedAnd a voltage fundamental active component vd>95％·UedAnd maintaining at least one fundamental period, UedAnd outputting rated voltage amplitude for the inverter slave machine.
5. Root of herbaceous plantThe output current-sharing control method for the master-slave parallel inverter as claimed in claim 4, wherein in step 7.5, the phase angle of the bus voltage on the AC side is θu′，
Figure FDA0002742577930000021
Wherein the content of the first and second substances,
Figure FDA0002742577930000022
is the initial phase angle of the AC side bus voltage, f is the frequency of the AC side bus voltage and the fundamental wave component of the inverter slave machine reference current, and the phase angle theta of the fundamental wave component of the inverter slave machine reference currenti′＝θu', the frequency of each major subharmonic component of the reference current is h.f, the phase angle
Figure FDA0002742577930000023
6. The output current-sharing control method for the master-slave parallel inverter according to claim 5, wherein in step 7.7, the calculation formula of the fundamental wave α β component of the reference current is:
Figure FDA0002742577930000031
the calculation formula of each main subharmonic alpha beta component of the reference current is as follows:
Figure FDA0002742577930000032
total reference current i of inverter slaveL_refThe calculation formula of (2) is as follows:
iL_ref＝iL1α_ref+∑iLhα_ref。
7. the output current-sharing control method for master-slave parallel inverters according to claim 1, wherein in step 5, the output current-sharing control method is adoptedActive component i of the fundamental currentL1dAnd a reactive component iL1qThe calculation formula of (2) is as follows:
Figure FDA0002742577930000033
active component i of each major sub-harmonic of the currentLhdAnd a reactive component iLhqThe calculation formula of (2) is as follows:
Figure FDA0002742577930000034
wherein, thetahiThe phase angle of each major sub-harmonic component of the current,
Figure FDA0002742577930000035
the frequency of each major harmonic component of the current is h.f, f is the frequency of the fundamental component of the reference voltage and the output current, and the phase angle theta of the fundamental component of the output currenti＝θu，
Figure FDA0002742577930000036
Is the initial phase angle of the voltage.
8. The output current-sharing control method for the master-slave parallel inverter according to claim 1 or 7, wherein in step 6, the average value i of the active components of the major sub-harmonics of the current in n control periodsLhd_avgAnd the average value of reactive components iLhq_avgThe calculation formula of (2) is as follows:
Figure FDA0002742577930000037
when h is 1, the calculation formula is the active component average value i of the current fundamental wave in n control periodsL1d_avgAverage value of reactive component iL1q_avgThe calculation formula of (2).
9. The output current sharing control method for the master-slave parallel inverter according to claim 8, wherein in step 6, n is 5.
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