CN112164649A

CN112164649A - Etching method of semiconductor structure

Info

Publication number: CN112164649A
Application number: CN202011039819.0A
Authority: CN
Inventors: 侯潇; 何欢; 王秉国; 高勇强; 李寒骁
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2021-01-01

Abstract

A method for etching a semiconductor structure is disclosed. The method comprises the following steps: placing a semiconductor structure to be etched in a reactor; and performing a plurality of etch cycles on the semiconductor structure. Each of the etch cycles comprises: filling an etching gas into the reactor for a first duration; and stopping filling the etching gas, and filling the first purge gas into the reactor for a second time period to remove by-products generated in the reactor.

Description

Etching method of semiconductor structure

Technical Field

The present application relates to the field of semiconductor device manufacturing, and more particularly, to methods of etching semiconductor structures.

Background

In the manufacture of semiconductor devices, it is often necessary to utilize a sacrificial layer, such as an amorphous silicon sacrificial layer. These sacrificial layers are to be removed in a later process step. The removal of the sacrificial layer may be achieved by an etch reactor using a reaction between a reactive gas and the material of the sacrificial layer.

Currently, the wafer batch size (batch size) processed in etch reactors is typically 6-12 wafers, which limits the efficiency of wafer processing. Accordingly, there is a need in the art to increase the batch size for wafer processing, for example, to 50 or more wafers, such as 100 wafers, to increase the efficiency of wafer processing.

However, as wafer lot sizes increase, the amount of reactive gas required during etching also increases rapidly, which under prior art conditions can lead to an insufficient supply of reactive gas and possibly to a residue of reaction byproducts that is inconsistent between the wafer center and the wafer edge. For example, in the case where the reactive gas inlet is located above the wafer edge, there may be more residue in structural features such as deep holes at the wafer center than deep holes at the wafer edge.

On the other hand, as the lot size of wafers increases, byproducts generated during the etching process also increase rapidly, and particle residues of the byproducts may occur, which are easily attached to the surface of the wafer, thereby causing small micro-defects on the wafer.

Disclosure of Invention

In order to solve the foregoing problems, an aspect of the present invention provides a method for etching a semiconductor structure. The method comprises the following steps: placing a semiconductor structure to be etched in a reactor; and performing a plurality of etch cycles on the semiconductor structure. Each of the etch cycles comprises: filling an etching gas into the reactor for a first duration; and stopping filling the etching gas, and filling the first purge gas into the reactor for a second time period to remove by-products generated in the reactor.

In one or more embodiments of the present invention, the semiconductor structure includes a substrate, a trench formed on the substrate, and a layer to be etched covering at least an inner wall of the trench, and performing a plurality of etching cycles on the semiconductor structure includes: and executing a plurality of etching cycles on the layer to be etched.

In one or more embodiments, a dielectric layer is formed between the layer to be etched and the inner wall of the trench, the dielectric layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride, and the layer to be etched includes amorphous silicon and/or polysilicon.

In one or more embodiments, the layer to be etched comprises amorphous silicon and/or polysilicon, the etching gas comprises an etchant, and the etchant comprises HCl and Cl₂One or more of HF and F.

In one or more embodiments, during the charging of the etching gas into the reactor, the pressure in the reactor is raised to and maintained at a pressure in the range of 20 torr to 50 torr.

In one or more embodiments, the first purge gas comprises H₂、N₂One or more of Ar and He.

In one or more embodiments, the first period of time is in the range of 3 minutes to 5 minutes and the second period of time is in the range of 2 minutes to 4 minutes.

In one or more embodiments, the method may further comprise: after performing the plurality of etch cycles, performing a plurality of purge cycles on the reactor. Each purge cycle of the plurality of purge cycles comprises: charging a second purge gas into the reactor for a third period of time; and stopping the charging of the second purge gas into the reactor for a fourth period of time.

In one or more embodiments, the second purge gas comprises H₂、N₂One or more of Ar and He.

In one or more embodiments, each of the third and fourth time periods is in a range of 2 minutes to 4 minutes.

In one or more embodiments, the method may further comprise: gradually raising the temperature of the semiconductor structure from an initial temperature to a target temperature and maintaining the target temperature during etching prior to performing the plurality of etch cycles. Wherein during the gradual temperature increase, the semiconductor structure is subjected to an anneal and the temperature and pressure are maintained constant during the anneal.

These and other features and aspects of the present invention will become more apparent from the following detailed description, which proceeds with reference to the accompanying drawings.

Drawings

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings, where like reference numerals have been used, where possible, to designate like elements that are common to the figures. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments, wherein:

fig. 1 shows a schematic flow diagram of a method for etching a semiconductor structure according to one or more embodiments of the present application.

FIG. 2 shows a schematic timing diagram of a process for etching a semiconductor structure according to one or more embodiments of the present application.

Fig. 3 schematically shows a distribution of particles attached to the surface of the substrate after performing the etching process.

FIG. 4 schematically shows a top view of a high aspect ratio hole obtained by energy-filtered transmission electron microscopy (EFTEM).

It is contemplated that elements of one embodiment of the present invention may be beneficially utilized on other embodiments without further recitation.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but it will be apparent to one skilled in the art that the present invention may be practiced without some or all of these specific details and that the present invention is therefore not limited to the specific embodiments disclosed below. In other instances, well known processes or steps have not been described in detail so as not to unnecessarily obscure the present invention.

Further, it is to be understood that the various embodiments shown in the figures are illustrative and that the figures are not necessarily drawn to scale.

This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

In this document, unless defined otherwise, technical or scientific terms used in the claims and the specification should have the ordinary meaning as understood by those of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the description and claims of this application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The terms "a" or "an," and the like, do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item appearing before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalent, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, nor are they restricted to direct or indirect connections.

The method or process of the present invention may be used in CVD, PVD, ALD, and like applications. The terms "wafer" and "substrate" as used herein may be used interchangeably and may refer to a 300mm, 200mm, or other size substrate. In addition, the terms "about," "approximately," or "approximately" as used herein are intended to mean that the nominal value provided is precisely within a range of ± 5%. The term "near vacuum" as used herein is intended to mean a pressure in the reactor of less than about 0.25 torr with process gas flowing. The term "vacuum" as used herein is intended to mean a pressure in the reactor of less than about 0.04 torr without flow of process gases. The method or process of the present invention is described in more detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic flow diagram of a method 100 for etching a semiconductor structure according to one or more embodiments of the present application. Method 100 may include step 120 and step 140. In step 120, a semiconductor structure to be etched may be placed in a reactor. In step 140, a plurality of etch cycles may be performed on the semiconductor structure.

In some embodiments, the present invention can implement process 100 using a furnace tube as a reactor. In other embodiments, the reactor may be an etch chamber or other similar apparatus.

In an embodiment of the present invention, the semiconductor structure may include a substrate, a trench or other structural feature formed on the substrate, and a layer to be etched covering at least an inner wall of the trench or other structural feature. In some embodiments, trenches and the like on the semiconductor structure may have a high aspect ratio. In addition, a dielectric layer is arranged between the inner wall of the trench and the layer to be etched, and the dielectric layer can mainly comprise one or more of silicon oxide, silicon nitride, silicon oxynitride and the like. In an embodiment, the layer to be etched on the substrate may mainly comprise one or more of amorphous silicon, polysilicon, and the like.

Each of the plurality of etch cycles performed in step 140 may further include sub-steps 142 and 146. In sub-step 142, an etching gas may be charged into the reactor for a first period of time. In an embodiment, the etching gas may have an etch selectivity with respect to the dielectric layer and the layer to be etched. In sub-step 146, the charging of the etching gas into the reactor may be stopped and the first purge gas may be charged into the reactor for a second period of time. In embodiments of the present invention, step 140 may perform two, three, four, five, six, seven, eight, or more etch cycles. The multiple etch cycles may ensure complete removal of the layer to be etched. Alternatively, in a preferred embodiment, the etching may be continued for a period of time after the layer to be etched is completely removed, such as for about 3-5 minutes.

Further, during step 140, the temperature in the reactor may be maintained between about 680 degrees celsius and about 750 degrees celsius, such as at about 720 degrees celsius.

During substep 142, the charged etching gas may contain at least an etchant. In one or more embodiments, the etchant in the etching gas can be a halogen group gas, including, for example, HCl, Cl₂、HF、F、BCl₃、CCl₄、ClF₃And the like. In one or more embodiments, the etching gas may be charged into the reactor for a first period of time in a range of about 3 minutes to about 5 minutes. Preferably, the first time period may be about 4 minutes. During etching, the etchant may be charged into the reactor, typically at a flow rate in the range of about 1L/min to about 10L/min, for example, at a flow rate of about 8L/min.

In a preferred embodiment of the present invention, HCl may be used as an etchant. HCl has a high etching selectivity ratio for etching an amorphous silicon layer to be etched and a silicon oxide layer under the amorphous silicon layer, and thus it can be ensured that the underlying silicon oxide layer is not damaged even by a continued etching process after the amorphous silicon layer is completely removed. In addition, HCl also has a high etching selectivity ratio for etching of an amorphous silicon layer and a single crystal silicon layer, so that loss of Selective Epitaxial Growth (SEG) mainly formed of single crystal silicon during etching is small.

During substep 142, the pressure in the reactor may be raised to and maintained at a relatively high pressure, for example, a pressure greater than 10 torr. This is higher than the constant pressure in the range of 1-10 torr (e.g., about 8 torr) used in the prior art, thereby increasing the amount of etching gas charged into the reactor, which in turn may alleviate the problem of insufficient supply of etching gas due to the rise in wafer lot size, helping to improve the uniformity of the etch by-product residues in the wafer center and the wafer edge structural features. In one or more embodiments, the pressure in the reactor can be raised to and maintained at a pressure in the range of about 20 torr to about 50 torr, and preferably, can be raised to and maintained at a pressure of about 30 torr.

In practice, when the pressure in the reactor is low (e.g., about 1-10 torr), the etching gas can more easily reach the bottom of the trench or other structural feature, thereby promoting sufficient reaction of the etching gas with the layer to be etched at the bottom. Therefore, etching of layers on such semiconductor structures is typically performed at low pressures.

The present application employs high pressures, such as pressures in the range of about 20-50 torr. The amount of etching gas in the reactor under high pressure is greatly increased, so that more etching gas can be provided for the bottoms of the structural features such as the grooves. Therefore, although the amount of etching gas in the same volume of gas which finally reaches the bottom is relatively reduced due to the high pressure, the total supply amount of etching gas is large enough to ensure that the layer to be etched on the inner wall of the structural feature such as the trench is completely removed.

During substep 146, the charged first purge gas may include H₂、N₂And an inert gas (such as Ar, He, etc.). The first purge gas may carry etch by-products generated during the etch of substep 142 and cause the by-products to exit the reactor with the gas stream. In one or more embodiments, the first purge gas may be charged to the reactor for a second period of time in the range of about 2 minutes to about 4 minutes, for example about 3 minutes. During this purging, the first purge gas may be charged into the reactor, typically at a flow rate in the range of about 2L/min (liters per minute) to about 10L/min, preferably at a flow rate of about 8L/min.

In a preferred embodiment of the invention, H may be used₂As the first purge gas. H₂The cost of (2) is low. And, H₂And also has strong reducibility, and can reduce the etching by-products (such as silicon chloride) of macromolecules into small molecules, which is beneficial to discharge of the etching by-products. Further, H is used at a high temperature of about 680 to about 750 degrees celsius in the reactor₂It is also possible to avoid random migration of amorphous silicon atoms and thereby prevent agglomeration of etch by-products, such as polysilicon. In practice, when etch by-products agglomerate into large objects (such as poly clusters), it is possible to block such holesClass structural features, resulting in wafer defects.

Further, during substep 146, the reactor may be under near vacuum, i.e., having a pressure less than about 0.25 torr.

As described above, the method for etching a semiconductor structure of the present invention divides the etching process into a plurality of etching cycles, each of which includes an etching sub-step and a purging sub-step. Compared with the single long etching step (without purging substep) adopted by the prior art, the etching method of the semiconductor structure can discharge the etching by-products in time after etching a part of the layer to be etched, thereby preventing the by-product particles from attaching to the surface of the wafer to cause the defect of the wafer.

One example of a process timing sequence of the method of etching a semiconductor structure of the present invention is described below with reference to fig. 2. In the following description, the dielectric layer is silicon oxide, the layer to be etched is amorphous silicon, the etchant is HCl, and the first purge gas is H₂For example. Thus, the process of etching the amorphous silicon layer using HCl can be expressed by the following equation:

at the beginning of the process, the semiconductor structure is provided into a reactor ready. During this process, the temperature in the reactor may be maintained at an initial temperature (e.g., about 550 degrees celsius), and the pressure may be maintained, for example, equal to standard atmospheric pressure.

Thereafter, the reactor may be subjected to a ramp-up operation to gradually raise the temperature in the reactor from an initial temperature (e.g., about 550 degrees celsius) to a desired target temperature (e.g., a temperature in a range of about 680 degrees celsius to about 750 degrees celsius, such as about 720 degrees celsius) during the etching process, such that the temperature of the semiconductor structure in the reactor may be gradually raised to the desired target temperature. During the warm-up operation, the pressure in the reactor may be reduced to and maintained at about 70 torr. This temperature increase operation allows the charging reaction to be carried out by means of the heating element of the reactorGas in the vessel (e.g. H)₂) Is achieved by a temperature increase of. In one or more embodiments, H₂May be charged to the reactor at a flow rate in the range of about 2L/min to about 10L/min, preferably about 8L/min. Further, the warming operation may last for about 25 minutes to about 40 minutes, such as about 30 minutes.

In some embodiments, an annealing operation may be interposed during the temperature ramp operation to subject the semiconductor structure to annealing. For example, the annealing operation may be performed at about 20 minutes after the temperature increasing operation is started. At this point, the temperature in the reactor may have been increased to, for example, about 650 degrees celsius, and the pressure in the reactor may have been substantially decreased to and maintained at a pressure in the range of about 1 torr to about 10 torr. The temperature and pressure may be maintained constant during the annealing operation. Such an annealing operation may also cause a gas (e.g., H) charged into the reactor to pass through the heating element of the reactor₂) Is achieved with the temperature of (a) being kept constant. In one or more embodiments, H₂May be charged to the reactor at a flow rate in the range of about 2L/min to about 10L/min, preferably about 8L/min. Further, the annealing operation may be performed for about 70 minutes to about 110 minutes, and preferably, for about 90 minutes. After the annealing operation is finished, the previously unfinished temperature raising operation is continued until the desired temperature for the etching process is reached in the reactor. The intervening annealing operation during the temperature ramp operation may help prevent agglomeration of etch byproducts (e.g., polysilicon).

After the ramping operation is complete, the elevated temperature in the reactor may be maintained, thereby maintaining the semiconductor structure disposed in the reactor at the desired target temperature. Also, a plurality of etch cycles may be performed on the semiconductor structure in the reactor, wherein each etch cycle may include an etch sub-step and a purge sub-step. In the embodiment shown in fig. 2, a total of three etch cycles are performed. During the etch substep of each etch cycle, the pressure in the reactor may be raised to and maintained at about 30 torr, while HCl may be charged to the reactor at a flow rate of about 8L/min for about 4 minutes. Thus, in carrying out threeIn the case of a single etch cycle, the total etch time for the semiconductor structure may be up to about 12 minutes. Further, in the purge substep of each etch cycle, the pressure in the reactor may be reduced to approximately vacuum (i.e., below about 0.25 torr), while H may be delivered at a flow rate of about 8L/min₂The reactor was charged for about 3 minutes. Thus, where three etch cycles are performed, the total time for purging may be up to about 9 minutes.

After completion of the plurality of etch cycles, the elevated temperature in the reactor may continue to be maintained. Also, a purging operation may be further performed on the reactor, the purging operation including a plurality of purging cycles, each purging cycle may include a purging sub-step and a non-purging sub-step to enhance a purging effect. In the purge substep, a second purge gas may be charged to the reactor for a third length of time. In the non-purge substep, the charging of the second purge gas into the reactor may be stopped for a fourth period of time. That is, the second purge gas may be pulsed into the reactor during the purge operation.

The second purge gas can disturb the remaining etch byproducts in the reactor such that the etch byproducts can be carried with the second purge gas and exit the reactor with the second purge gas. In the case where the second purge gas is continuously supplied, a portion of the second purge gas may be stagnant in the reactor such that the etch by-products carried by it cannot be discharged out of the reactor. To enhance the purging effect and to facilitate the removal of the etch by-products, the second purge gas may be pulsed. Carrying the etching by-product with the second purge gas through the purge sub-step; then, through the non-purging substep, the supply of the second purge gas is stopped, such that the reactor is evacuated to discharge substantially all of the etch by-products carried by the second purge gas in the reactor out of the reactor.

In embodiments of the present invention, two, three, four, five, six, seven, eight, or more purge cycles may be performed. In one or more embodiments, the second purge gas may also include H, similar to the first purge gas₂、N₂And one or more of Ar, He and the like. Further, the second purge gas may have the same composition as the first purge gas, or may have a different composition from the first purge gas. In a preferred embodiment, the second purge gas may also be H with strong reducibility₂。

In one or more embodiments, each of the third and fourth time periods may be a time period in the range of about 2 minutes to about 4 minutes, and preferably may be about 3 minutes. During this purging, the second purge gas may be charged to the reactor, typically at a flow rate in the range of about 2L/min to about 10L/min, preferably at a flow rate of about 8L/min.

In the embodiment shown in FIG. 2, a total of three purge cycles are performed. In the purge substep of each purge cycle, H may be fed at a flow rate of about 8L/min₂The reactor is charged for about 3 minutes while the reactor may be under a near vacuum (i.e., pressure less than about 0.25 torr). In the non-purge substep of each purge cycle, H is stopped₂For about 3 minutes while the pressure in the reactor may be reduced to below about 0.04 torr, that is, the reactor is under vacuum.

The present invention performs an independent purge operation after the etching operation, so that it is possible to further prevent the residue of the etching by-products, thereby preventing the generation of defects on the wafer.

After the purging operation is completed, the reactor may be subjected to a cool-down operation that lowers the temperature in the reactor (and thus the temperature of the semiconductor structure disposed in the reactor) back to the initial temperature, for example, about 550 degrees celsius. During the cool down operation, the pressure in the reactor may be raised to and maintained at about 70 torr. Such a temperature reduction operation may also cause the gas (e.g., H) charged into the reactor to pass through the heating element of the reactor₂、N₂One or more of Ar, He and the like, preferably H₂) Is achieved by a temperature drop of (1). In one or more embodiments, the gas may be charged to the reactor at a flow rate in the range of about 2L/min to about 10L/min, preferably about 8L/minIn a reactor. Further, the cooling operation may last for about 25 minutes to about 40 minutes, such as about 30 minutes. In the use of H₂In embodiments where a cool down operation is performed, H is used during the cool down operation₂It is still possible to reduce etching residues that may be present in the reactor.

After the temperature reduction operation is finished, the pressure in the reactor can be increased to the original standard atmospheric pressure by performing pressure return operation on the reactor. During this process, the temperature in the reactor may be maintained constant at the returned initial temperature (e.g., about 550 degrees celsius).

The semiconductor structure may then be unloaded from the reactor.

Referring now to fig. 3 and 4, the results of the etch process after the wafer lot size is raised will be described.

As shown in fig. 3, (a) and (b) represent etching process results obtained by the method of etching a semiconductor structure according to the related art, and (c) represents etching process results obtained by the method of etching a semiconductor structure according to the present invention. The shading in fig. 3 indicates particle defects distributed on the substrate surface. As can be seen from fig. 3, the particles are less at three points on the wafer (a) except for the triangular points, and the particles are very much attached to other parts; the situation on wafer (b) is substantially opposite to wafer (a), with more particles at the three points of the triangular position and at the edge. In contrast, the wafer (c) treated by the method of the present invention had very few particle defects.

Fig. 4 (a) shows the result of an etching process of one deep hole according to a method of etching a semiconductor structure of the related art, in which white spots indicate the residue of etching by-products existing in the deep hole. Fig. 4 (b) shows the result of the etching process for a deep hole-like etching process according to the method of etching a semiconductor structure of the present invention, and it can be seen that there is substantially no etching by-product remaining therein.

It should be noted that in the foregoing description of embodiments of the present application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, embodiments may have fewer than all of the features of a single embodiment disclosed above.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, changes and modifications to the above embodiments within the spirit of the invention are intended to fall within the scope of the claims of the present application.

Claims

1. A method for etching a semiconductor structure, the method comprising:

placing a semiconductor structure to be etched in a reactor; and

performing a plurality of etch cycles on the semiconductor structure, each of the etch cycles comprising:

filling an etching gas into the reactor for a first duration; and

and stopping filling the etching gas, and filling the first purging gas into the reactor for a second time to remove by-products generated in the reactor.

2. The method of claim 1, wherein the semiconductor structure comprises a substrate, a trench formed on the substrate, and a layer to be etched overlying at least an inner wall of the trench, and wherein performing a plurality of etch cycles on the semiconductor structure comprises: and executing a plurality of etching cycles on the layer to be etched.

3. The method of claim 2, wherein a dielectric layer is formed between the layer to be etched and the inner wall of the trench, the dielectric layer comprises one or more of silicon oxide, silicon nitride and silicon oxynitride, and the layer to be etched comprises amorphous silicon and/or polysilicon.

4. The method according to claim 1, wherein the layer to be etched comprises amorphous silicon and/or polysilicon, the etching gas comprises an etchant comprising HCl, Cl₂One or more of HF and F.

5. The method of claim 1, wherein during charging the reactor with etching gas, the pressure in the reactor is raised to and maintained at a pressure in the range of 20 torr to 50 torr.

6. The method of claim 1, wherein the first purge gas comprises H₂、N₂One or more of Ar and He.

7. The method of claim 1, wherein the first time period is in a range of 3 minutes to 5 minutes and the second time period is in a range of 2 minutes to 4 minutes.

8. The method of claim 1, further comprising:

after performing the plurality of etch cycles, performing a plurality of purge cycles on the reactor, each purge cycle comprising:

charging a second purge gas into the reactor for a third period of time; and

stopping the charging of the second purge gas into the reactor for a fourth period of time.

9. The method of claim 8, wherein the second purge gas comprises H₂、N₂One or more of Ar and He.

10. The method of claim 8, wherein each of the third and fourth time periods is in a range of 2 minutes to 4 minutes.

11. The method of claim 1, further comprising: gradually increasing the temperature of the semiconductor structure from an initial temperature to a target temperature and maintaining the target temperature during etching prior to performing the plurality of etch cycles,

wherein during the gradual temperature increase, the semiconductor structure is subjected to an anneal and the temperature and pressure are maintained constant during the anneal.