CN112151485A - Packaging structure of semiconductor device and packaging method thereof - Google Patents
Packaging structure of semiconductor device and packaging method thereof Download PDFInfo
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- CN112151485A CN112151485A CN202011024752.3A CN202011024752A CN112151485A CN 112151485 A CN112151485 A CN 112151485A CN 202011024752 A CN202011024752 A CN 202011024752A CN 112151485 A CN112151485 A CN 112151485A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a packaging structure of a semiconductor device and a packaging method thereof, wherein the packaging structure comprises: a semiconductor substrate; the semiconductor device is formed on the upper surface of the semiconductor substrate and comprises a chip area for realizing the function of the semiconductor device and an off-chip area surrounding the chip area; a top metal layer located on the upper portion of the chip region; a first passivation layer on the upper portion of the semiconductor device; a rewiring layer covering the upper surface of the first passivation layer; and a plurality of openings penetrating through the first passivation layer are correspondingly arranged in the upper part of each top layer metal, and the plurality of openings are used for realizing the electrical connection between the top layer metal and the rewiring layer. The invention can realize the uniformity of current flowing in the semiconductor device, thereby improving the current capability of the chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a packaging structure and a packaging method of a semiconductor device.
Background
In recent years, with the development of large-current and high-power chips, RDL (Redistribution Layer) wiring using copper as a material has been widely used. In the conventional 0.18um and 0.35um processes, the metal at the back end of the chip is AlCu (copper aluminum alloy), and the size of the opening on the passivation layer is relatively large (greater than or equal to 60 um).
With the improvement of chip current, the conventional process method cannot meet the requirement of chip design on resistance, and when back-end packaging (such as wire bonding or flip chip) is performed on a large passivation layer opening, current is mainly concentrated near the large opening, so that current unevenness is easily caused, and even local burning of the chip is caused due to too large local current.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problem, the invention provides a packaging structure of a semiconductor device and a packaging method thereof, which can realize the uniformity of current flowing in the semiconductor device and further improve the current capability of a chip.
In one aspect, a package structure of a semiconductor device according to the present invention includes: a semiconductor substrate; the semiconductor device is formed on the upper surface of the semiconductor substrate and comprises a chip area for realizing the function of the semiconductor device and an off-chip area surrounding the chip area; a top metal layer located on the upper portion of the chip region; a first passivation layer on the upper portion of the semiconductor device; the rewiring layer is positioned on the upper surface of the first passivation layer; a plurality of first openings penetrating through the first passivation layer are correspondingly arranged in the upper part of each top layer metal, and the plurality of first openings are used for realizing the electrical connection between the top layer metal and the rewiring layer.
Optionally, the plurality of first openings on the top of each top layer metal are spaced from each other, a spacing distance between each of the plurality of first openings is smaller than or equal to a first preset value, and a spacing distance between a peripheral opening of the plurality of first openings and a terminal position of the top layer metal is smaller than or equal to a second preset value.
Optionally, the package structure further includes: a second passivation layer between the semiconductor device upper surface and the first passivation layer; and the second openings are correspondingly arranged in the lower area of the top layer metal and penetrate through the second passivation layer.
Optionally, the plurality of second openings in the lower region of the top layer metal are spaced apart from each other, a spacing distance between each of the plurality of second openings is smaller than or equal to a first preset value, and a spacing distance between a peripheral opening of the plurality of second openings and a terminal position of the top layer metal is smaller than or equal to a second preset value.
Optionally, the sizes of the first and second plurality of apertures are less than or equal to the first threshold.
Optionally, the cross-section of the first and second plurality of apertures is circular or square in shape.
Optionally, the cavity of each first opening and each second opening is filled with a copper material.
Optionally, an upper surface of the first passivation layer is flat.
Optionally, the first passivation layer and the second passivation layer are formed from an oxide or an oxynitride.
Optionally, the semiconductor substrate comprises: the epitaxial layer is formed on the substrate.
Optionally, the material of the redistribution layer and the top metal is copper.
Optionally, the package structure further includes: and the bonding pad or the solder ball and/or the array bump are arranged on the rewiring layer.
Optionally, the package structure further includes: a protective layer covering the rewiring layer; and the bonding pad or the solder ball and/or the array bump are arranged on the protective layer.
In another aspect, a method for packaging a semiconductor device according to the present invention includes: forming a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and an epitaxial layer formed on the substrate; forming a semiconductor device on the upper surface of the semiconductor substrate, wherein the semiconductor device comprises a chip area for realizing the function of the semiconductor device and an off-chip area surrounding the chip area; forming a top metal layer on the upper surface of the chip region; forming a first passivation layer covering the upper surface of the semiconductor device; forming a plurality of first openings penetrating the first passivation layer on the upper portion of each top layer metal; and forming a rewiring layer which covers the upper surface of the first passivation layer and is filled with the first openings.
Optionally, a size of each of the plurality of first apertures is less than or equal to a first threshold.
Optionally, the cross-section of the first plurality of apertures is circular in shape, the diameter of each of the first plurality of apertures being less than or equal to the first threshold; or the cross section of the first openings is square, and the side length of each first opening in the first openings is smaller than or equal to the first threshold value.
Optionally, the plurality of first openings on the top of each top layer metal are spaced from each other, a spacing distance between each of the plurality of first openings is smaller than or equal to a first preset value, and a spacing distance between a peripheral opening of the plurality of first openings and a terminal position of the top layer metal is smaller than or equal to a second preset value.
Optionally, before forming the plurality of first openings penetrating the first passivation layer, the method further includes: and carrying out chemical mechanical polishing on the first passivation layer.
Optionally, after forming a redistribution layer covering the upper surface of the first passivation layer and filling the plurality of first openings, the method further includes: and arranging a bonding pad or a solder ball and/or an array bump on the rewiring layer.
Optionally, after forming a redistribution layer covering the upper surface of the first passivation layer and filling the plurality of first openings, the method further includes: and forming a protective layer covering the rewiring layer, and arranging a bonding pad or a welding ball and/or an array bump on the protective layer.
In still another aspect, a method for packaging a semiconductor device according to the present invention includes: forming a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and an epitaxial layer formed on the substrate; forming a semiconductor device on the upper surface of the semiconductor substrate, wherein the semiconductor device comprises a chip area for realizing the function of the semiconductor device and an off-chip area surrounding the chip area; forming a second passivation layer on the upper surface of the semiconductor device; forming a plurality of second openings on the upper portion of the chip region and penetrating through the second passivation layer; forming a top metal layer on the upper surface of the second passivation layer corresponding to the chip region; forming a first passivation layer covering the upper surface of the second passivation layer; forming a plurality of first openings penetrating the first passivation layer on the upper portion of each top layer metal; and forming a rewiring layer which covers the upper surface of the first passivation layer and is filled with the first openings, wherein the size specifications of the second openings are consistent with the size specifications of the first openings.
The invention has the beneficial effects that: the invention discloses a packaging structure and a packaging method of a semiconductor device.
By setting the sizes of the plurality of openings and the spacing distance between each opening, the opening arrays can be arranged as many as possible according to a specific layout in the passivation layer of the chip region corresponding to the semiconductor device to realize interconnection between the metal layers, and the uniformity of current flowing in the semiconductor device is further improved.
The copper material is adopted to manufacture the top metal layer and the rewiring layer, so that the metal resistance of the semiconductor device is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 illustrates a schematic cross-sectional view of a package structure of a semiconductor device provided according to an embodiment of the present invention;
fig. 2a to 2g show schematic cross-sectional views of stages of a method of packaging a semiconductor device according to an embodiment of the invention;
fig. 3 is a schematic cross-sectional view illustrating a package structure of a semiconductor device according to another embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
Unless otherwise specified below, various layers or regions of a semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge. The gate conductor and the electrode layer may beFormed of various materials that are electrically conductive, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other electrically conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" refers to extending in a direction substantially perpendicular to the depth direction of the trench.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 is a schematic cross-sectional view illustrating a package structure of a semiconductor device according to an embodiment of the present invention.
As shown in fig. 1, in the present embodiment, the package structure of the semiconductor device includes: the semiconductor device comprises a semiconductor substrate, semiconductor devices formed on the upper surface of the semiconductor substrate, top metal 13 located on the upper portions of the semiconductor devices, a passivation layer 14 located on the upper portions of the semiconductor devices, a plurality of openings 15 arranged on the upper portions of the top metal 13 and penetrating through the passivation layer 14, and a rewiring layer 16 located on the upper surface of the passivation layer 14 and filling cavities of the openings 15.
The semiconductor substrate includes a substrate 10 (e.g., an N + silicon wafer: an N-type heavily doped silicon wafer) and an epitaxial layer 11 (e.g., an N-epitaxial wafer: an N-type lightly doped silicon epitaxial layer formed on the substrate 10 by epitaxial growth) formed on an upper surface of the substrate 10. In this embodiment, a semiconductor device is formed on the upper surface of the epitaxial layer 11. Of course, depending on the semiconductor device, the semiconductor substrate is not limited to include the substrate 10 and the epitaxial layer 11, for example, a schottky diode chip package commonly used at present, whose substrate face is also deposited with a device cathode metal as an electrical connection.
The semiconductor device includes a chip region 121 that realizes a function of the semiconductor device, and an off-chip region 122 surrounding the chip region 121. In this embodiment, the top metal 13 covers the upper surface of the chip region 121 in the semiconductor device. When the semiconductor device includes two or more chip regions 121, the adjacent two chip regions 121 are divided by an off-chip region 122, and a chip on the semiconductor substrate can be cut by the off-chip region 121.
In this embodiment, the top metal 13 covers the upper surface of each chip region 121 in the semiconductor device, and the top metal 13 is made of a copper material. The metal resistance of a semiconductor device, such as a power transistor, may be reduced due to the small resistivity of copper (e.g., less than the resistivity of aluminum).
Further, a passivation layer 14 covers the upper surface of the off-chip region 122 of the semiconductor device and the outer surface of the top metal 13. The upper surface of the passivation layer 14 is flat, and the material forming the passivation layer 14 may be, for example, an oxide such as silicon dioxide or tetraethylorthosilicate, or an oxynitride such as silicon oxynitride.
A plurality of openings 15 are formed in the passivation layer 14 at positions covering the upper surface of each top metal 13, and the plurality of openings 15 are used for electrically connecting the top metal 13 and the redistribution layer 16. And the size of each of the plurality of openings 15 is smaller than or equal to a first threshold (e.g., 2.5um), further, the plurality of openings 15 on the top of each top metal 13 are spaced apart from each other, and the spacing distance between each of the plurality of openings 15 is smaller than or equal to a first predetermined value, and the spacing distance between the peripheral openings of the plurality of openings 15 and the terminal position of the top metal 13 (i.e., the boundary between the chip region of the semiconductor device and the region 122 outside the chip 121) is smaller than or equal to a second predetermined value. Therefore, the opening arrays can be arranged in the upper surface area of each top metal 13 as much as possible according to the specific layout to realize the interconnection between the metal layers, so that the current can vertically go downwards from the upper layer to the lower layer as uniformly as possible, the resistance in the horizontal direction is reduced, and the uniformity of the current flowing in the semiconductor device is further improved. The first threshold, the first preset value and the second preset value may be set according to specific process conditions, which is not limited in the present invention, as long as the first preset value and the second preset value are set as small as possible under the permission of the existing process conditions.
Optionally, the plurality of apertures 15 are circular apertures (i.e., the plurality of apertures 15 are circular in cross-sectional shape), and the diameter of each of the plurality of apertures 15 is less than or equal to the first threshold; or the plurality of openings 15 are square openings (i.e., the plurality of openings 15 are square in cross-section), each of the plurality of openings 15 having a side length less than or equal to the first threshold. It will be appreciated that the cross-sectional shape of the plurality of apertures 15 may be any other shape that may be achieved by any conventional process.
Further, the cavity of each of the plurality of openings 15 is filled with a copper material to further improve the current capability of the semiconductor device.
In one embodiment of the present disclosure, a pad or solder ball and/or an array bump is further disposed on the corresponding position of the redistribution layer 16. In another embodiment of the present disclosure, the redistribution layer 16 is further covered with a protective layer for preventing moisture and the like from corroding chips, wires and the like, and pads or solder balls and/or array bumps are disposed on the protective layer. The rewiring layer 16 is a metallization pattern deposited on the passivation layer 14 by using a copper material, and thus the pins of the chip can be rearranged so as to be arranged in a new region with looser pitch occupation.
The following describes a package structure of a semiconductor device with a power transistor as a semiconductor device with reference to fig. 3. Fig. 3 is a schematic cross-sectional view illustrating a package structure of a semiconductor device according to another embodiment of the present invention.
As shown in fig. 3, in the present embodiment, the package structure of the semiconductor device (power device) includes: a substrate 20, an epitaxial layer 21 formed on an upper surface of the substrate 20, a power device (including a well region 221, two implant regions 223 in the well region, and a field oxide region 224 on an upper surface of the well region 221) and an off-chip region 222 formed on an upper surface of the epitaxial layer 21, a second passivation layer 23 on the power device and the off-chip region 222, a plurality of second openings 24 on upper portions of the two implant regions 223 and penetrating through the second passivation layer 23, a top metal 25 on upper portions of the plurality of second openings 24 and connected to the well region 223 of the power device through the plurality of second openings 24, a first passivation layer 26 on upper portions of the second passivation layer 23 and covering an outer surface of the top metal 25, a plurality of first openings 27 disposed on upper portions of each top metal 25 and penetrating through the first passivation layer 26, a redistribution layer 28 covering an upper surface of the first passivation layer 26 and filling cavities of the plurality of first openings 27, and pads at corresponding locations on the upper surface of redistribution layer 28. The connection between the power tube device and the external bonding pad is realized by arranging the plurality of second openings 24 and the plurality of first openings 27 as many as possible, so that the uniformity of current flowing of the power tube device is well realized, the performance of the power tube device is improved, and the local burning of a chip caused by the large-size openings can be avoided.
Further, in the present embodiment, the size of each of the first openings 27 and the second openings 24 is consistent with the size of the openings 15 in the embodiment shown in fig. 1, and includes that the size of each of the first openings 27 and the second openings 24 is smaller than or equal to a first threshold (e.g., 2.5 um); the cross-sectional shape of the first plurality of openings 27 and the second plurality of openings 24 is circular or square; the plurality of first openings 27 are arranged at intervals, the interval distance between every two second openings in the plurality of first openings 27 is smaller than or equal to a first preset value, and the interval distance between the peripheral openings in the plurality of first openings 27 and the terminal position of the top layer metal 25 is smaller than or equal to a second preset value; and the plurality of second openings 24 are spaced from each other, and the spacing distance between each of the plurality of second openings 24 is less than or equal to a first preset value, and the spacing distance between the peripheral openings of the plurality of second openings 24 and the terminal position of the top metal 25 is less than or equal to a second preset value, etc. And correspondingly, in order to better realize the current flow between the top layer and the metal 25 and the corresponding chip region of the power transistor device through the plurality of first openings 27 and the plurality of second openings 24, copper materials are filled in the plurality of first openings 27 and the plurality of second openings 24.
Further, the first passivation layer and the second passivation layer may be formed of the same material, and may be an oxide such as silicon dioxide or tetraethylorthosilicate, or an oxynitride such as silicon oxynitride.
Further, in the package structure shown in fig. 3, pads or solder balls and/or array bumps are further disposed at corresponding positions of the redistribution layer 16. Or the rewiring layer 16 is covered with a protective layer for preventing the erosion of water vapor and the like to the structures such as chips, wires and the like, and pads or solder balls and/or array bumps are arranged on the protective layer. The rewiring layer 16 is a metallization pattern deposited on the passivation layer 14 by using a copper material, and thus the pins of the chip can be rearranged so as to be arranged in a new region with looser pitch occupation.
It should be noted that the above package structure is only an exemplary embodiment, wherein the number of the passivation layer and the top metal layer can be adjusted according to specific situations, and it should not be taken as a limitation of the present invention as long as the conductive path (the opening penetrating through the passivation layer) connecting the multiple metal layers is configured as a structure with as many openings as possible.
The package structure of the semiconductor device shown in fig. 1 is fabricated by the process steps of fig. 2 a-2 g to further improve the uniformity of the current flow of the semiconductor device, and the following description of the manufacturing method is made.
Fig. 2a to 2g are schematic cross-sectional views illustrating stages of a packaging method of a semiconductor device according to an embodiment of the present invention, and a manufacturing process of a packaging structure of a semiconductor device according to an embodiment of the present application is described below with reference to fig. 2a to 2 g.
As shown in fig. 2a and 2b, a semiconductor substrate is first formed, which includes a substrate 10 and an epitaxial layer 11 formed over the substrate 10. As shown in fig. 2a, a single crystal silicon wafer is prepared by any conventional preparation method, and the substrate 10 is, for example, an N-type heavily doped silicon substrate. As shown in fig. 2b, a small amount of ions are implanted into the substrate 10, and the well is pushed down at a high temperature to form a lightly doped region, i.e., an epitaxial layer 11. Epitaxial layer 11 is lightly doped relative to substrate 10 and has the same ground-down type as the substrate, e.g., epitaxial layer 11 is a lightly N-type doped silicon epitaxial layer. This step is accomplished using conventional techniques.
As shown in fig. 2c, a semiconductor device is formed on the upper surface of the semiconductor substrate, and the semiconductor device includes a chip region 121 that performs a function of the semiconductor device, and an off-chip region 122 surrounding the chip region 121. The semiconductor device is formed using conventional processes. Such as by thermal oxidation or chemical vapor deposition of silicon dioxide as the insulating dielectric layer. Then, the chip region 121 is selectively exposed as a trench region with a MOS function by photolithography and etching, for example, by using a photoresist as a mask, an oxide layer (insulating dielectric layer) not protected by the photoresist is selectively removed by wet etching, and after a region corresponding to a pattern is exposed, the photoresist is removed, thereby forming a chip region 121 and an off-chip region 122. Semiconductor device structures are then formed in chip region 121 by conventional processes such as well implant, deposition of polysilicon, N +/P + implant, and the like.
As shown in fig. 2d, a top layer metal 13 is formed on the upper surface of the chip region 121. The top metal 13 is formed using conventional processes. For example, an anode metal (e.g., copper) is deposited on the top of the entire structure by thermal evaporation, metal sputtering, etc., and then the top metal on the top of the off-chip region 122 is removed by photolithography to define a pattern, i.e., the terminal structure of the top metal 13 is formed on the top surface of the chip region 121 by wet etching.
As shown in fig. 2e, a passivation layer 14 is formed covering the upper surface of the semiconductor device. The passivation layer 14 is formed using conventional processes. For example, using a low pressure chemical vapor deposition method to plasma-enhance chemical vapor deposition method to deposit oxides such as silicon dioxide, ethyl orthosilicate, or oxynitrides such as silicon oxynitride on the upper surface of the semiconductor device and the top metal 13, so as to form a passivation layer 14 covering the upper surface of the semiconductor device and the top metal 13. Or depositing metal materials such as titanium or tantalum or metal nitrides such as titanium nitride or tantalum nitride on the upper surfaces of the semiconductor device and the top metal 13 by adopting a chemical vapor deposition process or a sputtering deposition process to form an etching barrier layer covering the upper surfaces of the semiconductor device and the top metal 13; then, depositing oxides such as silicon dioxide, ethyl orthosilicate and the like or nitrogen oxides such as silicon oxynitride and the like on the surface of the etching barrier layer by adopting a low-pressure chemical vapor deposition method and a plasma-enhanced chemical vapor deposition method so as to form a passivation layer 14 covering the surface of the etching barrier layer.
Further, after forming the passivation layer 14, a Chemical Mechanical Polishing (CMP) process is performed on the passivation layer 14 to make the passivation layer have a relatively flat surface.
As shown in fig. 2f, a plurality of openings 15 are formed through the passivation layer 14 in the upper portion of each top metal layer 13. The plurality of openings 15 are formed using conventional processes. The passivation layer 14 is etched, for example, by photolithography to size, to selectively expose a desired plurality of top metal portions, forming a plurality of openings 15 through the passivation layer 14.
Further, the size of each of the plurality of openings 15 is smaller than or equal to a first threshold (e.g., 2.5um), further, the plurality of openings 15 on the top of each top metal 13 are spaced apart from each other, the spacing distance between each of the plurality of openings 15 is smaller than or equal to a first preset value, and the spacing distance between the peripheral openings of the plurality of openings 15 and the terminal position of the top metal 13 (i.e., the boundary between the chip region of the semiconductor device and the outer region 122 of the chip 121) is smaller than or equal to a second preset value. Therefore, the opening arrays can be arranged in the upper surface area of each top metal 13 as much as possible according to the specific layout to realize the interconnection between the metal layers, so that the current can vertically go downwards from the upper layer to the lower layer as uniformly as possible, the resistance in the horizontal direction is reduced, and the uniformity of the current flowing in the semiconductor device is further improved. The first preset value and the second preset value may be set according to specific process conditions, which is not limited in the present invention, as long as the first preset value and the second preset value are set as small as possible under the permission of the existing process conditions.
Optionally, the plurality of apertures 15 are circular apertures (i.e., the plurality of apertures 15 are circular in cross-sectional shape), and the diameter of each of the plurality of apertures 15 is less than or equal to the first threshold; or the plurality of openings 15 are square openings (i.e., the plurality of openings 15 are square in cross-section), each of the plurality of openings 15 having a side length less than or equal to the first threshold. It will be appreciated that the cross-sectional shape of the plurality of apertures 15 may be any other shape that may be achieved by any conventional process.
As shown in fig. 2g, a redistribution layer 16 is formed to cover the upper surface of the passivation layer 14 and fill the plurality of openings 15. The re-wiring layer 16 is formed using conventional processes. Exposing the photoresist layer on the surface of the passivation layer 14 to form a photoresist layer pattern, for example, by using a photolithography technique; etching and modifying the photoresist layer pattern to form a rewiring layer pattern; and electroplating metal to form a rewiring layer line.
In this embodiment, the material of the redistribution layer 16 and the top metal 13 is copper. The metal resistance of a semiconductor device, such as a power transistor, may be reduced due to the small resistivity of copper (e.g., less than the resistivity of aluminum). Moreover, the prepared thickness of the rewiring layer 16 and the top metal 13 is thicker when the copper material is adopted compared with the copper-aluminum alloy material adopted in the traditional process, and the current capability of a semiconductor device (such as a power tube) can be further improved.
After forming the rewiring layer, further comprising: and arranging a bonding pad or a solder ball and/or an array bump on the rewiring layer. Or forming a protective layer covering the rewiring layer, and arranging a bonding pad or a welding ball and/or an array bump on the protective layer. The protective layer covering the rewiring layer can prevent water vapor and the like from corroding structures such as chips, wires and the like, and can be prepared by the same process as the passivation layer 14.
Based on the same principle, the present disclosure also relates to a packaging method for forming the packaging structure of the semiconductor device shown in fig. 3, which is substantially the same as the packaging method disclosed in fig. 2a to 2g, and the description of the same parts is omitted.
The difference lies in that: after the semiconductor device is formed, forming a second passivation layer on the upper surface of the semiconductor device; forming a plurality of second openings which are positioned at the upper part of the chip area and penetrate through the second passivation layer; forming a top metal layer on the upper surface of the second passivation layer corresponding to the chip region; forming a first passivation layer covering the upper surface of the second passivation layer; forming a plurality of first openings penetrating through the first passivation layer on the upper part of each top metal layer; and forming a rewiring layer which covers the upper surface of the first passivation layer and is filled with the first openings. The dimensions of the first openings and the second openings are all the same as those of the openings in the embodiment shown in fig. 1, and reference may be made to the description in fig. 3 for details, which are not repeated herein.
In summary, the invention realizes the electrical connection between the top metal and the rewiring layer by arranging the plurality of small-sized openings in the passivation layer on the top of the top metal, thereby realizing the uniformity of current flowing in the semiconductor device and further improving the current capability of the chip.
By setting the sizes of the plurality of openings and the spacing distance between each opening, the opening arrays can be arranged as many as possible according to a specific layout in the passivation layer of the chip region corresponding to the semiconductor device to realize interconnection between the metal layers, and the uniformity of current flowing in the semiconductor device is further improved. Meanwhile, the copper material is adopted to manufacture the top metal layer and the rewiring layer, so that the metal resistance of the semiconductor device is reduced.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (10)
1. A package structure of a semiconductor device, the package structure comprising:
a semiconductor substrate;
the semiconductor device is formed on the upper surface of the semiconductor substrate and comprises a chip area for realizing the function of the semiconductor device and an off-chip area surrounding the chip area;
a top metal layer located on the upper portion of the chip region;
a first passivation layer on the upper portion of the semiconductor device;
the rewiring layer is positioned on the upper surface of the first passivation layer;
a plurality of first openings penetrating through the first passivation layer are correspondingly arranged in the upper part of each top layer metal, and the plurality of first openings are used for realizing the electrical connection between the top layer metal and the rewiring layer.
2. The semiconductor device package structure of claim 1, wherein the first openings of each of the top metal layers are spaced apart from each other, and a distance between each of the first openings is less than or equal to a first predetermined value, an
And the spacing distance between the peripheral opening in the first openings and the terminal position of the top layer metal is less than or equal to a second preset value.
3. The package structure of a semiconductor device according to claim 2, further comprising:
a second passivation layer between the semiconductor device upper surface and the first passivation layer;
and the second openings are correspondingly arranged in the lower area of the top layer metal and penetrate through the second passivation layer.
4. The semiconductor device package structure of claim 3, wherein the second openings of the top metal lower region are spaced apart from each other, and a spacing distance between each of the second openings is smaller than or equal to a first predetermined value, an
And the spacing distance between the peripheral opening in the second openings and the terminal position of the top layer metal is less than or equal to a second preset value.
5. The package structure of the semiconductor device according to claim 4, wherein sizes of the plurality of first openings and the plurality of second openings are less than or equal to the first threshold.
6. The package structure of the semiconductor device according to claim 5, wherein a cross-sectional shape of the plurality of first openings and the plurality of second openings is a circle or a square.
7. The package structure of the semiconductor device according to claim 5, wherein a cavity of each first opening and each second opening is filled with a copper material.
8. The package structure of a semiconductor device according to claim 1, wherein an upper surface of the first passivation layer is flat.
9. The package structure of the semiconductor device according to claim 3, wherein the first passivation layer and the second passivation layer are formed using an oxide or an oxynitride.
10. The package structure of a semiconductor device according to claim 1, wherein the semiconductor substrate comprises: the epitaxial layer is formed on the substrate.
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