CN112151398A

CN112151398A - Chip packaging method

Info

Publication number: CN112151398A
Application number: CN201910560967.8A
Authority: CN
Inventors: 张为国; 张俊; 唐世弋
Original assignee: Shanghai Micro Electronics Equipment Co Ltd
Current assignee: Shanghai Micro Electronics Equipment Co Ltd
Priority date: 2019-06-26
Filing date: 2019-06-26
Publication date: 2020-12-29
Anticipated expiration: 2039-06-26
Also published as: WO2020258493A1; CN112151398B

Abstract

The embodiment of the invention discloses a chip packaging method. The chip packaging method comprises the following steps: providing a carrier plate; forming a rewiring layer on the carrier plate; forming a conductive bump structure on the rewiring layer; welding a chip pin with the conductive salient point structure to form a chip packaging structure; and applying uniform pressure to the region of the conductive bump structure, and simultaneously carrying out laser annealing on the region of the conductive bump structure. The embodiment of the invention solves the problem that the redistribution layer is easy to warp to influence the position of an electrical structure in a chip packaging structure and cause poor chip quality in the prior art, and can relieve or even eliminate the warp of the redistribution layer through the cooperation of laser annealing and pressure application, avoid poor electrical connection in the chip packaging structure and ensure the quality of a packaged chip.

Description

Chip packaging method

Technical Field

The embodiment of the invention relates to a semiconductor technology, in particular to a chip packaging method.

Background

Chip packaging refers to the routing of circuit pins on a chip to external connections for connection to other devices. The package form refers to a housing for mounting a semiconductor integrated circuit chip. The chip is not only used for mounting, fixing, sealing, protecting the chip and enhancing the electric heating performance, but also connected to pins of the packaging shell through the connection points on the chip by leads, and the pins are connected with other devices through the leads on the printed circuit board, thereby realizing the connection of the internal chip and an external circuit.

The conventional packaging method generally includes soldering a chip to a carrier, where the carrier is provided with a redistribution layer and conductive bumps soldered to the chip, and the pins of the chip are soldered to the conductive bumps, and then the redistribution layer leads out the circuit pins of the chip. However, after the redistribution layer in the carrier is formed, because a heating process exists in the subsequent packaging step, for example, in a reflow soldering process adopted during soldering, solder needs to be melted for soldering, and at this time, the redistribution layer material is likely to deform at the contact position with the materials such as the conductive bumps due to different thermal expansion coefficients in the process of temperature rise and drop, which causes the problem of warpage of the redistribution layer, causes the positions of the redistribution layer and other structures to change, affects the contact effect of the conductive structure in the packaged chip, and degrades the quality of the packaged chip.

Disclosure of Invention

The invention provides a chip packaging method, which is used for eliminating or weakening the warpage of a rewiring layer on a carrier plate and ensuring the quality of a packaged chip.

In a first aspect, an embodiment of the present invention provides a chip packaging method, including:

providing a carrier plate;

forming a rewiring layer on the carrier plate;

forming a conductive bump structure on the rewiring layer;

welding a chip pin with the conductive salient point structure to form a chip packaging structure;

and applying uniform pressure to the region of the conductive bump structure, and simultaneously carrying out laser annealing on the region of the conductive bump structure.

Optionally, the performing laser annealing on the region of the conductive bump structure includes:

and performing laser annealing on the region of the conductive bump structure by adopting pulse laser.

Optionally, the wavelength of the pulsed laser is in the range of 0.8-2 μm.

Optionally, the power of the pulsed laser is in the range of 0.01-30W.

Optionally, the applying uniform pressure on the region of the conductive bump structure includes:

placing the chip packaging structure on a workbench, wherein the carrier plate of the chip packaging structure deviates from the workbench;

placing a transparent pressing plate on one side of the support plate, which is far away from the workbench;

applying uniform pressure to the transparent platen.

and applying uniform pressure to the area of the conductive bump structure on one side of the carrier plate, which is far away from the workbench, through an air supply device.

Optionally, the stage temperature ranges from 20-40 ℃.

Optionally, the uniform pressure may generate a pressure in the range of 100-1000 pa.

Optionally, before applying uniform pressure to the region of the conductive bump structure and performing laser annealing on the region of the conductive bump structure, the method further includes:

and placing the chip packaging structure in an inert gas environment.

Optionally, the conductive bump structure includes a metal conductive pillar, and the forming of the conductive bump structure on the redistribution layer includes:

forming a metal seed layer pattern on the rewiring layer;

and forming a metal conductive pillar pattern on the metal seed layer pattern.

Optionally, after forming the metal seed layer pattern on the redistribution layer, the method further includes:

performing primary laser annealing on the region where the metal seed layer pattern is located;

and/or after forming the metal conductive pillar pattern on the metal seed layer pattern, further comprising:

and carrying out primary laser annealing on the region where the metal conductive column pattern is located.

Optionally, the laser wavelength range of the preliminary laser annealing is 1-20 μm.

Optionally, the laser power of the preliminary laser annealing ranges from 1 mW to 300 mW.

The chip packaging method provided by the embodiment of the invention comprises the steps of forming a rewiring layer on a carrier plate, forming a conductive bump structure on the rewiring layer, welding chip pins with the conductive bump structure to form a chip packaging structure, and finally applying uniform pressure to the area where the conductive bump structure is located and performing laser annealing, so that on one hand, a flattening force is applied to the warped rewiring layer in the formed chip packaging structure, on the other hand, the warped rewiring layer is subjected to stress release by using laser annealing treatment, the shape of the rewiring layer is changed, the warped rewiring layer is restored to be flat, and the problems that the rewiring layer is easy to warp in the prior art, the position of an electrical structure in the chip packaging structure is influenced, and the quality of a chip is poor are solved, the bad electrical connection in the chip packaging structure is avoided, and the quality of the packaged chip is ensured.

Drawings

Fig. 1 is a flowchart of a chip packaging method according to an embodiment of the present invention;

FIG. 2 is a flow chart of the structure of the chip packaging method shown in FIG. 1;

FIG. 3 is a graph providing penetration depth in silicon for different wavelengths according to an embodiment of the present invention;

FIG. 4 is a flow chart of another chip packaging method provided by the embodiment of the invention;

FIG. 5 is a flow chart of the structure of the chip packaging method shown in FIG. 4;

fig. 6 is a flowchart of a further chip packaging method according to an embodiment of the present invention;

FIG. 7 is a flow chart of the structure of the chip packaging method shown in FIG. 6;

fig. 8 is a flowchart of another chip package structure provided in an embodiment of the present invention;

fig. 9 is a graph of metal absorption coefficient and thermal conductivity according to an embodiment of the present invention.

The device comprises a carrier plate 10, a rewiring layer 20, a conductive bump structure 30, a chip 40, a chip packaging structure 50, a workbench 60, a transparent pressing plate 70 and an air supply device 80.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a flowchart of a chip packaging method according to an embodiment of the present invention, and fig. 2 is a structural flowchart of the chip packaging method shown in fig. 1, and with reference to fig. 1 and fig. 2, the chip packaging method includes:

s110, providing a carrier plate 10;

referring to step a) of fig. 2, in the flip chip structure, a carrier is usually required to be disposed for bonding the electrical surface of the chip on the carrier, conducting the electrical wires out through the carrier, and packaging and protecting the chip by using the carrier. The carrier plate is usually a silicon wafer.

S120, forming a rewiring layer 20 on the carrier plate 10;

referring to step b) of fig. 2, the electrical structure on the carrier 10 includes a redistribution layer 20, and the redistribution layer 20 leads out the chip pins for electrically connecting to an external electronic device.

S130, forming a conductive bump structure 30 on the rewiring layer 20;

referring to step c) of fig. 2, when the redistribution layer 20 is soldered to a chip, a conductive bump structure 30 for soldering a chip pin is required to be disposed on the redistribution layer 20, and the common conductive bump structure 30 includes a tin-lead pillar, a gold ball bump, a copper pillar, a conductive adhesive bump, a polymer bump, and the like, wherein the copper pillar is most widely used.

S140, welding pins of the chip 40 with the conductive bump structures 30 to form a chip packaging structure 50;

referring to step d) of fig. 2, the soldering process of the conductive bump structure 30 and the pin of the chip 40 may generally form a solder ball on the conductive bump structure, and after the chip 40 is aligned and mounted on the carrier, the solder ball is melted by a reflow process to realize the soldering process. After the chip is soldered, the carrier board needs to be filled with an organic material and a dielectric layer to protect the redistribution layer and the chip on the carrier board, and finally the chip package structure 40 is formed. In the chip package structure 40 shown in fig. 2, the height of the copper pillar is usually 5-80 um.

S150, applying uniform pressure to the area where the conductive bump structure 30 is located, and simultaneously performing laser annealing on the area where the conductive bump structure 30 is located.

Referring to step e) of fig. 2, in the step of forming the chip package structure 40, for example, in the process of forming the conductive bump structure 30 and the process of soldering with the pin of the chip 40, a temperature rise or a heating process is caused, and the processes of temperature rise and temperature fall may deform the redistribution layer 20 and the conductive bump structure 30, and the redistribution layer 20 may warp due to the different materials of the redistribution layer 20 and the conductive bump structure 30 and the different thermal expansion coefficients. Therefore, the position of the redistribution layer 20 where warpage occurs is mostly in the region where the conductive bump structure 30 is located, a uniform pressure is applied to the region, the warped redistribution layer 20 can be flattened, and the region is processed by laser annealing (not shown), so that the redistribution layer 20 at the position is deformed when absorbing and releasing laser heat, thereby releasing stress causing warpage. And under the action of the uniform leveling pressure, the form of the redistribution layer 20 can be changed to a flat state, thereby weakening or even eliminating the warping phenomenon of the redistribution layer 20.

Considering that the chip packaging structure has already preliminarily finished the chip structure packaging, the laser annealing process is used to process the redistribution layer in the region where the conductive bump structure is located, so as to avoid the laser energy from being too high to damage other electrical structures in the chip packaging structure. Therefore, in step S150, optionally, laser annealing the region of the conductive bump structure includes: and performing laser annealing on the region of the conductive bump structure by adopting pulse laser. The pulse laser has lower laser energy relative to the continuous laser, so that the damage of the internal electrical structure in the chip packaging structure by the laser with higher energy can be avoided. Optionally, the power range of the pulse laser can be selected from 0.01-30W, so that the heat generated by the laser can be effectively controlled during the annealing of the pulse laser, and the annealing effect can be conveniently controlled. To ensure better control, the pulse width can be selected in the range of 1-100ns to further reduce the instantaneous energy of the pulsed laser.

In addition, when performing laser annealing, laser needs to be provided from one side of the carrier of the chip package structure, and at this time, the laser needs to penetrate the carrier and act on the redistribution layer. Fig. 3 is a graph showing penetration depths of different wavelengths in silicon according to an embodiment of the present invention, and referring to fig. 3, considering that the thickness of a silicon wafer used for a carrier is more than several tens to several hundreds of micrometers, in order to ensure the penetration effect of laser, the wavelength of pulse laser may be set to be not less than 800 nm. Meanwhile, the wavelength of the pulse laser can be limited to be not more than 2 μm in order to avoid the too high penetration effect of the laser to influence other structures in the annealing environment.

In order to provide a leveling force during laser annealing to change the warped redistribution layer back to a flat state, a uniform pressure needs to be applied to the chip package structure. Optionally, the pressure range generated by the uniform pressure should be within the range of 100-1000pa, wherein when the pressure range is smaller than 100pa, the leveling force provided by the uniform pressure is not enough to change the form of the warped redistribution layer, and by setting the pressure of the uniform pressure to be larger than 100pa, effective extrusion on the warped redistribution layer can be realized, and the redistribution layer is driven to return to the leveling state. In addition, the strength of the chip packaging structure is low, and when the pressure exceeds 1000pa, the chip packaging structure is easily damaged by compression, so that the pressure with uniform pressure does not exceed 1000 pa.

Specifically, the embodiment of the invention provides two ways of applying pressure to the chip packaging structure, which can be divided into two ways of mechanically applying pressure to a rigid structure and applying pressure to a high air pressure. Fig. 4 is a flowchart of another chip packaging method according to an embodiment of the present invention, and fig. 5 is a flowchart of a structure of the chip packaging method shown in fig. 4, and with reference to fig. 4 and fig. 5, the chip packaging method includes:

s210, providing a carrier plate 10;

s220, forming a rewiring layer 20 on the carrier plate;

s230, forming a conductive bump structure 30 on the rewiring layer;

s240, welding the pins of the chip 40 with the conductive bump structures 30 to form a chip packaging structure 50;

s250, placing the chip package structure 50 on a worktable 60, and making the carrier board 10 of the chip package structure 50 depart from the worktable 60;

referring to step e) in fig. 5, the surface of the worktable 60 is a flat surface, and the chip package structure 50 is flipped over on the worktable 60, that is, the chip in the chip package structure 50 is close to the worktable, and the carrier 10 is away from the worktable, at this time, laser can be emitted from one side of the carrier 10 during laser annealing, and laser annealing treatment is implemented through the laser-transmissive carrier 10.

S260, placing a transparent pressing plate 70 on one side of the carrier plate 10, which is far away from the workbench 60;

referring to step f) in fig. 5, the transparent pressing plate 70 may be a rigid glass substrate, and the laser can act on the chip package structure 50 through the glass substrate.

S270, applying uniform pressure to the transparent pressing plate 70, and performing laser annealing on the region where the conductive bump structure 50 is located.

Referring to step g) in fig. 5, applying a uniform pressure to the transparent pressing plate 70 may further press the chip package structure 50 on the worktable 60, so as to ensure that a flat pressure exists in the chip package structure 50.

Fig. 6 is a flowchart of another chip packaging method according to an embodiment of the present invention, and fig. 7 is a flowchart of a structure of the chip packaging method shown in fig. 6, and with reference to fig. 6 and 7, the chip packaging method includes:

s310, providing a carrier plate 10;

s320, forming a redistribution layer 20 on the carrier 10;

s330, forming a conductive bump structure 30 on the rewiring layer 20;

s340, welding pins of the chip 40 with the conductive bump structures 30 to form a chip packaging structure 50;

s350, placing the chip package structure 50 on a workbench 60, and the carrier 10 of the chip package structure 50 is away from the workbench 60;

and S360, applying uniform pressure to the region of the conductive bump structure 30 on the side of the carrier plate 10 away from the workbench 60 through the gas supply device 80, and performing laser annealing on the region of the conductive bump structure 30.

Referring to step f) in fig. 7, the gas supply device 80 is disposed above the worktable 60, and applies gas pressure to the chip package structure 50 through the gas holes or gas passages, so as to press the chip package structure with the gas pressure to form a leveling pressure. Compared with a mode of applying pressure by adopting a transparent pressing plate in a contact mode, the mode of applying pressure by air pressure can conveniently adjust and control the applied pressure, and meanwhile, the physical damage to the chip packaging structure can be reduced, and the chip packaging structure is protected. It should be noted that the structure of the air supply device 80 and the manner of applying air pressure are shown in the figures as examples, and those skilled in the art can design the air supply device according to specific situations, and the invention is not limited thereto.

Further, in order to avoid damage to the chip in the chip packaging structure by laser, the workbench can be arranged to have a temperature adjusting function. It is understood that, in both of the above-described ways of applying the pressing and leveling force, the chip package structure is placed on the worktable, and the carrier plate of the chip package structure is away from the worktable, and the chip is close to the worktable. In the laser annealing process, the laser may penetrate the carrier and act on the chip, so as to heat the chip. At the moment, the temperature of the workbench can be regulated to be stabilized at 20-40 ℃ during laser annealing, so that the temperature of the chip close to the workbench is stabilized, and the chip is prevented from being damaged by laser.

In the laser annealing process, the temperature of the rewiring layer in the chip packaging structure can be changed, and at a higher temperature, the electric structure in the chip packaging structure is easy to oxidize or corrode, so that uniform pressure can be applied to the area where the conductive bump structure is located, and the chip packaging structure is placed in an inert gas environment before laser annealing is performed on the area where the conductive bump structure is located. The inert gas atmosphere may be a nitrogen atmosphere or the like.

In a typical chip package structure, the conductive bump structure includes a metal conductive pillar structure, and when the metal conductive pillar structure is disposed on the redistribution layer, the metal conductive pillar structure needs to be fixedly connected to the redistribution layer. Therefore, optionally, an embodiment of the present invention further provides a chip packaging method, fig. 8 is a flowchart of another chip packaging structure provided in the embodiment of the present invention, and with reference to fig. 8, the chip packaging structure includes:

s410, providing a carrier plate;

s420, forming a rewiring layer on the carrier plate;

s430, forming a metal seed layer pattern on the rewiring layer;

when the metal conductive column structure is formed on the redistribution layer, the adhesion force of the metal conductive column structure on the redistribution layer is low, poor contact is easy to occur, in order to better fix the metal conductive column structure, a metal seed layer can be firstly deposited on the redistribution layer, and then the metal conductive column structure is prepared and formed on the metal seed layer, and at the moment, the metal conductive column structure has good adhesion force with the redistribution layer through the metal seed layer, and poor connection of the metal conductive column structure can be avoided.

S440, performing primary laser annealing on the region where the metal seed layer pattern is located;

the preparation thickness of the metal seed layer is 2-8 mu m, the temperature is increased when the metal seed layer pattern is formed, the position of the heavy wiring layer deposited with the metal seed layer is easy to generate deformation stress, and therefore warping occurs.

S450, forming a metal conductive column pattern on the metal seed layer pattern, wherein the conductive bump structure comprises a metal conductive column;

the metal conductive pillar pattern is typically formed by an electroplating process and has a height of about 10-100 μm. Similarly, a drastic change in temperature occurs during the plating process, and at this time, the redistribution layer is likely to be deformed and stress-concentrated, thereby causing a warpage phenomenon.

S460, performing primary laser annealing on the region where the metal conductive column pattern is located;

at this time, the preliminary laser annealing step can also release the deformation stress generated by the redistribution layer during the preparation and formation of the metal conductive pillar pattern, so as to weaken the warping phenomenon.

S470, welding the chip pin with the conductive bump structure to form a chip packaging structure;

s480, applying uniform pressure to the region of the conductive bump structure, and simultaneously performing laser annealing on the region of the conductive bump structure.

It should be noted that, after the metal seed layer pattern is formed on the redistribution layer, a step of performing preliminary laser annealing on the region where the metal seed layer pattern is located, and a step of performing preliminary laser annealing on the region where the metal conductive pillar pattern is located after the metal conductive pillar pattern is formed on the metal seed layer pattern, may be selectively added by a person skilled in the art according to an actual process flow, and exemplarily, the step of performing preliminary laser annealing may also be performed only after the metal conductive pillar pattern is formed, and this is not limited here.

In order to facilitate the control of the effect of the preliminary laser annealing, the pulsed laser can also be selected during the preliminary laser annealing. However, since the chip is welded after the metal seed layer pattern and the metal conductive pillar pattern are formed, when the preliminary laser annealing is performed on the metal seed layer pattern and the metal conductive pillar pattern, the chip may be damaged without consideration, and thus the annealing may be performed by selecting a continuous laser. The power range in which the laser is effective also needs to be taken into account when annealing with a continuous laser, optionally with a laser power range of 1-300mW for the preliminary laser annealing. It should be noted that, the metal seed layer and the metal conductive pillar are both made of metal materials, and are usually in a copper pillar structure. Fig. 9 is a graph of absorption coefficient and thermal conductivity of metal provided by an embodiment of the present invention, and referring to fig. 9, the wavelength absorption range of the conductive material of copper is less than 1 μm, and optionally, the laser wavelength range of the preliminary laser annealing is 1-20 μm in order to avoid the metal conductive pillar responding to the laser during the preliminary laser annealing. At the moment, the laser annealing does not act on the metal seed layer, so that the laser annealing treatment does not influence the metal conductive column structure.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method of chip packaging, comprising:

providing a carrier plate;

forming a rewiring layer on the carrier plate;

forming a conductive bump structure on the rewiring layer;

2. The chip packaging method according to claim 1, wherein the laser annealing the region of the conductive bump structure comprises:

3. The chip packaging method according to claim 2, wherein the wavelength of the pulsed laser is in a range of 0.8-2 μm.

4. The chip packaging method according to claim 2, wherein the power of the pulsed laser is in the range of 0.01-30W.

5. The chip packaging method according to claim 1, wherein the applying uniform pressure to the area of the conductive bump structure comprises:

applying uniform pressure to the transparent platen.

6. The chip packaging method according to claim 1, wherein the applying uniform pressure to the area of the conductive bump structure comprises:

7. The chip packaging method according to claim 5 or 6, wherein the temperature of the working table is in a range of 20-40 ℃.

8. The chip packaging method as claimed in claim 1, wherein the pressure generated by the uniform pressure is in the range of 100-1000 pa.

9. The chip packaging method according to claim 1, wherein before applying uniform pressure to the region of the conductive bump structure and laser annealing the region of the conductive bump structure, the method further comprises:

and placing the chip packaging structure in an inert gas environment.

10. The chip packaging method according to claim 1, wherein the conductive bump structure comprises a metal conductive pillar, and the forming of the conductive bump structure on the redistribution layer comprises:

forming a metal seed layer pattern on the rewiring layer;

and forming a metal conductive pillar pattern on the metal seed layer pattern.

11. The chip packaging method according to claim 10, further comprising, after forming the metal seed layer pattern on the redistribution layer:

12. The chip packaging method according to claim 11, wherein the laser wavelength of the preliminary laser annealing is in a range of 1-20 μm.

13. The chip packaging method according to claim 11, wherein the laser power of the preliminary laser annealing is in a range of 1-300 mW.