CN112150974A - Display method, time schedule controller and display device - Google Patents
Display method, time schedule controller and display device Download PDFInfo
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- CN112150974A CN112150974A CN201910560456.6A CN201910560456A CN112150974A CN 112150974 A CN112150974 A CN 112150974A CN 201910560456 A CN201910560456 A CN 201910560456A CN 112150974 A CN112150974 A CN 112150974A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention provides a display method, a time sequence controller and a display device, wherein the display method is applied to the display device and comprises the following steps: detecting a control signal of the backlight module; if the control signal is detected to be a low level signal, outputting a first line frequency clock signal to the gate driving circuit, and determining a first output frequency of a data signal to the source driving circuit according to the first line frequency clock signal; if the control signal is detected to be a high-level signal, outputting a second line frequency clock signal to the gate driving circuit, and determining a second output frequency for outputting a data signal to the source driving circuit according to the second line frequency clock signal; the duration of the high level of the first line frequency clock signal is less than the duration of the high level of the second line frequency clock signal. The high level time length of the line frequency clock signal determines the voltage charged into the pixel, so that the charging rate of the pixel can be improved by changing the line frequency clock signal, the poor waterfall line of the display device is avoided, and the display effect is improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display method, a timing controller, and a display device.
Background
As shown in fig. 1, a PWM signal cycle of the backlight module is T, a high level time is H (a bright state of the backlight module at this time) and a low level time is L (a dark state of the backlight module at this time) in one cycle, and human eyes cannot recognize bright and dark switching of the backlight module due to a high frequency of a PMW signal, and can only perceive the overall brightness. The brightness of the backlight module is related to the duty ratio of high and low levels of the PWM signals, and the larger the H ratio is, the higher the overall brightness of the backlight module is, and the lower the overall brightness of the backlight module is.
Referring to fig. 2 and 3, when the PWM signal is at a high level (when the backlight module is in a bright state), the corresponding display area on the display panel is darker, and when the PWM signal is at a low level (when the backlight module is in a dark state), the corresponding display areas (i) and (iii) on the display panel are brighter, forming a horizontal Block (Block) with alternating light and shade, i.e., a waterfall pattern (Water fall) defect.
Disclosure of Invention
In view of the above, the present invention provides a display method, a timing controller and a display device, which are used to solve the problem of poor waterfall lines on the display device caused by the brightness and darkness switching of a backlight module.
In order to solve the above technical problem, the present invention provides a display method applied to a display device, where the display device includes a display panel, a backlight module, a gate driving circuit, and a source driving circuit, and the method includes:
detecting a control signal of the backlight module;
if the control signal is detected to be a low level signal, outputting a first line frequency clock signal to the gate driving circuit, and determining a first output frequency of a data signal to the source driving circuit according to the first line frequency clock signal; if the control signal is detected to be a high-level signal, outputting a second line frequency clock signal to the gate driving circuit, and determining a second output frequency of outputting a data signal to the source driving circuit according to the second line frequency clock signal;
wherein the duration of the high level of the first line frequency clock signal is less than the duration of the high level of the second line frequency clock signal.
Optionally, the frequency of the first line frequency clock signal is equal to a reference frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is smaller than the reference frequency and greater than a lowest cut-off frequency of the line frequency clock signal; or
The frequency of the first line frequency clock signal is greater than the reference frequency and less than the highest cut-off frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is equal to the reference frequency.
Optionally, the display method further includes:
outputting a false line frequency clock signal to the gate drive circuit at the end of each frame period;
if the frequency of the first line frequency clock signal is greater than the reference frequency, the outputting a dummy line frequency clock signal to the gate driving circuit includes:
increasing the number of the false line frequency clock signals in each frame to make each frame have a specified duration;
if the frequency of the second line frequency clock signal is less than the reference frequency, the outputting a dummy line frequency clock signal to the gate driving circuit includes:
reducing the number of false line frequency clock signals in each frame to have a specified duration for each frame.
Optionally, before detecting the control signal of the backlight module, the method further includes:
and when the line frequency clock signal and the data signal of the current frame are processed, caching the line frequency clock signal and the data signal of the next frame.
The invention also provides a time sequence controller, which is applied to a display device, wherein the display device comprises a display panel, a backlight module, a grid drive circuit and a source drive circuit, and the time sequence controller comprises:
the detection module is used for detecting a control signal of the backlight module;
the first output module is used for outputting a first line frequency clock signal to the gate driving circuit if the control signal is detected to be a low level signal, and determining a first output frequency of a data signal to the source driving circuit according to the first line frequency clock signal;
the second output module is used for outputting a second line frequency clock signal to the gate driving circuit if the control signal is detected to be a high level signal, and determining a second output frequency of the data signal to the source driving circuit according to the second line frequency clock signal;
wherein the duration of the high level of the first line frequency clock signal is less than the duration of the high level of the second line frequency clock signal.
Optionally, the frequency of the first line frequency clock signal is equal to a reference frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is smaller than the reference frequency and greater than a lowest cut-off frequency of the line frequency clock signal; or
The frequency of the first line frequency clock signal is greater than the reference frequency and less than the highest cut-off frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is equal to the reference frequency.
Optionally, the timing controller further includes: a third output module, configured to output a false line frequency clock signal to the gate driver circuit at the end of each frame period; if the frequency of the first line frequency clock signal is greater than the reference frequency, increasing the number of the false line frequency clock signals in each frame so that each frame has a specified duration; if the frequency of the second line frequency clock signal is less than the reference frequency, the number of the false line frequency clock signals in each frame is reduced, so that each frame has a specified duration.
Optionally, the timing controller further includes:
and the buffer module is used for buffering the line frequency clock signal and the data signal of the next frame when the line frequency clock signal and the data signal of the current frame are processed.
The invention also provides a display device which comprises the time sequence controller.
Optionally, the display device further includes a display panel, the display panel includes a data line and a semiconductor layer, the data line is in contact with the semiconductor layer in an overlapping manner, and an orthographic projection of the data line on the semiconductor layer completely falls on the semiconductor layer.
The technical scheme of the invention has the following beneficial effects:
in the embodiment of the invention, the control signal of the backlight module is detected, when the control signal of the backlight module is different (a low level signal or a high level signal), two different line frequency clock signals are input to the grid drive circuit, the high level time lengths of the two different line frequency clock signals are different, the voltage charged into the pixels is determined by the high level time length of the line frequency clock signals, the longer the high level time length is, the longer the charging time of the pixels is, the brighter the display is, therefore, by changing the line frequency clock signals, the charging rate of the pixels can be improved, the brightness of each line of pixels on the display panel is the same or approximately the same, the occurrence of poor waterfall lines is avoided, and the display effect is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a PWM signal of a backlight module;
FIG. 2 is a schematic diagram illustrating a waterfall line defect displayed on a panel;
FIG. 3 is a schematic diagram illustrating a corresponding relationship between the display area and the PWM signal of the backlight module in FIG. 2;
FIGS. 4 and 5 are schematic diagrams illustrating differences in conductivity of semiconductor regions in the case of a backlight module without illumination;
FIG. 6 is a schematic diagram of pixel voltages under the condition of no illumination of the backlight module;
FIG. 7 is a diagram illustrating a display method according to an embodiment of the invention;
fig. 8 is a schematic diagram of a row frequency clock signal (row CLK) input to a gate driving circuit and a Data signal (Data input) input to a Data line in the related art;
fig. 9 is a schematic diagram of a row clock signal (row CLK) input to the gate driving circuit and a Data signal (Data input) input to the Data line according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a row frequency clock signal (row CLK) input to a gate driving circuit and a Data signal (Data input) input to a Data line in the related art;
fig. 11 is a schematic diagram of a row clock signal (row CLK) input to the gate driving circuit and a Data signal (Data input) input to the Data lines according to another embodiment of the present invention;
FIG. 12 is a flowchart illustrating a display method according to another embodiment of the present invention;
FIG. 13 is a diagram illustrating a method for adjusting the frequency of a horizontal clock signal in a step manner according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of a timing controller according to an embodiment of the invention;
fig. 15 is a schematic structural diagram of a timing controller according to another embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention, are within the scope of the invention.
The reason why the display device generates the waterfall line will be described first.
The display device comprises a display panel and a backlight module, the display panel comprises an array substrate and a color film substrate, the array substrate comprises a semiconductor layer (Active) and a Data line (Data), the semiconductor layer and the Data line can be formed through a mask, so that the formed Data line is in superposed contact with the semiconductor layer, and the orthographic projection of the Data line on the semiconductor layer completely falls onto the semiconductor layer.
When the backlight module is in a bright state (i.e., when the PWM signal is at a high level), the backlight emitted from the backlight module may affect the conductor characteristics of the semiconductor layer on the display panel. As shown in fig. 4 and 5, the semiconductor layer under the data line has a conductor characteristic under the backlight irradiation (the diagonal pattern in fig. 4 and 5 indicates the conductor), and at this time, the parasitic capacitance between the data line & semiconductor layer and the pixel electrode & common electrode (pixel & Com) (not shown) on the array substrate is large, which causes the RC Delay (RC Delay) of the data line to become large, the actual charging time is short, the pixel voltage is low, and referring to fig. 6, the display brightness of the display panel is low. When the semiconductor layer below the data line is not irradiated by backlight, the parasitic capacitance between the data line and the semiconductor layer and the pixel electrode and the common electrode is small, the data line does not have an RC Delay, the actual charging time is sufficient, the pixel voltage is higher under the same data voltage, referring to fig. 6, the display brightness of the display panel is high, and further, a horizontal block, namely, a waterfall line defect, caused by a brightness difference may occur on the display panel.
To solve the above problem, referring to fig. 7, an embodiment of the present invention provides a display method applied to a display device, where the display device includes a display panel, a backlight module, a gate driving circuit, and a source driving circuit, and the display method includes:
step 71: detecting a control signal of the backlight module;
in the embodiment of the present invention, the control signal may be a PWM signal.
Step 72: if the control signal is detected to be a low level signal, outputting a first line frequency clock signal to the gate driving circuit, and determining a first output frequency of a data signal to the source driving circuit according to the first line frequency clock signal; the first output frequency is matched with the frequency of the first line frequency clock signal so as to ensure that a correct data signal is input to the source electrode driving circuit;
step 73: if the control signal is detected to be a high-level signal, outputting a second line frequency clock signal to the gate driving circuit, and determining a second output frequency for outputting a data signal to the source driving circuit according to the second line frequency clock signal; the second output frequency is matched with the frequency of the second line frequency clock signal so as to ensure that a correct data signal is input to the source electrode driving circuit;
wherein the duration of the high level of the first line frequency clock signal is less than the duration of the high level of the second line frequency clock signal.
In the embodiment of the invention, the control signal of the backlight module is detected, when the control signal of the backlight module is different (a low level signal or a high level signal), two different line frequency clock signals are input to the grid drive circuit, the high level time lengths of the two different line frequency clock signals are different, the voltage charged into the pixels is determined by the high level time length of the line frequency clock signals, the longer the high level time length is, the longer the charging time of the pixels is, the brighter the display is, therefore, by changing the line frequency clock signals, the charging rate of the pixels can be improved, the brightness of each line of pixels on the display panel is the same or approximately the same, the occurrence of poor waterfall lines is avoided, and the display effect is improved.
In the embodiment of the present invention, the duration of the high level of the line frequency clock signal input to the gate driving circuit may be changed by adjusting the frequency of the line frequency clock signal input to the gate driving circuit.
Referring to fig. 8, fig. 8 is a schematic diagram of a row clock signal (row CLK) input to a gate driving circuit and a Data signal (Data input) input to a Data line in the related art, and it can be seen from fig. 8 that, in the related art, when a backlight module is in a dark state and a backlight module is in a bright state, the row clock signal (row CLK) input to the gate driving circuit is the same, and both the row CLK with a reference frequency is used, and if the Data signals (i.e., pixel voltages) input to the Data lines are the same, it can be seen from a pixel charging curve in fig. 8 that a pixel voltage charged to a pixel in the bright state of the backlight module is significantly lower than a pixel voltage charged to the pixel in the dark state of the backlight module, thereby causing a waterfall defect.
Referring to fig. 9, fig. 9 is a schematic diagram of a row clock signal (row CLK) input to the gate driving circuit and a Data signal (Data input) input to the Data line according to an embodiment of the present invention, and it can be seen from fig. 9 that, in the embodiment of the present invention, when the backlight module is in a dark state and the backlight module is in a light state, the row clock signal (row CLK) input to the gate driving circuit is different, and when the backlight module is in the light state, the number of high levels of the row CLK signal is reduced and the duration of the high levels is increased compared with the row CLK signal in the related art, that is, the frequency of the row CLK is less than the related reference frequency. If the data signals (i.e., pixel voltages) input to the data lines are the same, it can be seen from the pixel charging curve in fig. 9 that the pixel voltage charged to the pixels in the bright state of the backlight module is equal to or approximately equal to the pixel voltage charged to the pixels in the dark state of the backlight module, so as to solve the problem of poor waterfall stripes.
In the embodiment shown in fig. 9, if it is detected that the control signal is a low level signal (i.e., the backlight module is in a dark state), a first line frequency clock signal is output to the gate driving circuit, and the frequency of the first line frequency clock signal is equal to the reference frequency of the line frequency clock signal. If the control signal is detected to be a high level signal (namely, the backlight module is in a bright state), outputting a second line frequency clock signal to the gate driving circuit, wherein the frequency of the second line frequency clock signal is smaller than the reference frequency and larger than the lowest cut-off frequency of the line frequency clock signal (the lowest cut-off frequency is the lowest frequency adopted by the line frequency clock signal capable of being input to the gate driving circuit). That is, when the backlight module is in a bright state, the frequency of the line frequency clock signal input to the gate driving circuit is reduced, and when the backlight module is in a dark state, the line frequency clock signal is input to the gate driving circuit according to the reference frequency.
In other embodiments of the present invention, the problem of poor waterfall lines can be solved by increasing the frequency of the line frequency clock signal input to the gate driving circuit when the backlight module is in a dark state.
Referring to fig. 10, fig. 10 is a schematic diagram of a row clock signal (row CLK) input to a gate driving circuit and a Data signal (Data input) input to a Data line in the related art, and it can be seen from fig. 10 that, in the related art, when a backlight module is in a dark state and a backlight module is in a bright state, the row clock signal (row CLK) input to the gate driving circuit is the same, and both the row CLK with a reference frequency is used, and if the Data signals (i.e., pixel voltages) input to the Data lines are the same, it can be seen from a pixel charging curve in fig. 10 that a pixel voltage charged to a pixel in the bright and dark states of the backlight module is obviously higher than a pixel voltage charged to the pixel in the bright state of the backlight module, thereby causing a waterfall defect.
Referring to fig. 11, fig. 11 is a schematic diagram of a row clock signal (row CLK) input to a gate driving circuit and a Data signal (Data input) input to a Data line according to another embodiment of the present invention, and it can be seen from fig. 11 that, in the embodiment of the present invention, the row clock signal (row CLK) input to the gate driving circuit is different when the backlight module is in a dark state and when the backlight module is in a light state, and when the backlight module is in a dark state, the number of high levels of the row CLK signal is increased and the duration of the high levels is shortened compared with the row CLK signal in the related art, that is, the Frequency (FK) of the row CLK is greater than the related reference frequency. If the data signals (i.e., pixel voltages) input to the data lines are the same, it can be seen from the pixel charging curve in fig. 11 that the pixel voltage charged to the pixels in the dark state of the backlight module is equal to or approximately equal to the pixel voltage charged to the pixels in the bright state of the backlight module, so as to solve the problem of poor waterfall stripes.
In the embodiment shown in fig. 11, if the control signal is detected to be a low level signal (i.e. the backlight module is in a dark state), the first row clock signal is output to the gate driving circuit, and the Frequency (FK) of the first row clock signal is greater than the reference frequency and less than the highest cut-off frequency of the row clock signal (the highest cut-off frequency is the highest frequency that can be used for the clock signal input to the gate driving circuit). If the control signal is detected to be a high level signal (i.e. the backlight module is in a bright state), outputting a second line frequency clock signal to the gate driving circuit, wherein the frequency of the second line frequency clock signal is a reference frequency (F1). That is, when the backlight module is in a dark state, the frequency of the line frequency clock signal input to the gate driving circuit is increased, and when the backlight module is in a bright state, the line frequency clock signal is input to the gate driving circuit according to the reference frequency.
In fig. 9-11, STV refers to a frame start signal, i.e., a control signal at the beginning of a frame.
Referring to fig. 9 and 11, in the embodiment of the present invention, if the line CLK signal has ended but the time of one frame has not ended, it is ensured that one frame has a specified duration by inputting a dummy line frequency clock signal (dummy CLK) to the gate driving circuit at the end of one frame period. The dummy line frequency clock signal is a line frequency clock signal that is not actually input to the gate driving circuit. Referring to fig. 11, if the frequency of the first line frequency clock signal is greater than the reference frequency, that is, the duration of the line CLK signal of each frame becomes shorter, the outputting the dummy line frequency clock signal to the gate driving circuit includes: and increasing the number of the false line frequency clock signals in each frame to eliminate the time difference of each frame of data caused by different frequencies, so that each frame has a specified time length. Referring to fig. 9, if the frequency of the second line frequency clock signal is less than the reference frequency, that is, the duration of the line CLK signal of each frame is longer, the outputting the dummy line frequency clock signal to the gate driving circuit includes: and reducing the number of the false line frequency clock signals in each frame to eliminate the time difference of each frame of data caused by different frequencies, so that each frame has a specified time length. Through the scheme of the embodiment of the invention, the occurrence of poor waterfall lines is avoided, and meanwhile, the duration of each adjusted frame is ensured to be the same as the duration of each frame required by the display device, so that the display effect is not influenced.
In some embodiments, the first line frequency clock signal has a frequency equal to a reference frequency of the line frequency clock signal, and the second line frequency clock signal has a frequency less than the reference frequency and greater than a lowest cut-off frequency of the line frequency clock signal.
In some of the above embodiments, the first line frequency clock signal has a frequency greater than the reference frequency and less than the highest cut-off frequency of the line frequency clock signal, and the second line frequency clock signal has a frequency equal to the reference frequency.
Of course, in some other embodiments of the present invention, the frequency of the line frequency clock signal is not limited to the two setting manners, for example, the frequency of the first line frequency clock signal may be greater than the reference frequency, and the frequency of the second line frequency clock signal may be smaller than the reference frequency, as long as the frequency of the first line frequency clock signal is greater than the frequency of the second line frequency clock signal.
In the related display method, when displaying each frame of data signal, the clock signal output to the gate driving circuit is not changed, and at this time, when receiving the data signal of each frame, the data signal of each frame can be directly input to the source driving circuit according to the predetermined frequency, but in the embodiment of the present invention, since the control signal of the backlight module needs to be detected and different clock signals are input to the gate driving circuit according to different control signals, after receiving the next frame of data signal, the data signal of the next frame cannot be input to the source driving circuit immediately, but before detecting the control signal of the backlight module, the received data signal of the next frame needs to be buffered, after determining the clock signal output to the gate driving circuit (whether to use the reference frequency F1 or to use the adjusted frequency FK), and after determining the output frequency of the data signal input to the source driving circuit according to the clock signal output to the gate driving circuit, the buffered data signal is input to the source driving circuit according to the determined output frequency. That is, when the line frequency clock signal and the data signal of the current frame are processed, the line frequency clock signal and the data signal of the next frame are buffered.
Referring to fig. 12, fig. 12 is a flowchart illustrating a display method according to another embodiment of the present invention, the display method is mainly used for explaining a method for adjusting a line frequency clock signal output to a gate driving circuit, the method includes:
step 121: storing the next frame data signal;
step 122: detecting a control signal of the backlight module;
step 123: judging whether the control signal is a low level signal, if so, entering step 124, otherwise, entering step 125;
step 124: outputting a first line frequency clock signal to the gate driving circuit at a frequency FK, FK being greater than a reference frequency F1;
step 125: outputting a second line frequency clock signal to the gate driving circuit according to a reference frequency F1;
step 126: judging whether waterfall line defect exists, if so, ending FK adjustment, otherwise, entering a step 127;
in the embodiment of the invention, whether the waterfall line defect exists can be judged by a manual identification method. Of course, the determination may also be performed in other manners, for example, an image acquisition device is used to acquire a display image of the display device, and whether the waterfall line defect exists is determined according to the acquired display image.
Step 127: adjusts the frequency FK and returns to step 121.
In the embodiment of the present invention, referring to fig. 13, the frequency FK may be adjusted in a step adjustment manner, where FK is based on a certain frequency between the reference frequency F1 and the cutoff frequency FN, and if F1 can reach FN by adjusting N times, FK is F1+ (FN-F1) N/N, and N is the number of times of adjustment.
The method for adjusting the frequency of the line frequency clock signal in the above embodiment may be completed in a test stage of the display device, and the adjusted frequency is obtained and stored, and when displaying normally, the stored frequency is directly used.
Referring to fig. 14, an embodiment of the present invention further provides a timing controller applied to a display device, where the display device includes a display panel, a backlight module, a gate driving circuit, and a source driving circuit, and the timing controller includes:
a detecting module 141, configured to detect a control signal of the backlight module;
a first output module 142, configured to output a first line frequency clock signal to the gate driving circuit if the control signal is detected to be a low level signal, and determine a first output frequency of outputting a data signal to the source driving circuit according to the first line frequency clock signal;
a second output module 143, configured to output a second line frequency clock signal to the gate driving circuit if the control signal is detected to be a high level signal, and determine a second output frequency of the data signal to the source driving circuit according to the second line frequency clock signal;
wherein the duration of the high level of the first line frequency clock signal is less than the duration of the high level of the second line frequency clock signal.
Optionally, the frequency of the first line frequency clock signal is equal to a reference frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is smaller than the reference frequency and greater than a lowest cut-off frequency of the line frequency clock signal; or
The frequency of the first line frequency clock signal is greater than the reference frequency and less than the highest cut-off frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is equal to the reference frequency.
Optionally, the timing controller further includes: a third output module, configured to output a false line frequency clock signal to the gate driver circuit at the end of each frame period; if the frequency of the first line frequency clock signal is greater than the reference frequency, increasing the number of the false line frequency clock signals in each frame so that each frame has a specified duration; if the frequency of the second line frequency clock signal is less than the reference frequency, the number of the false line frequency clock signals in each frame is reduced, so that each frame has a specified duration.
Optionally, the timing controller further includes:
and the buffer module is used for buffering the line frequency clock signal and the data signal of the next frame when the line frequency clock signal and the data signal of the current frame are processed.
Referring to fig. 15, fig. 15 is a schematic structural diagram of a timing controller (TCON IC) according to another embodiment of the present invention, including:
the detection module is used for detecting the input PWM signal of the backlight module;
a buffer module (Frame buffer) for buffering the received next Frame data signal;
a first output module, configured to output a first line frequency clock signal to the gate driving circuit based on a frequency FK if the control signal is detected to be a low level signal, and determine a first output frequency of outputting a data signal to the source driving circuit according to the first line frequency clock signal;
and the second output module is used for outputting a second line frequency clock signal to the gate driving circuit based on the reference frequency if the control signal is detected to be a high level signal, and determining a second output frequency for outputting a data signal to the source driving circuit according to the second line frequency clock signal.
Wherein, the external regulation FK means that the frequency FK in the first line frequency clock signal output module is regulated by an external regulation mode.
The embodiment of the invention also provides a display device which comprises the time schedule controller.
Optionally, the display device further includes a display panel, the display panel includes a data line and a semiconductor layer, the data line is in contact with the semiconductor layer in an overlapping manner, and an orthographic projection of the data line on the semiconductor layer completely falls on the semiconductor layer. Due to the characteristics of the display panel, the waterfall line defect is easy to occur, so the display method in the embodiment of the invention is particularly suitable for the display device with the display panel.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A display method is applied to a display device, the display device comprises a display panel, a backlight module, a grid drive circuit and a source drive circuit, and the method is characterized by comprising the following steps:
detecting a control signal of the backlight module;
if the control signal is detected to be a low level signal, outputting a first line frequency clock signal to the gate driving circuit, and determining a first output frequency of a data signal to the source driving circuit according to the first line frequency clock signal;
if the control signal is detected to be a high-level signal, outputting a second line frequency clock signal to the gate driving circuit, and determining a second output frequency of outputting a data signal to the source driving circuit according to the second line frequency clock signal;
wherein the duration of the high level of the first line frequency clock signal is less than the duration of the high level of the second line frequency clock signal.
2. The display method according to claim 1,
the frequency of the first line frequency clock signal is equal to the reference frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is smaller than the reference frequency and larger than the lowest cut-off frequency of the line frequency clock signal; or
The frequency of the first line frequency clock signal is greater than the reference frequency and less than the highest cut-off frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is equal to the reference frequency.
3. The display method as claimed in claim 2, further comprising:
outputting a false line frequency clock signal to the gate drive circuit at the end of each frame period;
if the frequency of the first line frequency clock signal is greater than the reference frequency, the outputting a dummy line frequency clock signal to the gate driving circuit includes:
increasing the number of the false line frequency clock signals in each frame to make each frame have a specified duration;
if the frequency of the second line frequency clock signal is less than the reference frequency, the outputting a dummy line frequency clock signal to the gate driving circuit includes:
reducing the number of false line frequency clock signals in each frame to have a specified duration for each frame.
4. The display method as claimed in claim 1, further comprising:
and when the line frequency clock signal and the data signal of the current frame are processed, caching the line frequency clock signal and the data signal of the next frame.
5. The utility model provides a time schedule controller, is applied to display device, display device includes display panel, backlight unit, grid drive circuit and source drive circuit, its characterized in that, time schedule controller includes:
the detection module is used for detecting a control signal of the backlight module;
the first output module is used for outputting a first line frequency clock signal to the gate driving circuit if the control signal is detected to be a low level signal, and determining a first output frequency of a data signal to the source driving circuit according to the first line frequency clock signal;
the second output module is used for outputting a second line frequency clock signal to the gate driving circuit if the control signal is detected to be a high level signal, and determining a second output frequency of the data signal to the source driving circuit according to the second line frequency clock signal;
wherein the duration of the high level of the first line frequency clock signal is less than the duration of the high level of the second line frequency clock signal.
6. The timing controller of claim 5,
the frequency of the first line frequency clock signal is equal to the reference frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is smaller than the reference frequency and larger than the lowest cut-off frequency of the line frequency clock signal; or
The frequency of the first line frequency clock signal is greater than the reference frequency and less than the highest cut-off frequency of the line frequency clock signal, and the frequency of the second line frequency clock signal is equal to the reference frequency.
7. The timing controller of claim 6, further comprising:
a third output module, configured to output a false line frequency clock signal to the gate driver circuit at the end of each frame period; if the frequency of the first line frequency clock signal is greater than the reference frequency, increasing the number of the false line frequency clock signals in each frame so that each frame has a specified duration; if the frequency of the second line frequency clock signal is less than the reference frequency, the number of the false line frequency clock signals in each frame is reduced, so that each frame has a specified duration.
8. The timing controller of claim 5, further comprising:
and the buffer module is used for buffering the line frequency clock signal and the data signal of the next frame when the line frequency clock signal and the data signal of the current frame are processed.
9. A display device comprising the timing controller according to any one of claims 5 to 8.
10. The display device according to claim 9, further comprising a display panel including a data line and a semiconductor layer, wherein the data line is in overlapping contact with the semiconductor layer, and an orthographic projection of the data line on the semiconductor layer falls entirely on the semiconductor layer.
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