CN112135072B

CN112135072B - Image sensor

Info

Publication number: CN112135072B
Application number: CN201911010510.6A
Authority: CN
Inventors: 李在原
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2019-06-25
Filing date: 2019-10-23
Publication date: 2023-05-19
Anticipated expiration: 2039-10-23
Also published as: KR20210000600A; US20200411583A1; US11011569B2; CN112135072A

Abstract

An image sensor includes a pixel group including: first to fourth photodiodes each configured to accumulate a photo-charge converted corresponding to an intensity of incident light; a floating diffusion region configured to receive and accumulate photo-charges; first to fourth transfer transistors coupled with the first to fourth photodiodes, respectively, and each configured to transfer photo-charges; and a common transfer transistor coupled between the first to fourth transfer transistors and the floating diffusion region and configured to transfer the photo-charges to the floating diffusion region.

Description

Image sensor

Technical Field

The technology and implementations disclosed in this patent document relate to an image sensor device and an imaging pixel structure.

Background

An image sensor is a device that captures light from an optical image or one or more objects using the properties of a photosensitive semiconductor element that converts incident light into an electrical signal. Recently, with the development of the automobile, medical, computer and communication industries, there is an increasing demand for high-performance image sensors in various devices such as smart phones, digital cameras, game machines, devices operating using the internet of things, robots, security cameras and medical micro-cameras.

One common type of image sensor is a Charge Coupled Device (CCD). Another common type of image sensing device is a Complementary Metal Oxide Semiconductor (CMOS) image sensor. The CCD image sensor is superior to the CMOS image sensor in noise characteristics and image quality. However, CMOS image sensors are now widely used due to certain advantages over CCD counterparts, including, for example, higher frame rates and shutter speeds. In addition, the CMOS image sensor and the signal processing circuit can be integrated into a single chip, so that miniaturization of the product is easy and very low power is consumed. Furthermore, using CMOS process technology may result in lower manufacturing costs. These characteristics of CMOS image sensors make these sensors more suitable for implementation in mobile devices.

Disclosure of Invention

Among other features and benefits, this patent document describes an image sensing device that includes a common transfer transistor coupled between a plurality of transfer transistors and corresponding floating diffusion regions to efficiently transfer photo-charges to the floating diffusion regions.

In an embodiment, an image sensor may include a pixel group including: first to fourth photodiodes each configured to accumulate a photo-charge converted corresponding to an intensity of incident light; a floating diffusion region configured to receive and accumulate photo-charges; first to fourth transfer transistors coupled with the first to fourth photodiodes, respectively, and each configured to transfer photo-charges; and a common transfer transistor coupled between the first to fourth transfer transistors and the floating diffusion region and configured to transfer the photo-charges to the floating diffusion region.

The floating diffusion region may be disposed at a central portion of the first to fourth photodiodes.

The common transfer transistor may have a ring shape to surround the floating diffusion region.

The common transfer transistor may include first to fourth sub transfer transistors disposed to surround the floating diffusion region.

The gate electrode of the common transfer transistor may be electrically isolated from the gate electrodes of the respective first to fourth transfer transistors.

The low-level voltage applied to the common transfer transistor may be different from the low-level voltages applied to the respective first to fourth transfer transistors.

The high-level voltage applied to the common transfer transistor may be different from the high-level voltage applied to each of the first to fourth transfer transistors.

In the reset operation of the first photodiode, the first transfer transistor may be turned on by a first transfer control signal of a first high level, and the common transfer transistor may be turned on by a common transfer control signal of a second high level higher than the first high level.

In the reset operation on the first photodiode, a potential difference of the first potential may be caused between the first transfer transistor having a potential lower than the first photodiode and the common transfer transistor having a potential higher than the floating diffusion region.

The first potential may be determined in consideration of a photo-charge accumulation capacity of the floating diffusion region.

In the reset operation on the first photodiode, the common transfer transistor may transfer the photo-charges existing between the floating diffusion region and the respective second to fourth transfer transistors to the floating diffusion region.

In the photo-charge accumulating operation on the first photodiode, the first transfer transistor may be turned off by a first transfer control signal of a second low level, and the common transfer transistor may be turned off by a common transfer control signal of a first low level higher than the second low level.

In the photo-charge accumulating operation on the first photodiode, a potential difference of the second potential may be caused between the first transfer transistor having a higher potential than the first photodiode and the common transfer transistor.

The second potential may be determined in consideration of a photo-charge accumulation capacity of the first photodiode.

In the photo-charge transfer operation to the first photodiode, the first transfer transistor may be turned on by a first transfer control signal of a first high level, and the common transfer transistor may be turned on by a common transfer control signal of a second high level higher than the first high level.

The shared pixels may include first to fourth unit pixels arranged in a 2×2 arrangement.

The first to fourth unit pixels may share a reset transistor, a driving transistor, and a selection transistor.

In an embodiment, an image sensor may include a shared pixel including: first to fourth transfer transistors configured to transfer the photo-charges accumulated in the first to fourth photodiodes, respectively; and a common transfer transistor coupled between the first to fourth transfer transistors and the floating diffusion region and configured to transfer the photo-charges to the floating diffusion region, wherein a low level voltage or a high level voltage applied to the first to fourth transfer transistors is different from the low level voltage or the high level voltage applied to the common transfer transistor.

In an embodiment, an image sensor may include: a pixel array including a shared pixel configured by the first to fourth unit pixels; and a row decoder configured to drive the pixel array, wherein the first unit pixel includes a first transfer transistor and a common transfer transistor coupled in series between a first photodiode accumulating photo-charges converted corresponding to an intensity of incident light and a floating diffusion region.

According to the embodiments disclosed in this document, by dividing the transfer transistor that performs the transfer of the photoelectric charge between the photodiode and the floating diffusion into two transfer transistors, and independently controlling the bias voltages to be applied to the respective transfer transistors, such advantages can be provided: when the floating diffusion region is reset, photo charges are accumulated and transferred to the floating diffusion region, pixel operation characteristics may be improved, noise of a pixel signal may be reduced and power consumption may be minimized.

Drawings

Fig. 1 shows an example of an image sensor based on an embodiment of the disclosed technology.

Fig. 2 illustrates an example of a pixel group including two or more pixels in the pixel array illustrated in fig. 1.

Fig. 3 shows an example layout of the pixel group shown in fig. 2.

Fig. 4 is a cross-sectional view taken along the first direction A-A' of fig. 3, showing an example of a pixel group.

Fig. 5 is an example timing diagram illustrating how the pixel groups shown in fig. 2 to 4 operate.

Fig. 6 shows a voltage distribution of the pixel group in the first period shown in fig. 5.

Fig. 7 illustrates a voltage distribution of the pixel group in the second period shown in fig. 5.

Fig. 8 shows a voltage distribution of the pixel group in the third period shown in fig. 5.

Fig. 9 illustrates another example of a pixel group shared by a set of unit pixels included in the pixel array illustrated in fig. 1.

Fig. 10 is another example layout of the pixel group shown in fig. 9.

The symbols of the various elements in the drawings

100: image sensor

110: pixel array

120: line decoder

130：CDS

140：ADC

150: output buffer

160: column decoder

170: timing controller

Detailed Description

Various embodiments of the present technology will be disclosed below with reference to the accompanying drawings. However, the description is not intended to limit the disclosure to the particular embodiments, but should be construed to include various modifications, equivalents, and/or alternatives to the embodiments according to the present disclosure.

By way of example and not limitation, the image sensor 100 may include a pixel array 110, a row decoder 120, a Correlated Double Sampler (CDS) 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column decoder 160, and a timing controller 170.

The pixel array 110 may include a plurality of unit pixels UP arranged in rows and columns, wherein two or more pixels are grouped together to form a pixel group. In some implementations of the disclosed technology, a plurality of unit pixels (e.g., unit pixels constituting the pixel group 200 of fig. 2) may convert an optical signal into an electrical signal based on the pixel group, wherein at least two unit pixels in the same pixel group share at least one common element such as a floating diffusion region. The pixel array 110 may receive control signals such as a row selection signal, a pixel reset signal, and a transfer signal from the row decoder 120, and may operate based on the control signals.

The row decoder 120 may be used to select one or more pixels of the pixel array 110 according to the timing provided by the timing controller 170. In some implementations, the row decoder 120 may select at least one row among the plurality of rows arranged in the pixel array 110 by generating a row selection signal. The row decoder 120 may sequentially enable the pixel reset signal and the transfer signal with respect to the pixels coupled to the selected at least one row. When the pixel reset signal and the transfer signal are enabled, the reference signal and the analog image signal generated from the respective pixels corresponding to the selected row are sequentially transferred to the correlated double sampler 130. Here, the reference signal and the image signal may be collectively referred to as a pixel signal.

The correlated double sampler 130 may sequentially sample and hold a reference signal and an image signal supplied from the pixel array 110 to each of a plurality of column lines. In other words, the correlated double sampler 130 may sample and hold voltage levels of the reference signal and the image signal corresponding to each column of the pixel array 110.

The correlated double sampler 130 may transmit the reference signal and the image signal of each column as correlated double sampling signals to the ADC 140 under the control of the timing controller 170.

CMOS image sensors can use Correlated Double Sampling (CDS) to remove unwanted offset values of pixels by sampling the pixel signal twice to remove the difference between the two samples. In one example, correlated Double Sampling (CDS) may remove an undesired offset value of a pixel by comparing a pixel output voltage obtained before an optical signal is incident on the pixel and after the optical signal is incident on the pixel so that only the pixel output voltage based on the incident light may be measured.

The ADC 140 may convert the analog pixel signal, from which the offset value is removed by the correlated double sampling by the correlated double sampler 130, into a digital signal for each column. Examples of ADC 140 may include a ramp comparison ADC in which an analog pixel signal is compared to a ramp signal that ramps up or down and a timer counts until the voltage of the ramp signal matches the analog pixel signal. In one example, the analog pixel signal from which the offset value is removed by correlated double sampling is compared with a ramp signal supplied from the timing controller 170 to generate digital image data from which noise (e.g., reset noise specific to each pixel) corresponding to each column is removed.

The ADC 140 may include a plurality of column counters corresponding to columns of the pixel array 110, respectively, and the offset-removed signals corresponding to the columns, respectively, may be converted into digital signals using the column counters. In some implementations of the disclosed technology, the ADC 140 may include one global counter, and the de-offset signals corresponding to the columns may be converted to digital signals using a global code provided from the global counter.

The output buffer 150 may capture and output image data of each column unit supplied from the ADC 140. The output buffer 150 may temporarily store the image data output from the ADC 140 according to the timing provided by the timing controller 170. The output buffer 150 may operate as an interface that compensates for a transmission (or processing) speed difference between the image sensor 100 and another device connected thereto.

The column decoder 160 may select a column of the output buffer 150 according to the timing provided by the timing controller 170, and image data temporarily stored in the selected column of the output buffer 150 may be sequentially output. In one example, upon receiving an address signal from the timing controller 170, the column decoder 160 may select a column of the output buffer 150 by generating a column selection signal based on the address signal to output image data from the selected column of the output buffer 150 as the output signal SO.

The timing controller 170 may control the row decoder 120, the ADC 140, the output buffer 150, and the column decoder 160.

The timing controller 170 may provide clock signals, control signals for timing control, and address signals for selecting a row or a column, required for the operation of the respective components of the image sensor 100 to the row decoder 120, the column decoder 160, the ADC 140, and the output buffer 150. In some implementations of the disclosed technology, the timing controller 170 may include logic control circuitry, phase Locked Loop (PLL) circuitry, timing control circuitry, and communication interface circuitry.

Fig. 2 illustrates an example of a pixel group including two or more unit pixels in the pixel array illustrated in fig. 1.

As shown in fig. 2, the pixel group 200 may include four unit pixels. That is, the pixel group 200 may include four unit pixels (e.g., four photodiodes PD1 to PD4 and four transfer transistors TX1 to TX4, each including one photodiode and one transfer transistor), and the remaining elements are configured to be shared by the four unit pixels (e.g., four photodiodes PD1 to PD4 and four transfer transistors TX1 to TX 4).

In an implementation, the pixel group 200 may include first to fourth photodiodes PD1 to PD4, first to fourth transfer transistors TX1 to TX4, a common transfer transistor TXc, a floating diffusion region (floating diffusion region) FD, a reset transistor RX, a driving transistor DX, and a selection transistor SX. In the context of this patent document, a transfer transistor may refer to a transistor or other component that may be used to transfer charge accumulated on a photodiode to a floating diffusion region.

Each of the first to fourth photodiodes PD1 to PD4 may generate a photo-charge corresponding to an amount of incident light based on the incident light. Each of the first to fourth photodiodes PD1 to PD4 is an example of a photoelectric conversion element. In various embodiments of the disclosed technology, the photoelectric conversion element may include a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

Each of the first to fourth transfer transistors TX1 to TX4 may be coupled between each of the first to fourth photodiodes PD1 to PD4 and the common transfer transistor TXc. Each of the first to fourth transfer transistors TX1 to TX4 may be turned on or off in response to the first to fourth transfer control signals TG1 to TG4 corresponding thereto, respectively, and the turned-on transfer transistor may transfer the photo-charges accumulated in the corresponding photodiode to the common transfer transistor TXc.

The common transfer transistor TXc may be coupled between the respective first to fourth transfer transistors TX1 to TX4 and the floating diffusion FD. The common transfer transistor TXc may be turned on or off in response to the common transfer control signal TGc, and the turned-on common transfer transistor TXc may transfer the photo-charges transferred from each of the first to fourth transfer transistors TX1 to TX4 to the floating diffusion FD.

The floating diffusion FD may accumulate the photo-charges of each of the first to fourth photodiodes PD1 to PD4 transferred through the common transfer transistor TXc. The floating diffusion FD may be formed on the junction capacitor.

The reset transistor RX may be coupled between the power supply voltage VDD and the floating diffusion FD, and may reset the voltage level of the floating diffusion FD to the power supply voltage VDD in response to the reset control signal RG.

The driving transistor DX may amplify the voltage at the floating diffusion FD receiving the photo-charges generated by the first to fourth photodiodes PD1 to PD4, and may transmit the amplified voltage to the selection transistor SX; thus, for example, the drive transistor DX may operate as a source follower transistor.

The selection transistor SX may select a pixel group to be read based on a row. The selection transistor SX may be turned on in response to the selection control signal SEL, and a signal corresponding to the charge at the floating diffusion FD supplied to the drain of the selection transistor SX (i.e., the source of the source follower transistor) may be output as the output voltage Vout.

In some implementations, the output voltage Vout of the selection transistor SX may correspond to the reference signal (i.e., a signal corresponding to the floating diffusion FD in the reset state) or the image signal (i.e., a voltage at the floating diffusion FD in a state where photo-charges transferred from the photodiodes PD1 to PD4 are accumulated) described above with reference to fig. 1.

Fig. 3 shows an example layout of the pixel group shown in fig. 2.

Referring to fig. 3, a pixel group 300 may include four unit pixels (e.g., a photodiode and a transfer transistor).

Although the four unit pixels (e.g., four photodiodes and four transfer transistors) shown in fig. 3 are arranged in the form of a 2×2 matrix, they may be arranged in different manners such as a 1×4 or 4×1 matrix.

The floating diffusion FD may be disposed at the center between the four unit pixels, and the common transfer transistor TXc may be disposed around the periphery of the floating diffusion FD. For example, the common pass transistor TXc may have a ring shape or any polygonal shape. Between each side of the common transfer transistor TXc and each of the photodiodes PD1 to PD4, each of the transfer transistors TX1 to TX4 may be disposed to extend along each side of the common transfer transistor TXc.

At least a portion of each of the photodiodes PD1 to PD4 may be exposed to increase light receiving efficiency, and other elements RX, DX, and SX not shown in fig. 3 may be disposed in upper, lower, left, and/or right peripheral regions (not shown) of the photodiodes PD1 to PD 4.

By way of example and not limitation, the respective photodiodes PD1 to PD4 and the respective transfer transistors TX1 to TX4 or the common transfer transistor TXc and the floating diffusion FD may at least partially overlap each other.

The three directions A-A ', B-B ', and C-C ' shown in fig. 3 may indicate directions extending from the first photodiode PD1 to the second to fourth photodiodes PD2 to PD4 through the floating diffusion FD, respectively. Since the cross sections corresponding to the respective directions A-A ', B-B', and C-C 'have substantially the same structure, a cross section along the first direction A-A' will be described with reference to fig. 4.

Although the arrangement of the respective transfer transistors TX1 to TX4 and TXc will be described with reference to fig. 3 and 4 for convenience of explanation, the respective transfer transistors TX1 to TX4 and TXc may indicate gates of the respective transfer transistors TX1 to TX4 and TXc.

Fig. 4 is a cross-sectional view 400 taken along the first direction A-A' of fig. 3, illustrating an example of a pixel group.

The cross-sectional view 400 of the pixel group schematically shows a cross-sectional structure taken along the first direction A-A' in the pixel group shown in fig. 3.

In the case where the semiconductor substrate 410 may have front and rear sides facing away from each other, the region shown in fig. 4 may indicate the front side. The pixel group may have a rear side illumination type structure that receives incident light through a rear side, and may have a front side illumination type structure that receives incident light through a front side.

The semiconductor substrate 410 may be formed of a p-type epitaxial layer, and the first and second photodiodes PD1 and PD2 and the floating diffusion FD are formed of an n-type impurity layer doped into the semiconductor substrate 410.

Over the region between the first photodiode PD1 and the floating diffusion FD, respective gates of the first transfer transistor TX1 and the common transfer transistor TXc may be disposed in series. The respective gates of the first and common transmission transistors TX1 and TXc may include gate electrodes receiving the first and common transmission control signals TG1 and TGc and a gate dielectric layer electrically isolating the respective gate electrodes from the semiconductor substrate 410. The gate isolation layer 420 may be disposed between the respective gate electrodes of the first and common pass transistors TX1 and TXc, and thus, the respective gate electrodes of the first and common pass transistors TX1 and TXc may be electrically and physically isolated from each other. By way of example and not limitation, the gate electrode may comprise polysilicon and the gate dielectric layer and gate spacer 420 may comprise an oxide.

The first transfer transistor TX1 and the common transfer transistor TXc may be turned on by a first transfer control signal TG1 and a common transfer control signal TGc, respectively, and the photo-charges accumulated in the first photodiode PD1 may be transferred to the floating diffusion FD through channels under the respective gate dielectric layers.

Over the region between the second photodiode PD2 and the floating diffusion FD, respective gates of the second transfer transistor TX2 and the common transfer transistor TXc may be disposed in series. The respective gates of the second and common pass transistors TX2 and TXc may include gate electrodes receiving the second and common pass control signals TG2 and TGc and a gate dielectric layer electrically isolating the respective gate electrodes from the semiconductor substrate 410. The gate isolation layer 430 may be disposed between the respective gate electrodes of the second and common pass transistors TX2 and TXc, and the respective gate electrodes of the second and common pass transistors TX2 and TXc may be electrically and physically isolated from each other. By way of example and not limitation, the gate electrode may comprise polysilicon and the gate dielectric layer and gate spacer 430 may comprise an oxide.

The second transfer transistor TX2 and the common transfer transistor TXc may be turned on by a second transfer control signal TG2 and a common transfer control signal TGc, respectively, and the photo-charges accumulated in the second photodiode PD2 may be transferred to the floating diffusion FD through channels under the respective gate dielectric layers.

Fig. 5 is an example timing diagram illustrating how the pixel groups shown in fig. 2 to 4 operate. Fig. 6 to 8 are diagrams showing example representations of voltage distribution of the pixel group in the period shown in fig. 5.

Referring to fig. 5, control signals RG, TG1, TG2, and TGc are applied to the pixel group 200 to control the pixel group 200 described above with reference to fig. 2 to 4. Although control signals and timings for the reset, photo-charge accumulation, and photo-charge transfer operations of the first photodiode PD1 and the second photodiode PD2 are shown in fig. 5 for convenience of explanation, the reset, photo-charge accumulation, and photo-charge transfer operations of the third photodiode PD3 and the fourth photodiode PD4 may be sequentially performed in substantially the same manner as the first photodiode PD1 and the second photodiode PD 2.

Each of the control signals RG, TG1, TG2, and TGc may have a voltage level corresponding to any one of four logic levels H1, H2, L1, and L2. The first high level H1 is lower than the second high level H2, the first low level L1 is higher than the second low level L2, and the first high level H1 is higher than the first low level L1. Each of the transistors RX, TX1, TX2, and TXc may be turned on in a case where a signal of a high level H1 or H2 is applied to the corresponding gate, and may be turned off in a case where a signal of a low level L1 or L2 is applied to the corresponding gate.

The reset control signal RG is a signal that swings between a first high level H1 and a first low level L1. The first and second transmission control signals TG1 and TG2 are signals that swing between the first high level H1 and the second low level L2. The common transmission control signal TGc is a signal that swings between the second high level H2 and the first low level L1.

First, in the first period t1 to t2, each of the reset control signal RG, the first transmission control signal TG1, and the common transmission control signal TGc may have a high level, and the second transmission control signal TG2 may have a low level. Due to this fact, each of the reset transistor RX, the first transfer transistor TX1, and the common transfer transistor TXc may be turned on, and the second transfer transistor TX2 may be turned off.

Fig. 6 shows the voltage distribution of the pixel group 200 in the first period t1 to t 2. In fig. 6, the vertical axis may indicate voltage levels at various regions. If the individual transistors are turned off, the transistors may form a voltage difference barrier, blocking charge transfer between the source and drain. If the individual transistors are turned on, charge may be transferred between the source and drain. The voltages at the first photodiode PD1 and the second photodiode PD2 may be higher than the voltage level at the floating diffusion FD to have a predetermined voltage difference slope. By way of example, and not limitation, the voltage levels at the first photodiode PD1 and the second photodiode PD2 are the same as each other.

When each of the reset transistor RX, the first transfer transistor TX1, and the common transfer transistor TXc is turned on, photo charges existing in the first photodiode PD1, the first transfer transistor TX1, and the common transfer transistor TXc may be transferred to the floating diffusion FD, and the photo charges transferred to the floating diffusion FD may be discharged to the power supply voltage VDD.

Since the on-voltages applied to the first transfer transistor TX1 and the common transfer transistor TXc have the first high level H1 and the second high level H2, respectively, a first voltage difference Δv1 may be caused between the first transfer transistor TX1 having a voltage level lower than the first photodiode PD1 and the common transfer transistor TXc having a voltage higher than the floating diffusion FD. The first voltage difference Δv1 can be experimentally determined in consideration of the transfer efficiency of the photo-charges from the first photodiode PD1 to the floating diffusion region FD and preventing the overflow of the photo-charges transferred to the floating diffusion region FD (or the photo-charge accumulation capacity of the floating diffusion region FD).

The first transfer transistor TX1 and the common transfer transistor TXc may provide a voltage difference slope that ramps down from the first photodiode PD1 to the floating diffusion FD. Accordingly, due to such a voltage difference slope, photo charges existing in the first photodiode PD1, the first transfer transistor TX1, and the common transfer transistor TXc can be effectively transferred to the floating diffusion FD.

In addition, when the common transfer transistor TXc disposed around the periphery of the floating diffusion FD is turned on, in the pixel group structure, the region including the photo-charges that can be a noise source (the region between FD and TX2 to TX 4) can be reset together without resetting the other photodiodes PD2 to PD4, thereby minimizing the potential noise source in the pixel signal.

Referring again to fig. 5, in the second period t2 to t3, each of the reset control signal RG, the first and second transmission control signals TG1 and TG2, and the common transmission control signal TGc may have a low level, and thus each of the reset transistor RX, the first and second transmission transistors TX1 and TX2, and the common transmission transistor TXc may be turned off.

Fig. 7 shows the voltage distribution of the pixel group 200 in the second period t2 to t 3. In a state in which each of the reset transistor RX, the first and second transfer transistors TX1 and TX2, and the common transfer transistor TXc is turned off, an electric signal corresponding to a voltage level at the floating diffusion FD may be output through the driving transistor DX and the selection transistor SX. The electrical signal may correspond to the reference signal described above with reference to fig. 1.

In addition, in a state where each of the reset transistor RX, the first and second transfer transistors TX1 and TX2, and the common transfer transistor TXc is turned off, a photo-charge converted corresponding to the intensity of incident light may be accumulated in each of the first and second photodiodes PD1 and PD 2.

Since the off voltages applied to the first and common transfer transistors TX1 and TXc have the second low level L2 and the first low level L1, respectively, a voltage difference of the second voltage difference Δv2 may be induced between the first and common transfer transistors TX1 and TXc having a voltage difference higher than that of the first photodiode PD 1. The second voltage difference Δv2 can be experimentally determined in consideration of prevention of overflow of photo-charges from the photodiodes PD1 to PD4 (or photo-charge accumulation capacity of the photodiodes PD1 to PD 4) and power consumption optimization.

Due to such a voltage difference, the photo-charges accumulated in each of the first photodiode PD1 and the second photodiode PD2 can be prevented from overflowing to surrounding elements, and the sensitivity of each of the first photodiode PD1 and the second photodiode PD2 can be further increased.

Referring again to fig. 5, in the third period t3 to t4, each of the first and common transmission control signals TG1 and TGc may have a high level, and each of the reset control signal RG and the second transmission control signal TG2 may have a low level. Accordingly, each of the first and common transfer transistors TX1 and TXc may be turned on, and each of the reset and second transfer transistors RX and TX2 may be turned off.

Fig. 8 shows the voltage difference distribution of the pixel group 200 in the third period t3 to t 4.

When each of the first transfer transistor TX1 and the common transfer transistor TXc is turned on and each of the reset transistor RX and the second transfer transistor TX2 is turned off, the photo-charges accumulated in the first photodiode PD1 may be transferred to and accumulated in the floating diffusion FD.

Since the on-voltages applied to the first and common pass transistors TX1 and TXc have the first and second high levels H1 and H2, respectively, a first voltage difference Δv1 may be induced between the first and common pass transistors TX1 and TXc in the same manner as in fig. 6.

Accordingly, the first transfer transistor TX1 and the common transfer transistor TXc may provide a voltage slope that ramps down from the first photodiode PD1 to the floating diffusion FD. Accordingly, due to such a voltage slope, the photo-charges accumulated in the first photodiode PD1 can be effectively transferred to the floating diffusion FD.

Referring again to fig. 5, in the fourth period t4 to t5, each of the reset control signal RG, the first and second transmission control signals TG1 and TG2, and the common transmission control signal TGc may have a low level. Accordingly, each of the reset transistor RX, the first and second transfer transistors TX1 and TX2, and the common transfer transistor TXc may be turned off. In a state where each of the reset transistor RX, the first and second transfer transistors TX1 and TX2, and the common transfer transistor TXc is turned off, an electric signal corresponding to a voltage at the floating diffusion FD may be output through the driving transistor DX and the selection transistor SX (readout of fig. 8). The electrical signal may correspond to the image signal described above with reference to fig. 1.

Thereafter, in the fifth to seventh periods t5 to t6 to t7 to t8, reset, photo-charge accumulation, and photo-charge transfer operations may be performed for the second photodiode PD 2. Since the detailed operations and the voltage difference distribution in the fifth to seventh periods t5 to t6 to t7 to t8 correspond to the reset, photo-charge accumulation, and photo-charge transfer operations of the first photodiode PD1 described above with reference to the first to third periods t1 to t2 to t3 to t4, repetitive descriptions thereof will be omitted. For example, the voltage difference distribution in the fifth to seventh periods t5 to t6 to t7 to t8 may be bilaterally symmetrical with respect to the voltage difference distribution in the first to third periods t1 to t2 to t3 to t4 described above with reference to fig. 6 to 8.

In addition, in the following eighth period t8, an image signal corresponding to a voltage difference of the floating diffusion FD receiving the photo-charge accumulated by the second photodiode PD2 may be output through the driving transistor DX and the selection transistor SX.

Further, after the eighth period t8, reset, photo-charge accumulation, photo-charge transfer, and readout operations of the third photodiode PD3 and the fourth photodiode PD4 may be sequentially performed.

As described above with reference to fig. 5, in the period for transfer of the photo-charges to the floating diffusion FD (e.g., reset or photo-charge transfer operation), by applying the second high level H2 higher than the first high level H1 only to the common transfer transistor TXc close to the floating diffusion FD, an appropriate voltage slope and power consumption reduction in the direction of the floating diffusion FD (e.g., lower first high level H1 applied to the first transfer transistor TX 1) can be achieved.

Further, in a period in which the transfer of the photo-charges between the photodiodes PD1 to PD4 and the floating diffusion FD is blocked (for example, photo-charge accumulating operation), by applying the second low level L2 lower than the first low level L1 only to the transfer transistors TX1 to TX4 close to the photodiodes PD1 to PD4, the photo-charges accumulated in the photodiodes PD1 to PD4 can be prevented from overflowing, and a reduction in power consumption (the higher first low level L1 is applied to the common transfer transistor TXc) can be achieved.

If the transfer transistor is a single transistor, the single transistor needs to swing between the second low level L2 and the second high level H2 in order to float an appropriate voltage slope in the direction of the diffusion FD and prevent an overflow phenomenon of photo charges. However, in the case of implementing the dual transfer transistors as in the embodiment of the disclosed technology, even if the respective transfer transistors TX1 to TX4 and TXc have relatively narrow swing widths L2 to H1 or L1 to H2, an appropriate voltage slope in the direction of the floating diffusion FD and prevention of the overflow phenomenon of photo charges can be implemented in the same manner. In this way, the burden of hot carrier infection can be reduced and the reliability of pixel operation can be improved.

In the pixel according to the embodiment of the present disclosure, by dividing the transfer transistor performing the transfer of the photo-charges between the photodiode and the floating diffusion region into two transfer transistors and by independently controlling the bias voltages to be applied to the respective transfer transistors, when resetting the floating diffusion region, the photo-charges are accumulated and transferred to the floating diffusion region, the pixel operation characteristics can be improved, noise of the pixel signal can be reduced, and power consumption can be minimized.

Fig. 9 shows another example of a pixel group shared by the pixel sets included in the pixel array shown in fig. 1.

Referring to fig. 9, the pixel group 900 may include four unit pixels UP shown in fig. 1. That is, the pixel group 900 may include four unit pixels UP sharing a common element. Accordingly, the respective four unit pixels UP have independent photodiodes PD1 to PD4, transfer transistors TX1 to TX4, and sub transfer transistors TXs1 to TXs4, but the remaining elements are configured to be shared by the four unit pixels UP.

By way of example and not limitation, the pixel group 900 may include first to fourth photodiodes PD1 to PD4, first to fourth transfer transistors TX1 to TX4, first to fourth sub transfer transistors TXs to TXs4, a floating diffusion FD, a reset transistor RX, a driving transistor DX, and a selection transistor SX.

Since components except for the first to fourth sub-transmission transistors TXS to TXS4 are substantially the same as corresponding components of fig. 2, detailed descriptions thereof will be omitted.

The respective first to fourth sub transfer transistors TXS1 to TXS4 may be coupled in series between the respective first to fourth transfer transistors TX1 to TX4 and the floating diffusion FD. The first to fourth sub-transmission transistors TXS1 to TXS4 may be turned on or off in response to the first to fourth sub-transmission control signals TGS1 to TGS4, respectively, and the respective turned-on first to fourth sub-transmission transistors TXS1 to TXS4 may transmit the photo-charges transmitted from the respective first to fourth transmission transistors TX1 to TX4 to the floating diffusion FD.

Fig. 10 is another example layout of the pixel group shown in fig. 9.

Referring to fig. 10, a pixel group 1000 includes four unit pixels UP configuring the pixel group 900 shown in fig. 9.

Although the four unit pixels (e.g., four photodiodes and four transfer transistors) shown in fig. 10 are arranged in the form of a 2×2 matrix, they may be arranged in different manners such as a 1×4 or 4×1 matrix.

The floating diffusion FD may be disposed at the center between the four unit pixels, and the first to fourth sub-transfer transistors TXS1 to TXS4 may be disposed around the periphery of the floating diffusion FD. When compared with the common transfer transistor TXc of fig. 3, the common transfer transistor TXc has a shape in which one element physically surrounds the periphery of the floating diffusion FD, and the first to fourth sub transfer transistors TXS1 to TXS4 may be provided in a shape in which four independent elements physically separated from each other surround the periphery of the floating diffusion FD.

The first to fourth sub transmission transistors TXS1 to TXS4 may correspond to another embodiment of the common transmission transistor TXc and may be collectively referred to as a common transmission transistor.

Between the respective first to fourth sub transfer transistors TXS1 to TXS4 and the respective photodiodes PD1 to PD4, the respective transfer transistors TX1 to TX4 may be disposed to extend along the respective first to fourth sub transfer transistors TXS1 to TXS 4.

At least a portion of each of the photodiodes PD1 to PD4 may be exposed to increase light receiving efficiency, and other elements RX, DX, and SX not shown in fig. 10 may be disposed in upper, lower, left, and/or right peripheral regions (not shown) of the photodiodes PD1 to PD 4.

By way of example and not limitation, the respective photodiodes PD1 to PD4 and the respective transfer transistors TX1 to TX4 or the respective sub-transfer transistors TXs1 to TXs4 and the floating diffusion FD may at least partially overlap each other.

Three directions A-A ', B-B ' and C-C ' are shown in fig. 10. The respective directions A-A ', B-B ', and C-C ' indicate directions extending from the first photodiode PD1 to the second to fourth photodiodes PD2 to PD4 through the floating diffusion FD, respectively. Since cross sections corresponding to the respective directions A-A ', B-B', and C-C 'are substantially the same as the cross section along the first direction A-A' described above with reference to fig. 4, except that the common transmission transistor TXc is replaced by the first and second sub transmission transistors TXS1 and TXS2 at the corresponding positions, detailed description thereof will be omitted.

The respective first to fourth sub transmission transistors TXS1 to TXS4 receive the same signals as the above-described common transmission control signal TGc as the first to fourth sub transmission control signals TGS1 to TGS4 and may operate at the same timing as the common transmission transistor TXc.

In another embodiment of the disclosed technology, the entire waveform of each of the first to fourth sub-transmission control signals TGS1 to TGS4 may be the same as the waveform of the common transmission control signal TGc, but in a period (e.g., the third period t3 to t4 of fig. 5) in which the photo-charges accumulated in a specific photodiode (e.g., PD 1) are transmitted to the floating diffusion FD, only the sub-transmission control signal (e.g., TGS 1) corresponding to the specific photodiode PD1 may have a high level, and the sub-transmission control signals (e.g., TGS2 to TGS 4) corresponding to the remaining photodiodes PD2 to PD4 may have a low level. In this way, it is possible to prevent the photo-charges transferred from the specific photodiode PD1 to the floating diffusion FD from diffusing to another region, and to prevent the photo-charges existing in the other region from being transferred to the floating diffusion FD.

An image sensing device includes a common transfer transistor coupled between four transfer transistors and corresponding floating diffusion regions to efficiently transfer photo-charges to the floating diffusion regions.

Although 4-pixel groups are described as an example in the present specification, the scope of the present disclosure is not limited thereto, and substantially the same technical idea may be applied even to a case where a selectable number of unit pixels configure pixel groups or a case where no pixel group exists.

Cross Reference to Related Applications

This patent document claims priority and equity of korean patent application No.10-2019-0075939 filed in the korean intellectual property office at 25 th of 2019, which is incorporated herein by reference in its entirety.

Claims

1. An image sensor, the image sensor comprising:

a pixel group, the pixel group comprising:

a plurality of photodiodes configured to generate photo-charges in response to light incident on the plurality of photodiodes;

a floating diffusion region configured to receive and accumulate photo-charges generated by the plurality of photodiodes;

a plurality of transfer transistors respectively coupled to the plurality of photodiodes, each of the plurality of transfer transistors configured to transfer photo-charges generated by a corresponding photodiode; and

a common transfer transistor coupled between the plurality of transfer transistors and the floating diffusion region and configured to transfer the photo-charges generated by the plurality of photodiodes to the floating diffusion region,

wherein, to allow a reset operation on one of the plurality of photodiodes, one of the plurality of transfer transistors corresponding to the one of the plurality of photodiodes is configured to receive a first transfer control signal of a first logic high level, and the common transfer transistor is configured to receive a common transfer control signal of a second logic high level, and wherein the second logic high level is higher than the first logic high level, and

Wherein, in order to allow a reset operation on the one of the plurality of photodiodes, the common transfer transistor is configured to transfer a photo-charge existing between the floating diffusion region and transfer transistors other than the one of the plurality of transfer transistors corresponding to the one of the plurality of photodiodes to the floating diffusion region.

2. The image sensor of claim 1, wherein the floating diffusion region is disposed at a central portion of the plurality of photodiodes.

3. The image sensor of claim 1, wherein the common pass transistor is ring-shaped and surrounds the floating diffusion region.

4. The image sensor of claim 1, wherein the common transfer transistor comprises a plurality of sub-transfer transistors disposed around the floating diffusion region.

5. The image sensor of claim 1, wherein a gate electrode of the common pass transistor is electrically isolated from a gate electrode of each of the pass transistors.

6. The image sensor of claim 1, wherein the common pass transistor is configured to receive a first logic low level voltage and the plurality of pass transistors are configured to receive a second logic low level voltage, and wherein the first logic low level voltage is different from the second logic low level voltage.

7. The image sensor of claim 1, wherein the common pass transistor is configured to receive a first logic high level voltage and the plurality of pass transistors are configured to receive a second logic high level voltage, and wherein the first logic high level voltage is different from the second logic high level voltage.

8. The image sensor of claim 1, wherein to allow a reset operation on the one of the plurality of photodiodes, the one of the plurality of transfer transistors corresponding to the one of the plurality of photodiodes is configured to have a first voltage lower than the one of the plurality of photodiodes, and the common transfer transistor is configured to have a second voltage higher than the floating diffusion region, and wherein the first voltage is different from the second voltage.

9. The image sensor of claim 8, wherein a voltage difference between the first voltage and the second voltage is determined based on a photo-charge accumulation capacity of the floating diffusion region.

10. The image sensor of claim 1, wherein to allow a photo-charge accumulation operation on one of the plurality of photodiodes, one of the plurality of transfer transistors corresponding to the one of the plurality of photodiodes is configured to receive a first transfer control signal of a second logic low level, and the common transfer transistor is configured to receive a common transfer control signal of a first logic low level higher than the second logic low level.

11. The image sensor according to claim 10, wherein in the photo-charge accumulating operation for the one of the plurality of photodiodes, a voltage at the one of the plurality of transfer transistors corresponding to the one of the plurality of photodiodes is different from a voltage at the common transfer transistor higher than the one of the plurality of photodiodes.

12. The image sensor of claim 11, wherein a voltage difference between the one of the plurality of transfer transistors corresponding to the one of the plurality of photodiodes and the common transfer transistor is determined based on a photo-charge accumulation capacity of the one of the plurality of photodiodes.

13. The image sensor of claim 1, wherein to allow a photo-charge transfer operation to one of the plurality of photodiodes, one of the plurality of transfer transistors corresponding to the one of the plurality of photodiodes is configured to receive a first transfer control signal of a first logic high level, and the common transfer transistor is configured to receive a common transfer control signal of a second logic high level higher than the first logic high level.

14. The image sensor of claim 1, wherein the pixel group includes first to fourth unit pixels arranged in a 2 x 2 matrix, and wherein each unit pixel includes one of the plurality of photodiodes and one of the plurality of transfer transistors.

15. The image sensor of claim 14, wherein the first to fourth unit pixels share a reset transistor, a driving transistor, and a selection transistor.

16. An image sensor, the image sensor comprising:

a pixel group, the pixel group comprising:

First to fourth photodiodes configured to generate photo-charges in response to incident light;

first to fourth transfer transistors configured to transfer photo-charges accumulated in the first to fourth photodiodes, respectively; and

a common transfer transistor coupled between the first to fourth transfer transistors and the floating diffusion region and configured to transfer a photo-charge to the floating diffusion region,

wherein a logic low level voltage or a logic high level voltage applied to the first to fourth transfer transistors to turn on or off the first to fourth transfer transistors is different from a logic low level voltage or a logic high level voltage applied to the common transfer transistor to turn on or off the common transfer transistor,

wherein, to allow a reset operation on one of the first to fourth photodiodes, one of the first to fourth transfer transistors corresponding to the one of the first to fourth photodiodes is configured to receive a first transfer control signal of a first logic high level, and the common transfer transistor is configured to receive a common transfer control signal of a second logic high level, and wherein the second logic high level is higher than the first logic high level, and

Wherein, in order to allow a reset operation of the one of the first to fourth photodiodes, the common transfer transistor is configured to transfer a photo-charge existing between the floating diffusion region and a transfer transistor other than the one of the first to fourth transfer transistors corresponding to the one of the first to fourth photodiodes to the floating diffusion region.

17. The image sensor of claim 16, wherein to allow a photo-charge accumulation operation on the one of the first to fourth photodiodes, the one of the first to fourth transfer transistors corresponding to the one of the first to fourth photodiodes is configured to receive a first transfer control signal of a second logic low level, and the common transfer transistor is configured to receive a common transfer control signal of a first logic low level higher than the second logic low level.

18. An image sensor, the image sensor comprising:

a pixel array including a pixel group including first to fourth unit pixels; and

a row decoder configured to drive the pixel array,

wherein the first unit pixel includes a first transfer transistor and a common transfer transistor coupled between a first photodiode configured to accumulate photo-charges corresponding to an intensity of incident light and a floating diffusion region,

wherein, to allow a reset operation on the first photodiode, the first transfer transistor is configured to receive a first transfer control signal of a first logic high level, and the common transfer transistor is configured to receive a common transfer control signal of a second logic high level, and wherein the second logic high level is higher than the first logic high level, and

wherein, in order to allow the reset operation of the first photodiode, the common transfer transistor is configured to transfer a photo-charge existing between the floating diffusion region and transfer transistors corresponding to second to fourth photodiodes included in second to fourth unit pixels to the floating diffusion region.