CN112131161B

CN112131161B - Hardware analysis method for Binary protocol data stream

Info

Publication number: CN112131161B
Application number: CN202010961829.3A
Authority: CN
Inventors: 滕达; 温士魁
Original assignee: Shandong Industry Research Institute Of Integrated Circuit Industry Co ltd
Current assignee: Shandong Industry Research Institute Of Integrated Circuit Industry Co ltd
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2022-03-29
Anticipated expiration: 2040-09-14
Also published as: CN112131161A

Abstract

The invention relates to a hardware analysis method of Binary protocol data stream, which comprises the following steps: downloading a decoding program into an FPGA (field programmable gate array) or solidifying the decoding program into an ASIC (application specific integrated circuit), sending a transaction data stream by a deep traffic exchange server, inputting the transaction data stream into the FPGA or the ASIC through a network interface or a PCI-E (peripheral component interconnect-express) interface, caching the transaction data stream in an input interface cache, adjusting the length of each data packet through a packet reforming module, then entering a decoding module, stripping and decoding the data by the decoding module according to the steps to obtain decoded data, sending the decoded data to an output interface cache, and outputting the decoded data to a client CPU (central processing unit) through the network interface or the PCI-E interface to obtain the decoded data. The invention greatly improves the decoding speed by decoding through special hardware, can reduce the burden of a computer and has greater economic benefit.

Description

Hardware analysis method for Binary protocol data stream

Technical Field

The invention relates to a method for analyzing Binary protocol data streams, in particular to a method for analyzing hardware.

Background

With the development of economy in China, the stock industry makes great progress, and a Shenzhen stock exchange (hereinafter referred to as a 'deep crossing exchange') is one of main trading places in China, and generates a large amount of trading data every day. The transaction data are formatted into a functional flow described by a computer language through a Binary protocol (Binary protocol), and the format is exchanged uniformly on each service functional interface, so that the transaction data can be transmitted by referring to engineering technical standard Binary transaction data interface specification (Ver1.13) of Shenzhen stock exchange and further processed by a computer.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the Binary protocol data stream analysis method can reduce computer resource occupation and delay.

In order to solve the technical problems, the technical scheme provided by the invention is as follows: a hardware analysis method of Binary protocol data stream is disclosed, wherein the hardware is FPGA or AISC and is configured to have an input interface cache, a decoding module and an output interface cache;

the input interface buffer is used for storing the received original Binary protocol data stream;

the decoding module is used for carrying out field matching on each data packet in the data stream according to a Binary protocol, and the matched field is decoding output;

the output interface buffer is used for buffering the data decoded and output by the decoding module;

the hardware performs the following steps: the input interface cache receives an original Binary protocol data stream and sends the data stream to a decoding module according to an FIFO (first in first out) strategy, the decoding module decodes each data packet in the data stream and sends the data packet to an output interface cache, and the output interface caches the decoded data and outputs the data packet according to the FIFO strategy so as to obtain a decoded code stream;

the decoding module is a state machine which is executed in sequence, and when decoding a data stream, the decoding module executes the following steps:

s100, an IDLE state, waiting for data flow;

s200, Message-Header state, stripping the packet Header of the data packet in the data stream, and storing the packet Header for a subsequent module;

s300, in the Message-Length state, stripping the data packet to obtain the data Length, and storing the data Length;

s400, Message-Analyze state, according to the header data obtained in step S200, the data packet is divided into three categories by matching according to the protocol field, and the three categories are respectively sent to corresponding sub-states for decoding, namely when the protocol field is 30xx92, step S401 is executed, when the protocol field is 30xx91, step S402 is executed, and when the protocol field is 30xx11, step S403 is executed;

s401, Message-30xx92 substates, processing the related data packet with suffix 92 in the data stream, and decoding according to the protocol of the corresponding 92 field;

s402, Message-30xx91 substates, processes the related data packet with suffix 91 in the data flow, and decodes according to the protocol of the corresponding 91 field;

s403, Message-30xx11 substates, processes the related data packet with suffix 11 in the data stream, and decodes according to the protocol of the corresponding 11 fields;

and S500, calculating CRC in a Message-CRC state, and discarding the error data packet.

The analysis method can be operated on an FPGA or a special AISC, overcomes the defects in the prior art by hardware decoding, greatly improves the processing capacity of a subsequent computer, reduces the resource occupation of the subsequent computer and reduces the processing delay. The decoding module is configured into a state machine which is executed in sequence, so that the data stream can be classified after being matched through the protocol fields and is respectively processed according to different classes, and the decoding efficiency is further improved.

Drawings

The invention will be further explained with reference to the drawings.

Fig. 1 is a schematic diagram of data stream transmission in the embodiment of the present invention.

Fig. 2 is a schematic diagram of an input interface cache.

Fig. 3 is a schematic flow chart of the operation of the decoding module.

Detailed Description

Examples

The hardware that can be selected in this embodiment is FPGA or dedicated AISC, and in this embodiment, FPGA is preferred, and the FPGA device belongs to a semi-custom circuit in an application-specific integrated circuit and is a programmable logic array. In implementation, the corresponding execution program is downloaded to the FPGA, and the FPGA is configured to have an input interface cache, a decoding module and an output interface cache, where the input interface cache is used to store the received original Binary protocol data stream, the decoding module is used to perform field matching on the data stream according to the Binary protocol, and the output interface cache is used to cache the matched fields.

As shown in fig. 2, the input interface cache adopts a FIFO memory of a standard AXI-Stream interface, has a high data speed and strong external portability, and can be directly interfaced with existing PCI-E devices or ethernet devices. The output interface cache is similar to the input interface cache in structure and is also an FIFO memory of an AXI-Stream interface, and the output interface cache has high interface speed and convenient transplantation.

In the hardware parsing method for Binary protocol data stream in this embodiment, the hardware executes the following steps: as shown in fig. 1, the input interface cache receives an original Binary protocol data stream and sends the data stream to the decoding module according to an FIFO policy, the decoding module decodes the data stream and sends the decoded data stream to the output interface cache, and the output interface cache outputs the decoded data according to the FIFO policy, so as to obtain a decoded code stream.

Wherein, the decoding module is a state machine executed in sequence, and when decoding a data stream, as shown in fig. 3, the decoding module executes the following steps:

s100, an IDLE state, waiting for data flow;

After the steps are executed, decoding of the current data stream is completed, and the current data stream is cached and then output to a client CPU through a network. When the next data flow comes, step S100 to step S500 are executed again.

The embodiment may further be modified in that the hardware is configured to further have a packet reforming module, and the packet reforming module is configured to modify a bit width of a data packet in the data stream sent by the input interface buffer corresponding to the decoding module, and then send the modified data packet to the decoding module. The packet reassembly module can perform any byte reassembly on the data packets in the data stream, that is, the input is 8 bytes, but the output can be any length from 1 to 8 bytes, so that the output length can be adjusted at will under the condition that the protocol field is uncertain, thereby achieving the protocol packet reforming effect.

In specific implementation, the decoding program is downloaded to the FPGA or is solidified in the ASIC (streaming chip is required), the deep traffic server sends out a transaction data stream, the transaction data stream is input to the FPGA or the ASIC through the network interface or the PCI-E interface, the transaction data stream is cached in the input interface cache, the length of each data packet is adjusted through the packet reforming module, the transaction data stream enters the decoding module, the decoding module performs data stripping and decoding according to the above steps, the decoded data is obtained and sent to the output interface cache, and the decoded data is output to the client CPU through the network interface or the PCI-E interface, so that the decoded data can be obtained, the decoding speed is high, and the decoding delay is small. The embodiment decodes through special hardware, greatly improves the decoding speed, can lighten the burden of a computer, and has great economic benefit.

The present invention is not limited to the specific technical solutions described in the above embodiments, and other embodiments may be made in the present invention in addition to the above embodiments. It will be understood by those skilled in the art that various changes, substitutions of equivalents, and alterations can be made without departing from the spirit and scope of the invention.

Claims

1. A hardware analysis method of Binary protocol data stream is characterized in that the hardware is FPGA or AISC and is configured to have an input interface cache, a packet reforming module, a decoding module and an output interface cache;

the packet reforming module is used for modifying the bit width corresponding to the decoding module of the data packet in the data stream sent by the input interface buffer;

the hardware performs the following steps: the input interface cache receives an original Binary protocol data stream, the packet reforming module modifies bit width corresponding to the decoding module on data packets in the data stream sent by the input interface cache, and sends the data stream to the decoding module according to an FIFO (first in first out) strategy, the decoding module decodes each data packet in the data stream and sends the data packet to the output interface cache, and the output interface caches the decoded data and outputs the data according to the FIFO strategy to obtain a decoded code stream;

s100, an IDLE state, waiting for data flow;

2. The hardware parsing method of Binary protocol data stream according to claim 1, wherein: the input interface cache receives an original Binary protocol data stream through a network interface or a PCI-E interface, and the output interface cache sends a decoded code stream through the network interface or the PCI-E interface.