CN112130386A

CN112130386A - Array substrate, display panel and display device

Info

Publication number: CN112130386A
Application number: CN202010900657.9A
Authority: CN
Inventors: 金慧俊
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2020-12-25
Anticipated expiration: 2040-08-31
Also published as: CN112130386B

Abstract

The invention discloses an array substrate, a display panel and a display device, wherein the array substrate comprises a display area and a non-display area surrounding the display area; the display area edge of the display area comprises at least one special-shaped edge section, the non-display area part corresponding to the special-shaped edge section comprises at least a plurality of shift registers, the area proportion of the component part of each shift register is adjusted along the shape of the first non-display area, the arrangement shape of the shift registers is matched with the shape of the special-shaped edge section, and the area proportions of the component parts of at least two shift registers are different. Compared with the prior art, the layout area of the non-display area is fully utilized, and narrow frame is achieved.

Description

Array substrate, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

With the continuous development of display technologies, people pay more and more attention to the narrowing of the frame of the display panel. A display panel of a conventional structure generally includes a display region and a non-display region located on a peripheral side of the display region, and a shift register constituting a gate driver circuit is arranged in the non-display region.

The integration technology of Amorphous Silicon Gate driver (ASG, also called shift register) and active matrix display is to directly integrate the original Gate driver IC on the glass substrate by using the existing production line a-Si process, so that the display panel becomes significantly lighter, the reliability of the display can be increased, and the cost can be reduced. In the prior art, due to the etching characteristics, that is, the etching amount of the traces at different angles is different, it is determined that all the thin film transistors TFT of the ASG must have the same angle. In order to maintain the etching uniformity, the shape and arrangement of the thin film transistors TFT of all ASGs are uniform, which results in that the area of the oblique region of the non-display region is not fully utilized, which is not favorable for narrowing the frame of the display panel.

Disclosure of Invention

In view of this, the present invention provides an array substrate, a display panel and a display device, and aims to improve the utilization rate of the layout area of the non-display region and to implement a narrow frame design of the display panel.

According to an aspect of the present invention, there is provided an array substrate including a display area and a non-display area surrounding the display area; the display area is provided with a display area edge, and the non-display area is positioned between the display area edge and the edge of the array substrate; the display area edge comprises at least one shaped edge segment, the shaped edge segment comprising at least one arc segment; for the non-display area, the part between the special-shaped edge section and the edge of the array substrate is a first non-display area, the first non-display area comprises a plurality of shift registers, and the shift registers are adjacent to the special-shaped edge section; the area ratio of the component part of each shift register is adjusted along the shape of the first non-display area, so that the arrangement shape of the shift registers is adapted to the shape of the special-shaped edge section, wherein the area ratios of the component parts of at least two shift registers are different.

According to another aspect of the invention, the invention also provides a display panel comprising the array substrate provided by the invention.

According to another aspect of the invention, the invention also provides a display device comprising the display panel provided by the invention.

Compared with the prior art, the array substrate, the display panel and the display device provided by the invention at least have the following beneficial effects:

the area proportion of the component part of each shift register is adjusted along the shape of the first non-display area, so that the arrangement shape of the shift registers is matched with the shape of the special-shaped edge section, and the area proportions of the component parts of at least two shift registers are different, so that the component layout of the non-display area is more reasonable, the oblique area of the non-display area is fully utilized, and the design of a narrow frame is realized.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic structural diagram of an array substrate in the prior art;

fig. 2 is a schematic diagram of arrangement of components in each shift register on an array substrate in the prior art;

FIG. 3 is a schematic layout diagram of transistors in a shift register in a first region of a non-display area of an array substrate according to a first embodiment of the present invention;

FIG. 4 is a schematic diagram of a cascade relationship of shift registers on an array substrate according to the present invention;

FIG. 5 is a schematic diagram of a shift register circuit according to the present invention;

fig. 6 is a schematic diagram of an arrangement structure of transistors with the largest layout area in a shift register in the prior art;

fig. 7 is a schematic diagram of an arrangement structure of a transistor with a largest layout area according to the first embodiment of the present invention;

fig. 8 is a schematic layout diagram of the components in the shift register 11 in fig. 3;

FIG. 9 is a schematic diagram illustrating the arrangement of transistors in a shift register in a second area of a non-display area on an array substrate according to a first embodiment of the present invention;

fig. 10 is a schematic view of another arrangement structure of transistors having the largest layout area in the first embodiment of the present invention;

fig. 11 is a schematic layout diagram of the components in the shift register 13 in fig. 9;

FIG. 12 is a schematic diagram illustrating the arrangement of capacitors in a shift register in a first area of a non-display area on an array substrate according to a second embodiment of the present invention;

fig. 13 is a schematic diagram illustrating an arrangement of a capacitor C2 according to a second embodiment of the present invention;

fig. 14 is a schematic layout diagram of the components in the shift register 11 in fig. 12;

FIG. 15 is a schematic diagram illustrating the arrangement of transistors and capacitors of a shift register in a first area of a non-display area on an array substrate according to a third embodiment of the present invention;

fig. 16 is a schematic layout diagram of the components in the shift register 11 in fig. 15;

FIG. 17 is a schematic structural diagram of a display panel according to the present invention;

fig. 18 is a schematic structural diagram of a display device according to the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the prior art, (a), (b) in fig. 1 are enlarged top views at the corners of the display panel in the screen structure within two circles, respectively, as shown in fig. 1. In the oblique region (for example, the upper right corner and the lower right corner of the display panel) and the straight line segment region of the non-display region of the display panel, in order to maintain the etching uniformity, all the thin film transistors TFT of the ASG have the same angle, the shape arrangement of the thin film transistors TFT of all the ASGs is uniform, and taking the ASG structure of 9T2C as an example, as shown in fig. 2, the thin film transistors T0 to T8 in the ASG all have the same direction arrangement. The inventors found that the area of the diagonal region in fig. 1 is not fully utilized, and the narrow border of the diagonal region is affected.

The first embodiment:

in order to solve the above technical problem, a first embodiment of the present invention provides an improved array substrate, as shown in fig. 3, including: the display panel includes a display area AA and a non-display area BB surrounding the display area AA, the display area AA having a display area edge a1, the non-display area BB being located between the display area edge a1 and an edge B1 of the array substrate.

On the display area edge a1, there is a shaped edge segment a1a2 located between the point a1 and the point a2, and the shaped edge segment a1a2 may be composed of at least one arc segment, in this embodiment, fig. 3 only shows one opposite-shaped edge segment a1a2, and actually, the number of shaped edge segments on the display area edge a1 may be plural, the number of shaped edge segments is determined according to the specific application environment of the array substrate, and each shaped edge segment may also be formed by connecting plural arc segments in sequence, which all fall within the protection scope of the present invention.

In the non-display area BB, an area region corresponding to the shaped edge segment a1a2 is defined as a first non-display area, that is, a portion between the shaped edge segment a1a2 and the edge B1 of the array substrate is a first non-display area, the first non-display area refers to a region composed of a point 1, a point 2, a point B1 and a point B2 in fig. 3, the first non-display area includes a plurality of shift registers 10 therein, and the shift registers 10 are adjacent to the opposite edge segment a1a 2.

Usually, a plurality of parallel gate lines 20 are disposed in the display area AA, and a plurality of cascaded shift registers, such as N cascaded shift registers shown in fig. 4, are included in the non-display area BB, and these cascaded shift registers certainly also include the shift register in the first non-display area, and each gate line 20 is electrically connected to one shift register. It is understood that the number of transistors in the shift register is not particularly limited in this embodiment, and besides, the electrical connection relationship between the transistors in each shift register is not particularly limited.

Each shift register comprises a plurality of transistor, a plurality of capacitors and other component parts, the area ratio of the component parts included in each shift register 10 in the first non-display area is adjusted along the shape of the first non-display area, and the arrangement shape of each shift register 10 is made to be adapted to the shape of the special-shaped edge section a1a2 corresponding to the position of the shift register.

It should be noted that, in the first non-display area, the area ratios of the component parts of at least two shift registers are different, and for example, the area ratios of the component parts S1 and S2 in the shift register 11 in fig. 3 are significantly different from the area ratios of the component parts S3 and S4 in the shift register 12.

It will be understood by those skilled in the art that the cascade relationship of the shift registers shown in fig. 4 is only an example, and the cascade relationship of the shift registers in the non-display area is not particularly limited by the present invention. The RESET line, the CK1 line, the CK2 line, the CKB1 line, and the CKB2 line in fig. 4 all belong to signal lines on the array substrate, and each stage of shift register includes an initialization signal terminal SET, a gate signal terminal Gn +1, a clock signal terminal CKB, a gate signal output terminal GOUT, an initialization signal terminal RESET, and a clock signal terminal CK.

Based on the above description, the area ratio of the component part of each shift register is adjusted along the shape of the first non-display area, so that the arrangement shape of the shift registers is adapted to the shape of the special-shaped edge section, and the area ratios of the component parts of at least two shift registers are different, so that the component layout of the non-display area is more reasonable, the oblique area of the non-display area is fully utilized, and the design of the narrow frame is realized.

In some embodiments, considering that a transistor with a large layout area in the shift register has a significant influence on whether or not the area of the slope region is fully utilized, in this embodiment, the transistor with the largest layout area in the plurality of transistors included in the shift register is divided into at least a first portion and a second portion that are electrically connected in the first direction y, and the area ratio of the first portion to the second portion is adjusted along the shape of the first non-display region.

In a specific implementation, in the shift register, the transistor with the largest layout area generally refers to a transistor electrically connected to a gate signal output terminal (GOUT) of the shift register, where the gate signal output terminal (GOUT) is electrically connected to the gate line 20 in the display area AA and is also electrically connected to an input terminal (SET) of a shift register of a next stage in the cascade. Since the transistor having the largest layout area is used to drive the gate line 20, it is generally called a driving transistor and is located in the shift register near the edge of the display region.

For example, the specific internal circuit structure of the shift register with the 9T2C structure shown in fig. 5 includes 9 transistors, i.e., the transistor T0 to the transistor T8, and the first capacitor C1 and the second capacitor C2. Wherein the content of the first and second substances,

the grid of the transistor T0 is electrically connected with an initialization signal end SET, the first pole is electrically connected with a high-potential signal line DIR1, and the second pole is electrically connected with a bootstrap point P;

a gate of the transistor T1 is electrically connected to the gate signal terminal Gn +1, a first pole is electrically connected to the bootstrap point P, and a second pole is electrically connected to the low potential signal line DIR 2;

a first capacitor C1 is arranged between the transistor T2 and the clock signal terminal CKB, wherein a first plate of the first capacitor C1 is electrically connected with the clock signal terminal CKB, and a second plate is electrically connected with the gate of the transistor T2; a first pole of the transistor T2 is electrically connected to the bootstrap point P, and a second pole is electrically connected to the low potential signal line VGL;

a gate of the transistor T3 is electrically connected to the bootstrap point P, and a first capacitor C1 is present between the first pole and the clock signal terminal CKB, wherein a first plate of the first capacitor C1 is electrically connected to the clock signal terminal CKB, a second plate is electrically connected to a first pole of the transistor T3, and a second pole of the transistor T3 is electrically connected to the low potential signal line VGL;

the gate of the transistor T4 is electrically connected to the bootstrap point P, the first pole is electrically connected to the clock signal terminal CKB, and the second pole is connected to the gate signal output terminal GOUT; a second capacitor C2 is arranged between the gate and the second pole of the transistor T4, wherein the first plate of the second capacitor C2 is electrically connected with the gate of the transistor T4, and the second plate is electrically connected with the second pole of the transistor T4;

a gate of the transistor T5 is electrically connected to a first pole of the transistor T3, a first pole of the transistor T5 is electrically connected to the gate signal output terminal GOUT, and a second pole is electrically connected to the low potential signal line VGL;

the gate of the transistor T6 is electrically connected to the clock signal terminal CK, the first pole is electrically connected to the gate signal output terminal GOUT, and the second pole is electrically connected to the low potential signal line VGL;

a gate of the transistor T7 is electrically connected to an initialization signal terminal RESET, a first pole is electrically connected to the bootstrap point P, and a second pole is electrically connected to a low potential signal line VGL;

the gate of the transistor T8 is electrically connected to the initialization signal terminal RESET, the first pole is electrically connected to the gate signal output terminal GOUT, and the second pole is electrically connected to the low potential signal line VGL.

The transistor comprises a grid G, a first pole S and a second pole D; the transistor T4 is electrically connected to the gate signal output terminal GOUT, and therefore the transistor T4 is the transistor with the largest layout area.

Optionally, if the layout area of the transistor is to be made larger, the structure of the transistor is usually made into a comb-shaped transistor, as shown in fig. 6, which is a schematic view of a top-view structure of the transistor T4 in the prior art, the overall shape of the transistor is a square, and the transistor includes a gate S, an active layer B, a source S, and a drain D, where the source S and the drain D both include a plurality of comb-teeth electrodes, in fig. 6, the source S includes 6 comb-teeth electrodes, and the drain D includes 5 comb-teeth electrodes, and the channel width W can be increased by increasing the lengths of the comb-teeth electrodes or increasing the number of the comb-teeth electrodes, thereby increasing the layout area of the transistor T4.

In the present embodiment, taking the shift register 11 in fig. 3 as an example, as shown in fig. 7, which is a schematic diagram of an arrangement of the transistors T4, the area ratio of the first portion S1 to the second portion S2 is adjusted along the shape of the first non-display region by dividing the transistor T4 in the shift register 11 into at least the first portion S1 and the second portion S2 which are electrically connected along the first direction y.

Illustratively, in order to ensure the driving capability of the transistor T4, the length of the comb-teeth electrode in the first portion S1 and the length of the comb-teeth electrode in the second portion S2 are both greater than 5 um.

It will be understood by those skilled in the art that the dividing manner of the transistor T4 along the first direction y may be an average dividing manner or may not be an average dividing manner, and the present invention is not limited thereto.

It can be obtained that, as shown in fig. 8, in the schematic layout of the shift register 11 in fig. 3, the transistor T4 is merely divided into two electrically connected portions along the first direction y, the direction of the comb-teeth electrodes in the first portion S1 and the direction of the comb-teeth electrodes in the second portion S2 are still consistent, i.e. both are parallel to the second direction x, and the other component portions in the shift register are not changed all the time, i.e. the third portion S13, where the S13 includes the transistor T0 to the transistor T3, the transistor T5 to the transistor T8, the capacitor C1 and the capacitor C2. In addition, the ends of the first and second portions S1 and S2 distal from the shaped edge segment a1a2 are aligned and the ends proximal to the shaped edge segment a1a2 are offset.

Note that the area ratio of the electrically connected first portion S3 and second portion S4 into which the transistor T4 is divided in the shift register 12 in fig. 3 is different from the area ratio of the electrically connected first portion S1 and second portion S2 into which the transistor T4 is divided in the shift register 11 in fig. 8. And because the difference of the area proportion is realized by adjusting the length-width proportion of each part, the layout area of the transistor T4 is also larger, and the change range of the area proportion in the first direction y of the array substrate is limited, therefore, the purpose of different area proportions can be achieved by only changing the length proportion of the first part and the second part along the second direction x.

It should be further noted that, in order to ensure the uniformity of the driving capability of each shift register, the sum of the areas of the respective portions is constant regardless of the division of the transistor T4 into the portions. For example, the sum of the areas of the first portion S1 and the second portion S2 of the transistor T4 in the shift register 11 in fig. 3 is the same as the sum of the areas of the first portion S3 and the second portion S4 of the transistor T4 in the shift register 12.

For example, as shown in fig. 6, in the prior art, the length of the transistor T4 along the second direction x is L, the height along the first direction Y is H, and the layout area of the transistor T4 is H × L. As shown in fig. 7, it is assumed that the transistor T4 is equally divided into two electrically connected portions along the first direction y, that is, the height of the first portion S1 is H1, the height of the second portion S2 is H2, the length of the first portion S1 along the second direction x is L1+ L2, and the length of the second portion S2 along the second direction x is L1, where H ═ H1+ H2, in order to ensure the driving capability uniformity of the shift register, the area of the transistor T4 is still H ═ L, and the length of the first portion S1 (L1+ L2) > L, that is, the relationship between H, L, H1, H2, L1, and L2 needs to satisfy the condition of H ═ L (L1+ L2) + H1+ L1 × H2.

It can be understood by those skilled in the art that the present invention does not limit the specific structure of the other transistors in the shift register except that the transistor with the largest layout area is the comb-shaped transistor, and in order to simplify the etching process, all transistors have the same channel direction, that is, all transistors have the same angle.

It should be noted that when the first non-display region is located in the first region of the array substrate (i.e. the upper left corner or the upper right corner of the screen in fig. 1), the area of the first portion is larger than that of the second portion, as shown in fig. 3, the first non-display region is located in the upper right corner of the array substrate, and the area of the first portion located in the upper half is larger than that of the second portion located in the lower half in the first direction Y.

When the first non-display region is located in the second region of the array substrate (i.e. the lower left corner or the lower right corner of the screen in fig. 1), the area of the first portion is smaller than that of the second portion, as shown in fig. 9, the first non-display region (the region consisting of the point a3, the point a4, the point b3, and the point b 4) is located in the lower right corner of the array substrate, and the area of the first portion located in the upper half is smaller than that of the second portion located in the lower half in the first direction Y.

Taking the shift register 13 in fig. 9 as an example, as shown in fig. 10, which is another layout diagram of the transistor T4, in the first direction Y, the area of the first portion C2 located in the upper half is smaller than the area of the second portion C1 located in the lower half, so that the area ratio of the first portion C2 to the second portion C1 is adjusted along the shape of the first non-display area.

Based on the principle of the uniform driving capability of the shift register described above, the sum of the areas of the respective portions is constant regardless of the division of the transistor T4 into the portions.

Assuming that the transistor T4 in fig. 10 is still divided into two electrically connected parts equally along the first direction y, that is, the height of the first part C2 is H1, the height of the second part C1 is H2, the length of the first part C2 along the second direction x is L1, and the length of the second part C1 along the second direction x is L1+ L2, where H ═ H1+ H2, in order to ensure the driving capability uniformity of the shift register, the area of the transistor T4 is still H × L in fig. 6, and the length of the second part C4 (L1+ L2) > L, that is, the relationship between H, L, H1, H2, L1, and L2 also needs to satisfy the condition of H × L ═ H597 + L59 1 × H2.

As shown in fig. 11, in order to illustrate the arrangement of the shift register 13 in fig. 9, the transistor T4 is divided into two electrically connected parts along the first direction y, the direction of the comb-teeth electrodes in the first part C2 and the direction of the comb-teeth electrodes in the second part C1 are still consistent, i.e. both are parallel to the second direction x, and are not changed for the other parts of the shift register, i.e. still the third part S13. In addition, the ends of the first and second portions C2 and C1 distal from the shaped edge segment a3a4 are aligned and the ends proximal to the shaped edge segment a3a4 are offset.

In some embodiments, since the curvatures at the four corners of the array substrate are generally consistent, in order to simplify the adjustment manner of the area ratios of the components in the shift registers, the area ratios of the components in the shift registers located on the same horizontal line may be set to be the same for the shift registers located at the upper right corner and the upper left corner in the array substrate; the area ratios of the component parts of the shift registers positioned on the same horizontal line can be set to be the same for the shift registers positioned at the right lower corner and the left lower corner in the array substrate.

Comparing the above fig. 3 with the above fig. 9, fig. 3 shows that the first non-display region is located at the upper right corner of the array substrate, fig. 9 shows that the first non-display region is located at the lower right corner of the array substrate, and the upper right corner of the array substrate and the lower right corner of the array substrate are symmetrical along the horizontal center line of the array substrate, so if the position of the shift register located at the lower right corner of the array substrate and the position of the shift register located at the upper right corner of the array substrate are symmetrical along the horizontal center line of the array substrate, the area ratio of the two portions of the transistor T4 in the two shift registers can be set to be the same. That is, the area of the first portion C2 of the transistor T4 in the shift register located at the lower right corner of the array substrate may be the same as the area of the second portion S2 of the transistor T4 in the shift register located at the upper right corner of the array substrate; the area of the second portion C1 of the transistor T4 in the shift register located at the lower right corner of the array substrate may be the same as the area of the second portion S2 of the transistor T4 in the shift register located at the upper right corner of the array substrate.

Therefore, as long as the area ratio of the transistor division of the shift register at one corner of the array substrate is adjusted, the area ratios at the other three corners can be determined.

Based on the above-described embodiment, the transistor with the largest layout area in the shift register is divided into at least two parts, and the area ratio of the two parts is adaptively adjusted according to the shape of the special-shaped edge section, so that the occupied area of the shift register is more adaptive and more attached to the shape of the first non-display area, the area of the inclined plane area of the non-display area can be fully utilized, and the narrow-frame design is realized.

Second embodiment:

in the present embodiment, another array substrate is provided, as shown in fig. 12, compared with the array substrate of the first embodiment, the array substrate of the present embodiment is different in that:

the arrangement of the capacitors of each shift register 10 in the first non-display area is adaptively adjusted so that the arrangement shape of the shift register 10 is adapted to the shape of the first non-display area. In this embodiment, at least one of the capacitors in the shift register 10 is divided into at least a third portion and a fourth portion that are electrically connected along the first direction y, and the area ratio of the third portion and the fourth portion in each shift register is adjusted along the shape of the first non-display area, so that the arrangement shape of the shift register 10 is adapted to the shape of the first non-display area, wherein the area ratio of the third portion and the fourth portion of at least two shift registers 10 is ensured to be different.

It should be noted that, since the transistor T4 in the shift register 10 needs to be close to the edge a1 of the display area, in order to make the arrangement of the capacitors in the shift register 10 correspond to the shape of the first non-display area, the capacitors divided into the third portion and the fourth portion may be disposed close to the edge B1 of the array substrate. And the ends of the third and fourth portions remote from the edge B1 of the array substrate are offset from the ends thereof near the edge B1 of the array substrate.

Taking the shift register 11 in fig. 12 as an example, as shown in fig. 13, which is a schematic diagram of an arrangement of capacitors in the shift register 11, the capacitor C2 is divided into a third portion D1 and a fourth portion D2 that are electrically connected along the first direction y, so that the area ratio of the third portion D1 to the fourth portion D2 is adjusted along the shape of the first non-display area.

It will be appreciated by those skilled in the art that the capacitor C1 may be divided into a third portion and a fourth portion which are electrically connected, or both the capacitor C1 and the capacitor C2 may be arranged in a divided manner.

As shown in fig. 14, the layout of the components in the shift register 11 in fig. 12 is schematically illustrated, wherein the capacitor C2 is divided into a third portion D1 and a fourth portion D2 that are electrically connected along the first direction y, the component portion indicated by S14 is all the components except the capacitor C2, and the S14 includes transistors T0 to T8 and a capacitor C1.

Note that the area ratio of the capacitor C2 in the shift register 12 divided into the electrically connected third portion D3 and the fourth portion D4 in fig. 12 is different from the area ratio of the capacitor C2 in the shift register 11 divided into the electrically connected third portion D1 and the fourth portion D2 in fig. 12.

As can be understood by those skilled in the art, since the difference in area ratio is realized by adjusting the length-width ratio of each portion, and the layout area of the capacitor is smaller than that of the transistor T4, the purpose of different area ratios can be achieved by only changing the length ratio of the third portion and the fourth portion along the second direction x, the purpose of different area ratios can be achieved by only changing the height ratio of the third portion and the fourth portion along the first direction y, and the purpose of different area ratios can be achieved by simultaneously changing the height ratio of the third portion and the fourth portion along the first direction y and the length ratio of the third portion and the fourth portion along the second direction x.

It should be further noted that, since the performance of the capacitor is related to the plate area of the capacitor, which is the layout area of the capacitor, in order to ensure the driving capability consistency of each shift register, the sum of the areas of each part is always constant no matter the capacitor in each shift register is divided into several parts. For example, the sum of the areas of the third portion D1 and the fourth portion D2 of the capacitor C2 in the shift register 11 in fig. 12 is the same as the sum of the areas of the third portion D3 and the fourth portion D4 of the capacitor C2 in the shift register 12.

It should be noted that, when the first non-display region is located in the first region of the array substrate (i.e. the upper left corner or the upper right corner of the screen in fig. 1), the area of the third portion is smaller than that of the fourth portion, as shown in fig. 12, the first non-display region is located in the upper right corner of the array substrate, and the area of the third portion located in the upper half is smaller than that of the fourth portion located in the lower half in the first direction y.

For example, assuming that the original layout area of the capacitor C2 is S, as shown in fig. 13, the heights of the capacitor C2 divided into the third portion D1 and the fourth portion D2 along the first direction y are h1 and h2, respectively, the length of the third portion D1 along the second direction x is w1, and the length of the fourth portion D2 along the second direction x is w 2. Among them, the relationships between h1, h2, w1, w2 and S need to satisfy S ═ (h2 × w2) + h1 ═ w2-w1) and h1 ═ w2-w1) < h2 × w 2.

Correspondingly, when the first non-display area is located in the second region of the array substrate (i.e., the lower left corner or the lower right corner of the screen in fig. 1), the area of the third portion is larger than that of the fourth portion.

In this embodiment, at least one capacitor in the shift register is divided into at least two parts, and the area ratio of the two parts is adaptively adjusted according to the shape of the edge of the array substrate, so that the occupied area of the shift register and the shape of the first non-display area are more adaptive and more attached to each other, the area of the inclined plane area of the non-display area can be fully utilized, and the narrow-frame design is realized.

For the purpose of brief description, any technical feature description applicable to the same application in the first embodiment is incorporated herein, and the same description need not be repeated.

The third embodiment:

with reference to the first and second embodiments, in this embodiment, another array substrate is provided, as shown in fig. 15, compared with the array substrates of the first and second embodiments, the array substrate of this embodiment is different in that:

the arrangement of the transistor and the capacitor with the largest layout area of each shift register 10 in the first non-display area is simultaneously adjusted adaptively, so that the arrangement shape of the shift register 10 is adapted to the shape of the first non-display area. In this embodiment, the transistor with the largest layout area in the shift register 10 is divided into at least a first part and a second part which are electrically connected along the first direction y, at least one capacitor is divided into at least a third part and a fourth part which are electrically connected along the first direction y, and the area ratio of the first part and the second part and the area ratio of the third part and the fourth part in each shift register 10 are adjusted along the shape of the first non-display area, so that the arrangement shape of the shift register 10 is adapted to the shape of the first non-display area. Wherein the area ratio of the first and second portions of at least two shift registers 10 and/or the area ratio of the third and fourth portions are different.

Taking the shift register 11 in fig. 15 as an example, as shown in fig. 16, the arrangement structure of the transistors and the capacitors of the shift register 11 is schematically illustrated, the transistor T4 with the largest layout area is divided into a first part S1 and a second part S2 which are electrically connected, the capacitor C2 is divided into a third part D1 and a fourth part D2 which are electrically connected, the component part indicated by S15 is all the components except the capacitor C2 and the transistor T4, and the S15 includes the transistors T0 to T3, the transistors T5 to T8, and the capacitor C1.

In this embodiment, by combining the division of the transistor with the largest layout area in the shift register and the division of the capacitor, the area ratio of the divided part of the transistor and the area ratio of the divided part of the capacitor are both adaptively adjusted according to the shape of the first non-display area, so that the occupied area of the shift register and the shape of the first non-display area are more adaptive and more conformable to each other, the area of the inclined plane area of the non-display area can be fully utilized, and the narrow-frame design is realized.

For the purpose of brief description, any technical feature description applicable to the same application in the first embodiment and the second embodiment is incorporated herein, and the same description need not be repeated.

Based on the array substrate described in the first, second, and third embodiments, in the first non-display area, the area ratio of the component part of the shift register away from the centerline of the array substrate in the second direction x is greater than the area ratio of the component part of the shift register close to the centerline of the array substrate in the second direction x.

That is, as shown in fig. 15 and 16, the shift register 11 is a shift register far from the center line of the array substrate in the second direction x, and the shift register 12 is a shift register near the center line of the array substrate in the second direction x, specifically, the area ratio of the first portion S1 and the second portion S2 of the transistor T4 in the shift register 11 is larger than the area ratio of the first portion S3 and the second portion S4 of the transistor T4 in the shift register 12, and/or the area ratio of the third portion D1 and the fourth portion D2 of the capacitor C2 in the shift register 11 is larger than the area ratio of the third portion D3 and the fourth portion D4 of the capacitor C2 in the shift register 12.

The invention further provides a display panel, as shown in fig. 17, including the array substrate 30, the color filter substrate 40, and the liquid crystal layer 50 disposed between the array substrate 30 and the color filter substrate 40 according to any of the embodiments. It should be noted that the display panel of the embodiment is exemplified by a liquid crystal display panel, and it should be understood by those skilled in the art that in other implementation manners of the present invention, the display panel may also be a panel or a display component of organic Light Emitting display panel (OLED), micro Light Emitting diode display panel (micro LED), Quantum Dot display panel (QLED), electronic paper, and the like, which is not limited to this, and is determined by the actual situation. The display panel provided in the embodiment of the present invention has the beneficial effects of the array substrate 30 provided in the embodiment of the present invention, and specific reference may be made to the above detailed description of the array substrate 30, which is not repeated herein.

The present invention further provides a display device 100, as shown in fig. 18, which includes the display panel shown in fig. 17, fig. 18 is a schematic structural diagram of a mobile phone as the display device according to an embodiment of the present invention, where the display device may further include: the present invention is not limited to any particular device having a display function, such as a computer, a television, a door lock, a vehicle-mounted display device, a navigator, and a console. The display device provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and specific reference may be made to the above specific description of the display panel, which is not repeated herein.

It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. In addition, the above definitions of the respective elements are not limited to the specific structures, shapes or modes mentioned in the embodiments, and those skilled in the art may easily modify or replace them. Directional phrases used in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., refer only to the direction of the attached drawings and are not intended to limit the scope of the present invention. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments. The word "comprising" does not exclude the presence of elements not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The use of the words first, second, third and the like do not denote any order, but rather the words first, second, third and the like are used to distinguish one element having a certain name from another element having the same name.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. The array substrate is characterized by comprising a display area and a non-display area surrounding the display area; the display area is provided with a display area edge, and the non-display area is positioned between the display area edge and the edge of the array substrate;

the display area edge comprises at least one profiled edge section comprising at least one arc section;

for the non-display area, the part between the special-shaped edge section and the edge of the array substrate is a first non-display area, the first non-display area comprises a plurality of shift registers, and the shift registers are adjacent to the special-shaped edge section;

and the area ratio of the component part of each shift register is adjusted along the shape of the first non-display area, so that the arrangement shape of the plurality of shift registers is adapted to the shape of the special-shaped edge section, wherein the area ratios of the component parts of at least two shift registers are different.

2. The array substrate according to claim 1, wherein each of the shift registers includes a plurality of transistors and a plurality of capacitors, a transistor having a largest layout area among the plurality of transistors is divided into at least a first portion and a second portion electrically connected in a first direction y, and an area ratio of the first portion to the second portion is adjusted along a shape of the first non-display region.

3. The array substrate of claim 2, wherein the transistor with the largest layout area is a comb-shaped transistor.

4. The array substrate of claim 3, wherein the comb-shaped transistor comprises a plurality of comb-teeth electrodes, and wherein the length of the comb-teeth electrodes in the first portion and the length of the comb-teeth electrodes in the second portion are both greater than 5 um.

5. The array substrate of claim 2,

when the first non-display area is positioned in the first area of the array substrate, the area of the first part is larger than that of the second part;

when the first non-display area is located in the second area of the array substrate, the area of the first portion is smaller than that of the second portion.

6. The array substrate of claim 2, wherein at least one of the plurality of capacitors is divided into at least a third portion and a fourth portion electrically connected along the first direction y, and an area ratio of the third portion to the fourth portion is adjusted along a shape of the first non-display region.

7. The array substrate of claim 1, wherein each of the shift registers comprises a plurality of capacitors, at least one of the capacitors is divided into at least a third portion and a fourth portion electrically connected along the first direction y, and an area ratio of the third portion to the fourth portion is adjusted along the shape of the first non-display area.

8. The array substrate of claim 6 or 7,

when the first non-display area is positioned in the first area of the array substrate, the area of the third part is smaller than that of the fourth part;

when the first non-display area is located in the second area of the array substrate, the area of the third portion is larger than that of the fourth portion.

9. The array substrate of claim 1, wherein the ratio of the area of the component part of the shift register away from the x-centerline of the array substrate in the second direction is greater than the ratio of the area of the component part of the shift register close to the x-centerline of the array substrate in the second direction.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.

11. A display device characterized by comprising the display panel according to claim 10.