CN112118008A - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- 238000005070 sampling Methods 0.000 claims abstract description 132
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000001514 detection method Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 12
- 101100499400 Arabidopsis thaliana DMS3 gene Proteins 0.000 description 6
- 101100018408 Arabidopsis thaliana IDN2 gene Proteins 0.000 description 6
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 6
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 6
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 5
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 5
- 101100007538 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) cpc-1 gene Proteins 0.000 description 5
- 101100460768 Arabidopsis thaliana NPR5 gene Proteins 0.000 description 4
- 101000984584 Homo sapiens Ribosome biogenesis protein BOP1 Proteins 0.000 description 4
- 102100027055 Ribosome biogenesis protein BOP1 Human genes 0.000 description 4
- 101100067993 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) ASC1 gene Proteins 0.000 description 4
- 101100067991 Schizosaccharomyces pombe (strain 972 / ATCC 24843) rkp1 gene Proteins 0.000 description 4
- 101150085700 bop2 gene Proteins 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 101150110971 CIN7 gene Proteins 0.000 description 3
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 3
- 101150110298 INV1 gene Proteins 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 102100027674 CTD small phosphatase-like protein Human genes 0.000 description 2
- 102100027667 Carboxy-terminal domain RNA polymerase II polypeptide A small phosphatase 2 Human genes 0.000 description 2
- 101000725950 Homo sapiens CTD small phosphatase-like protein Proteins 0.000 description 2
- 101000725947 Homo sapiens Carboxy-terminal domain RNA polymerase II polypeptide A small phosphatase 2 Proteins 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100067989 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) cpc-2 gene Proteins 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a phase-locked loop circuit which comprises a delay phase-locked loop and a sub-sampling phase-locked loop. The delay locked loop is used for locking a first reference frequency and a second reference frequency to an input frequency and comprises a phase correction circuit, an integrator, a first sub-sampling phase detector and a first charge pump. The sub-sampling phase-locked loop is configured to generate an output frequency at a predetermined phase-locked loop frequency, and the output frequency is phase-locked to a first reference signal. The first sub-sampling phase detector and the second sub-sampling phase detector have symmetrical circuit structures, and the first charge pump circuit and the second charge pump circuit have symmetrical circuit structures.
Description
Technical Field
The present invention relates to a phase-locked loop circuit, and more particularly, to a phase-locked loop circuit having a symmetrical circuit architecture.
Background
A Phase-locked loop (PLL) is a frequency and Phase synchronization technique implemented by using a Feedback control principle, and functions to keep a clock output by a circuit synchronized with a reference clock external to the circuit. When the frequency or Phase of the reference clock changes, the pll detects the change and adjusts the output frequency through its internal feedback system until the two are resynchronized, which is also called "Phase-locked".
In a conventional PLL, noise of a Phase Detector (PD) and a Charge Pump (CP) is multiplied by N when controlling a Voltage-controlled oscillator (VCO) output due to an N-fold frequency divider provided in a feedback path2This factor, in turn, dominates the phase noise of the PLL and limits the achievable PLL jitter power Factor (FOM). For this purpose, a Sub-sampling phase locked loop (SSPLL) has been studied in which the output of a high frequency VCO is Sub-sampled with a reference frequency using a phase detector. Because the divider is omitted from the feedback path, the PD and CP noise in the PLL is not multiplied by N2Further, the high phase detection gain causes a large attenuation, resulting in low phase noise and better PLL jitter/power factor.
However, when the above-mentioned Sub-sampling phase locked loop (SSPLL) is applied to the dll, the output frequency needs to be sampled simultaneously with another sampling circuit, and the sampling position has an error due to the different loads of the two sampling circuits relative to the output frequency. Therefore, how to further enable the sub-sampling circuit to accurately sample the output frequency to improve the circuit performance by improving the circuit design has become one of the important issues to be solved by the industry.
Disclosure of Invention
The present invention provides a phase-locked loop circuit for improving performance by using two sub-sampling phase detectors and a charge pump with a symmetrical circuit architecture to realize symmetrical sampling.
In order to solve the above technical problem, one of the technical solutions of the present invention is to provide a phase-locked loop circuit, which includes a delay phase-locked loop and a sub-sampling phase-locked loop. The delay locked loop is used for locking a first reference frequency and a second reference frequency at an input frequency and comprises a phase correction circuit, a first sub-sampling phase detector and a first charge pump circuit. The phase correction circuit is configured to adjust the input frequency according to a first control signal or a second control signal and generate a first reference frequency and a second reference frequency. The first sub-sampling phase detector is configured to sample the output frequency differential pair at a second reference frequency and convert a phase error between the second reference frequency and the output frequency differential pair to output a first charge pump control signal pair. The first charge pump circuit generates a second control signal according to the first charge pump control signal pair. The sub-sampling phase-locked loop is configured to generate an output frequency differential pair at a predetermined phase-locked loop frequency, and the output frequency differential pair is phase-locked to a first reference signal. The second sub-sampling phase detector is configured to sample the output frequency differential pair at a first reference frequency and convert a phase error between the first reference frequency and the output frequency differential pair to output a second charge pump control signal pair. The second charge pump circuit is configured to generate a third control signal according to the second charge pump control signal pair. The phase frequency detection circuit is configured to receive a first reference frequency and a frequency divided signal, and generate a fourth control signal when a phase error between the first reference frequency and the frequency divided signal is greater than a predetermined dead time. The voltage controlled oscillator is configured to generate an output frequency differential pair according to a third control signal and a fourth control signal. A first frequency divider configured to divide the output frequency differential pair to generate a divided signal. The first sub-sampling phase detector and the second sub-sampling phase detector have symmetrical circuit structures, and the first charge pump and the second charge pump have symmetrical circuit structures, so that the first sub-sampling phase detector and the second sub-sampling phase detector have the same load when sampling the output frequency differential pair respectively.
The phase-locked loop circuit provided by the invention has the beneficial effects that symmetrical sampling is realized by utilizing the two sub-sampling phase detectors with symmetrical circuit structures and the charge pump, so that the waveform of an output frequency differential pair is not influenced when the sub-sampling phase detection technology is applied in the phase-locked loop circuit, and further, the accurate sampling can be realized, and the efficiency is improved.
For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.
Drawings
Fig. 1 is a block diagram of a phase-locked loop circuit according to an embodiment of the invention.
Fig. 2 is a circuit architecture diagram of a delay locked loop circuit according to an embodiment of the invention.
Fig. 3 is a circuit architecture diagram of a first sub-sampling phase detector, a first charge pump circuit, a second sub-sampling phase detector and a second charge pump circuit according to an embodiment of the present invention.
Fig. 4 is an internal circuit diagram of the first sub-sampling phase detector, the first charge pump circuit, the second sub-sampling phase detector and the second charge pump circuit according to the embodiment of the present invention.
Fig. 5 is a circuit architecture diagram of the first pulse generator and the second pulse generator according to the embodiment of the invention.
FIG. 6 is a timing diagram of signals with and without a symmetric architecture according to an embodiment of the present invention.
Detailed Description
The following is a description of the embodiments of the present disclosure related to "phase-locked loop circuit" by specific embodiments, and those skilled in the art will understand the advantages and effects of the present disclosure from the disclosure of the present disclosure. The invention is capable of other and different embodiments and its several details are capable of modifications and various changes in detail, all without departing from the spirit and scope of the present invention. The drawings of the present invention are for illustrative purposes only and are not intended to be drawn to scale. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or from one signal to another signal. In addition, the term "or" as used herein should be taken to include any one or combination of more of the associated listed items as the case may be.
Fig. 1 is a block diagram of a phase-locked loop circuit according to an embodiment of the invention. As shown in fig. 1, an embodiment of the present invention provides a pll circuit PLLC, which includes a DLL and a SSPLL. The delay locked loop DLL utilizes a Feedback (Feedback) control principle to keep the output first reference frequency VREF1 and second reference frequency VREF2 synchronized with the external input frequency CLKIN, i.e., to lock the first reference frequency VREF1 and second reference frequency VREF2 in the input frequency CLKIN, thereby achieving frequency and phase synchronization.
As shown in fig. 1, the delay locked loop DLL includes a phase correction circuit DCC, an integrator INT, a first sub-sampling phase detector SSPD1, and a first charge pump circuit CP 1.
The phase correction circuit DCC is used for adjusting the input frequency CLKIN according to the first control signal Vctrl1 or the second control signal Vctrl2 and generating a first reference frequency VREF1 and a second reference frequency VREF 2.
The integrator INT is used for generating a first control signal Vctrl1 according to a first reference frequency VREF1 and a second reference frequency VREF2, the circuit details of which will be described in detail below.
Further, please refer to fig. 2, which is a circuit architecture diagram of the delay locked loop circuit according to an embodiment of the present invention. As shown in fig. 2, the integrator INT generates the first control signal Vctrl1 according to the first reference frequency VREF1 and the second reference frequency VREF 2. The first control signal Vctrl1 may vary with the average component of the duty cycle of the first reference frequency VREF1 and the second reference frequency VREF 2.
For example, the integrator INT may decrease (or increase) the voltage level of the first control signal Vctrl1 when the duty ratio of the first reference frequency VREF1 and the second reference frequency VREF2 is greater (or less) than a target value (e.g., 50%). Alternatively, when the duty ratio of the first reference frequency VREF1 and the second reference frequency VREF2 is greater than (or less than) the target value, the voltage level of the first control signal Vctrl1 is increased (or decreased). The change of the first control signal Vctrl1 reflects the change of the duty ratio of the first reference frequency VREF1 and the second reference frequency VREF 2. Therefore, the frequency multiplier can be used in the duty cycle adjustment mode and has a low Jitter (Jitter) amount.
On the other hand, the first sub-sampling phase detector SSPD1 is coupled to the phase correction circuit DCC, and the first charge pump circuit CP1 is coupled to the first sub-sampling phase detector SSPD 1. The first sub-sampling phase detector SSPD1 receives the second reference frequency VREF2 and the output frequency differential pair Vvco, samples the output frequency differential pair Vvco with the second reference frequency VREF2, and converts a phase error between the second reference frequency VREF2 and the output frequency differential pair Vvco to output a first charge pump control signal pair CPC 1. The first charge pump circuit CP1 generates a second control signal Vctrl2 for the CPC1 according to the first charge pump control signal.
Wherein the control signal generated by the first sub-sampling phase detector/first sub-sampling phase detector SSPD 1/first charge pump circuit CP1 may be filtered by a low pass filter, thereby generating the second control signal Vctrl 2. The purpose is to add a sub-sampling delay locked loop (SSDLL) on top of the sub-sampling phase locked loop SSPLL, which uses the same sub-sampling phase detection circuit as the sub-sampling phase locked loop SSPLL but with a sampling frequency that is the inverse of the first reference frequency VREF1, i.e. the second reference frequency VREF 2. Therefore, the sub-sampling phase-locked loop SSPLL samples the output frequency differential pair Vvco of the voltage controlled oscillator VCO with a rising edge, which enables the rising edge of the second reference frequency VREF2 (i.e., the falling edge of the first reference frequency VREF 1) to be aligned with the Vvco zero-crossing point. Therefore, in the dll mode, the pll can be used as a phase retarder in a sub-sampling pll SSPLL and has a low glitch (spur).
Referring again to fig. 2, the sub-sampling phase-locked loop SSPLL is used for generating the output frequency differential pair Vvco at a predetermined phase-locked loop frequency, and the output frequency differential pair Vvco is phase-locked to the first reference signal VREF 1. Specifically, the sub-sampling phase-locked loop SSPLL includes a second sub-sampling phase detector SSPD2, a second charge pump circuit CP2, a phase frequency detection circuit PFDC, a voltage controlled oscillator VCO, and a first frequency divider Div-N.
The second sub-sampling phase detector SSPD2 is configured to sample the output frequency differential pair Vvco at the first reference frequency VREF1, and convert a phase error between the first reference frequency VREF1 and the output frequency differential pair Vvco to output a second charge pump control signal pair CPC 2. The second charge pump circuit CP2 is configured to generate a third control signal Vctrl3 for the CPC2 according to the second charge pump control signal.
The phase frequency detection circuit PFDC is configured to receive the first output frequency VREF1 and the frequency divided signal Vdiv, and generate the fourth control signal Vctrl4 when a phase error between the first output frequency VREF1 and the frequency divided signal is greater than a predetermined Dead time (Dead time).
The VCO generates an output frequency differential pair Vvco according to the third control signal Vctrl3 and the fourth control signal Vctrl 4. The first frequency divider Div-N is used to divide the output frequency differential pair Vvco to generate the divided signal Vdiv.
On the other hand, when the phase error between the first reference frequency VREF1 and the output frequency differential pair Vvco output by the voltage controlled oscillator VCO is small, the phase frequency detection circuit PFDC detects that this phase error is less than the predetermined dead time, and thus the output becomes zero. In other words, until the output frequency differential pair Vvco is close to being locked, the voltage controlled oscillator VCO is mainly controlled by the fourth control signal Vctrl4, and when the output frequency differential pair Vvco is in a locked state, the voltage controlled oscillator VCO is controlled to be in a locked state by the third control signal Vctrl 3. Thus, in the locked state, the sub-sampling phase locked loop SSPLL has no divider in the feedback path, thus eliminating the noise generated by the divider while being immune to its power. Furthermore, the sub-sampling phase locked loop SSPLL can achieve very low phase noise.
The phase frequency detector PFD receives the first output frequency VREF1 and the frequency divided signal Vdiv, and generates a third charge pump control signal pair CPC3 when a phase error between the first output frequency VREF1 and the frequency divided signal Vdiv is greater than a predetermined dead time. The third charge pump control signal pair CP3 is configured to generate a fourth control signal Vctrl4 for the CPC3 as a function of the third charge pump control signal pair CP 3.
In addition, as shown in fig. 2, the sub-sampling phase-locked loop SSPLL further includes a low-pass filter LPF for filtering the third control signal Vctrl3 and the fourth control signal Vctrl4 to generate a second filtered signal Vpf, and the VCO generates the output frequency differential pair Vvco according to the second filtered signal Vpf. In this way, the second sub-sampling phase detector SSPD2 and the second charge pump circuit CP2 sample the differential pair of output frequencies Vvco of the voltage controlled oscillator VCO, but cannot distinguish the frequency of the first reference frequency VREF1 from other harmonics of this frequency. Therefore, the sub-sampling phase-locked loop SSPLL may erroneously lock to an unnecessary frequency division ratio, and thus the frequency-locked loop FLL is required for accurate frequency locking. Here, the frequency locked loop FLL includes a phase frequency detection circuit PFDC and a first frequency divider Div-N.
It should be noted that the voltage controlled oscillator VCO can be a Ring oscillator (Ring VCO), which has a large adjustment gain, and therefore, a small variation in the control signal will cause the output frequency differential pair Vvco output by the voltage controlled oscillator VCO to have a large variation in the frequency. Therefore, it is necessary to provide the frequency locked loop FLL with a precisely predetermined dead time for the sub-sampling phase locked loop SSPLL to operate when the frequency of the output frequency differential pair Vvco is farther from the locked state.
Further referring to fig. 3 and fig. 4, they are a circuit architecture diagram and an internal circuit diagram of the first sub-sampling phase detector, the first charge pump circuit, the second sub-sampling phase detector and the second charge pump circuit, respectively, according to the embodiment of the present invention. As shown, the first charge pump circuit CP1 includes a first differential pair circuit DP1, a first current mirror circuit MR1, and a first charge pump CPI, and the second charge pump circuit CP2 includes a second differential pair circuit DP2, a second current mirror circuit MR2, and a second charge pump CPII.
The first sub-sampling phase detector SSPD1 and the second sub-sampling phase detector SSPD2 have a symmetrical circuit structure, and the first charge pump circuit CP1 and the second charge pump circuit CP2 have a symmetrical circuit structure, so that the first sub-sampling phase detector SSPD1 and the second sub-sampling phase detector SSPD2 have the same load when sampling the first output frequency Vvcop and the second output frequency Vvcon of the output frequency differential pair Vvco, respectively.
With further reference to fig. 4, the first sub-sampling phase detector SSPD1 includes a first sampling switch SW1, a second sampling switch SW2, a first sampling capacitor Cs1, and a second sampling capacitor Cs 2. One end of the first sampling switch SW1 receives the first output frequency Vvcop of the output frequency differential pair Vvco, and a control end thereof is controlled by the second reference frequency VREF2 to sample the first output frequency Vvcop to output the first charge pump control signal CPC12 of the first charge pump control signal pair CPC1 from the other end thereof.
One end of the second sampling switch SW2 receives the second output frequency Vvcon of the output frequency differential pair Vvco, and a control end thereof is controlled by the second reference frequency VREF2 to sample the second output frequency Vvcon to output the second charge pump control signal CPC11 of the first charge pump control signal pair CPC1 from the other end thereof. During operation, the first sub-sampling phase detector SSPD1 samples the high-frequency output frequency differential pair Vvco directly at the low-frequency second reference frequency VREF2 without using a frequency divider. Which detects a phase difference between the output frequency differential pair Vvco and a second reference frequency VREF2, and the second reference frequency VREF2 samples edges of the output frequency differential pair Vvco and converts them into a sampled voltage difference, generating a current for controlling the first charge pump CPI.
The first sampling capacitor Cs1 is connected between the other end of the first sampling switch SW1 and the first reference voltage source Vr 1. The second sampling capacitor Cs2 is connected between the other end of the second sampling switch SW2 and the second reference voltage source Vr 2.
Further referring to fig. 3, the first differential pair circuit DP1 is configured to convert the first and second charge pump control signals CPC11 and CPC12 into the first and second charge pump control currents IUP1 and IDN1, and the first current mirror circuit MR1 is configured to copy the first and second charge pump control currents IUP1 and IDN1 and input the first charge pump CPI.
In detail, the first differential pair circuit DP1 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a first current source S1. The first terminal of the first transistor M1 is connected to the first system reference voltage VDD1, the second terminal thereof is connected to the third terminal thereof, the first terminal of the second transistor M2 is connected to the third terminal of the first transistor M1, the second terminal thereof receives the first charge pump control signal CPC11, and the third terminal thereof is connected to the second system reference voltage VDD2 through the first current source S1. The third transistor M3 has a first terminal connected to the first system reference voltage VDD1 and a second terminal connected to the third terminal. The fourth transistor M4 has a first terminal connected to the third terminal of the third transistor M3, a second terminal receiving the second charge pump control signal CPC12, and a third terminal connected to the second system reference voltage VDD2 via the first current source S1.
Therefore, in response to the first charge pump control signal CPC11 and the second charge pump control signal CPC12, and based on the current magnitude of the first current source S1, a first charge pump control current IUP1 is generated at the first transistor M1, and a second charge pump control current IDN1 is generated at the third transistor M3, respectively.
Further, the first current mirror circuit MR1 includes a ninth transistor M9 and a tenth transistor M10, wherein a first terminal of the ninth transistor M9 is connected to the first system reference voltage VDD1, and a second terminal thereof is connected to the second terminal of the first transistor M1. The tenth transistor M10 has a first terminal connected to the second terminal thereof and the third terminal of the ninth transistor M9, and the third terminal is connected to the second system reference voltage VDD 2.
Here, the ninth transistor M9 and the first transistor M1 form a current mirror structure, so the second charge pump control current IDN1 is generated at the ninth transistor M9.
Referring next to fig. 4, the first charge pump CPI may include a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18. The thirteenth transistor M13 has a first terminal connected to the first system reference voltage VDD1 and a second terminal connected to the second terminal of the third transistor M3. Here, the thirteenth transistor M13 and the third transistor M3 form a current mirror structure, so that the first charge pump control current IUP1 is generated at the thirteenth transistor M13.
The fourteenth transistor M14 has a first terminal connected to the third terminal of the thirteenth transistor M13, a second terminal receiving the first pulse signal P1, and a third terminal connected to the fifth system reference voltage Vr5 through the first capacitor C1. A first terminal of the fifteenth transistor M15 is connected to the third terminal of the fourteenth transistor M14, and a second terminal thereof receives the first pulse-inverted signal
A sixteenth transistor M16 having a first terminal connected to the third terminal of the thirteenth transistor M13 and a second terminal receiving the first pulse-inverted signal
The seventeenth transistor M17 has a first terminal connected to the third terminal of the sixteenth transistor M16, and a second terminal receiving the first pulse signal P1.
The eighteenth transistor M18 has a first terminal connected to the third terminal of the fifteenth transistor M15 and the third terminal of the seventeenth transistor M17, a second terminal connected to the second terminal of the tenth transistor M10, and a third terminal connected to the second system reference voltage VDD 2. Here, the eighteenth transistor M18 and the tenth transistor M10 form a current mirror structure, so that the second charge pump control current IDN1 is generated at the eighteenth transistor M18.
In addition, the first charge pump CPI further includes a first buffer amplifier BOP1, a first input terminal of which is connected to the second terminal of the sixteenth transistor M16, a second input terminal of which is connected to the third terminal of the fifteenth transistor M15. The first Buffer amplifier BOP1 may be used to reduce the problem of charge sharing in the first charge pump CPI, wherein the first Buffer amplifier BOP1 may be a single gain amplifier (OPA) as a Buffer (Buffer), and when the transistor in the first charge pump CPI is turned off, since the current source is composed of a transistor, the drain voltage thereof can be maintained as the voltage of the output point, and when the transistor is turned on, the charge sharing effect is reduced.
In addition, the method can be used for producing a composite materialFig. 5 is a circuit architecture diagram of the first pulse generator and the second pulse generator according to the embodiment of the invention. In detail, the delay locked loop DLL further includes a first pulse generator PSR1 including a first delay unit DC1, a first inverter INV1, and a first and gate AG 1. The first delay unit DC1 delays the second reference frequency VREF2 by the first pulse delay time τ p1 to generate the first delayed reference frequency DVREF 1. The first inverter INV1 inverts the second reference frequency to generate the first inverted signal INVs 1. The first AND gate AG1 ANDs the first delayed reference frequency DVREF1 AND the first inverted signal INVS1 to generate a first pulse signal P1, AND generates the first pulse inverted signal through another inverter
Wherein, the first pulse signal P1 does not overlap with the second reference frequency VREF 2.
In detail, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 respectively receive the first pulse signal P1 and the first pulse inversion signal provided by the first pulse generator PSR1
Controlled to provide the second control signal Vctrl2 having the same period as the second reference frequency VREF2 and the same first pulse delay time τ P1 as the first pulse signal P1, such that the first charge pump CPI is enabled for the first pulse delay time τ P1 only in a single period of the second reference frequency VREF2 and the gain of the first charge pump CPI is dependent on the first pulse delay time τ P1. Also, therefore, when the phase error between the output frequency differential pair Vvco and the second reference frequency VREF2 is zero, a ripple can be prevented from occurring in the output second control signal Vctrl 2.
Similarly, the first and second sub-sampling phase detectors SSPD1 and SSPD2 have a symmetrical circuit architecture, and the first and second charge pump circuits CP1 and CP2 have a symmetrical circuit architecture. As further shown in fig. 3 and 4, the second sub-sampling phase detector SSPD2 includes a third sampling switch SW3, a fourth sampling switch SW4, a third sampling capacitor Cs3, and a fourth sampling capacitor Cs 4. One end of the third sampling switch SW3 receives the first output frequency Vvcop of the output frequency differential pair Vvco, and a control end thereof is controlled by the first reference frequency VREF1 to sample the first output frequency Vvcop to output the fourth charge pump control signal CPC22 of the second charge pump control signal pair CPC2 from the other end thereof.
One end of the fourth sampling switch SW4 receives the second output frequency Vvcon of the output frequency differential pair Vvco, and a control end thereof is controlled by the first reference frequency VREF1 to sample the second output frequency Vvcon to output the third charge pump control signal CPC21 of the second charge pump control signal pair CPC2 from the other end thereof. During operation, the second sub-sampling phase detector SSPD2 samples the high-frequency output frequency differential pair Vvco directly at the low-frequency first reference frequency VREF1 without the use of a frequency divider. Which detects the phase difference between the output frequency differential pair Vvco and a first reference frequency VREF1, and the first reference frequency VREF1 samples the edges of the output frequency differential pair Vvco and converts them to a sampled voltage difference, generating a current for controlling the second charge pump CPII.
The third sampling capacitor Cs3 is connected between the other end of the third sampling switch SW3 and the third reference voltage source Vr 3. The fourth sampling capacitor Cs4 is connected between the other end of the fourth sampling switch SW4 and the fourth reference voltage source Vr 4.
Further referring to fig. 3, the second differential pair circuit DP2 is used to convert the third and fourth charge pump control signals CPC21 and CPC22 into the third and fourth charge pump control currents IUP2 and IDN2, and the second current mirror circuit MR2 is used to copy the third and fourth charge pump control currents IUP2 and IDN2 and input the second charge pump CPII.
In detail, the second differential pair circuit DP2 may include a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a second current source S2. The first terminal of the fifth transistor M5 is connected to the third system reference voltage VDD3, the second terminal thereof is connected to the third terminal thereof, the first terminal of the sixth transistor M6 is connected to the third terminal of the fifth transistor M5, the second terminal thereof receives the third charge pump control signal CPC21, and the third terminal thereof is connected to the fourth system reference voltage VDD4 through the second current source S2. The seventh transistor M7 has a first terminal connected to the third system reference voltage VDD3, and a second terminal connected to the third terminal. The eighth transistor M8 has a first terminal connected to the third terminal of the seventh transistor M7, a second terminal receiving the fourth charge pump control signal CPC22, and a third terminal connected to the fourth system reference voltage VDD4 via the second current source S2.
Therefore, in response to the third charge pump control signal CPC21 and the fourth charge pump control signal CPC22, and based on the current magnitude of the second current source S2, the third charge pump control current IUP2 is generated at the fifth transistor M5, and the fourth charge pump control current IDN2 is generated at the seventh transistor M7, respectively.
Further, the second current mirror circuit MR2 includes an eleventh transistor M11 and a twelfth transistor M12, wherein a first terminal of the eleventh transistor M11 is connected to the third system reference voltage VDD3, and a second terminal thereof is connected to a second terminal of the fifth transistor M5. The twelfth transistor M12 has a first terminal connected to the second terminal thereof and the third terminal of the eleventh transistor M11, and the third terminal is connected to the fourth system reference voltage VDD 4.
Here, the eleventh transistor M11 and the fifth transistor M5 form a current mirror structure, so that the fourth charge pump control current IDN2 is generated at the eleventh transistor M11.
Referring next to fig. 4, the second charge pump CPII may include a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twentieth transistor M22, a twenty-third transistor M23, and a twenty-fourth transistor M24. The nineteenth transistor M19 has a first terminal connected to the third system reference voltage VDD3 and a second terminal connected to the second terminal of the seventh transistor M7. Here, the nineteenth transistor M19 and the seventh transistor M7 form a current mirror structure, so the third charge pump control current IUP2 is generated at the nineteenth transistor M19.
The twentieth transistor M20 has a first terminal connected to the third terminal of the nineteenth transistor M19, a second terminal receiving the second pulse signal P2, and a third terminal connected to the sixth system reference voltage Vr6 through the second capacitor C2. Twenty-first transistor M2The first terminal of the 1 is connected with the third terminal of the twentieth transistor M20, and the second terminal thereof receives the second pulse inversion signal
The twenty-second transistor M22 has a first terminal connected to the third terminal of the nineteenth transistor M19, and a second terminal receiving the second pulse-inverted signal
The first terminal of the twenty-third transistor M23 is connected to the third terminal of the twenty-second transistor M22, and the second terminal thereof receives the second pulse signal P2.
The first terminal of the twenty-fourth transistor M24 is connected to the third terminal of the twenty-first transistor M21 and the third terminal of the twenty-third transistor M23, the second terminal thereof is connected to the second terminal of the twelfth transistor M12, and the third terminal thereof is connected to the fourth system reference voltage VDD 4. Here, the twenty-fourth transistor M24 and the twelfth transistor M12 form a current mirror structure, so that the fourth charge pump control current IDN2 is generated at the twenty-fourth transistor M24.
The second charge pump CPII further comprises a second buffer amplifier BOP2, which has a first input connected to the second terminal of the twenty-second transistor M22, a second input connected to the third terminal thereof, and a third terminal connected to the third terminal of the twenty-first transistor M21. The second Buffer amplifier BOP2 may be used to reduce the problem of charge sharing in the second charge pump CPII, in which the second Buffer amplifier BOP2 may be a single gain amplifier (OPA) as a Buffer (Buffer), and when the transistor in the second charge pump CPII is turned off, since the current source is composed of a transistor, the drain voltage thereof can be maintained as the voltage of the output point, and when the transistor is turned on, the charge sharing effect is reduced.
In addition, referring to fig. 5, the sub-sampling phase locked loop SSPLL further includes a second pulse generator PSR2 including a second delay unit DC2, a second inverter INV2 and a second and gate AG 2. The second delay unit DC2 delays the first reference frequency VREF1 by a second pulse delay time τ p2 to generate a second delayed reference frequency DVREF 2. A second inverter INV2 for inverting the first reference frequency VREF1Generating a second inverted signal INVS 2. The second AND gate AG2 ANDs the second delayed reference frequency DVREF2 AND the second inverted signal INVS2 to generate a second pulse signal P2, AND generates a second pulse inverted signal after passing through another inverter
Wherein, the second pulse signal P2 does not overlap with the first reference frequency VREF 1.
In detail, the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22 and the twenty-third transistor M23 are respectively the second pulse signal P2 and the second pulse inversion signal provided by the second pulse generator PSR2
Controlled to provide a third control signal Vctrl3 having the same period as the first reference frequency VREF1 and the same second pulse delay time τ P2 as the second pulse signal P2, such that the second charge pump CPII is enabled for the second pulse delay time τ P2 only in a single period of the first reference frequency VREF1, and the gain of the second charge pump CPII is dependent on the second pulse delay time τ P2. Also, therefore, when the phase error between the output frequency differential pair Vvco and the first reference frequency VREF1 is zero, a ripple can be prevented from occurring in the output third control signal Vctrl 3.
Further, reference can be made to fig. 6, which is a timing diagram of signals with and without a symmetric architecture according to an embodiment of the present invention. As shown, in the case of not adopting the symmetric architecture, when two sampling circuits (such as the first sub-sampling phase detector SSPD1 and the second sub-sampling phase detector SSPD2) perform sampling, the load relative to the first output frequency Vvcop is different, so that the phase error PSER occurs at the sampling position. On the other hand, in the case of the symmetric architecture, since the first sub-sampling phase detector SSPD1 and the second sub-sampling phase detector SSPD2 have completely symmetric circuit architectures when sampling, so that the output frequency differential pair Vvco has the same waveform, accurate sampling can be performed to eliminate the phase error PSER.
[ advantageous effects of the embodiments ]
The phase-locked loop circuit provided by the invention has the beneficial effects that symmetrical sampling is realized by utilizing the two sub-sampling phase detectors with symmetrical circuit structures and the charge pump, so that the waveform of an output frequency differential pair is not influenced when the sub-sampling phase detection technology is applied in the phase-locked loop circuit, and further, the accurate sampling can be realized, and the efficiency is improved.
The disclosure is only a preferred embodiment of the invention and should not be taken as limiting the scope of the invention, which is defined by the appended claims.
[ notation ] to show
A phase-locked loop circuit: PLLC
A delay locked loop: DLL
A sub-sampling phase-locked loop: SSPLL
First reference frequency: VREF1
Second reference frequency: VREF2
Input frequency: CLKIN
A phase correction circuit: DCC
An integrator: INT
First sub-sampling phase detector SSPD1
First charge pump circuit CP1
The first control signal: vctrl1
The second control signal: vctrl2
Voltage controlled oscillator: VCO
Phase frequency detection circuit: PFDC
A first frequency divider: Div-N
Third control signal: vctrl3
Frequency-removing signals: vdiv
The fourth control signal: vctrl4
A second sub-sampling phase detector: SSPD2
A second charge pump circuit: CP2
The first charge pump control signal pair: CPC1
The second charge pump control signal pair: CPC2
A phase frequency detector: PFD
A third charge pump: CP3
The third charge pump control signal pair: CPC3
A low-pass filter: LPF
Second filtered signal: vpf
Frequency locked loop: FLL
A first differential pair circuit: DP1
The first current mirror circuit: MR1
A first charge pump: CPI
A second differential pair circuit: DP2
The second current mirror circuit: MR2
A second charge pump: CPII
First output frequency: vvcop
The second output frequency: vvcon
A first pulse generator: PSR1
A second pulse generator: PSR2
The first charge pump control signal: CPC11
The second charge pump control signal: CPC12
The third charge pump control signal: CPC21
Fourth charge pump control signal: CPC22
The first pulse signal: p1
First pulse inversion signal:
the second pulse signal: p2
The second pulse inversion signal:
a first sampling switch: SW1
A second sampling switch: SW2
A third sampling switch: SW3
A fourth sampling switch: SW4
First sampling capacitance: cs1
A second sampling capacitance: cs2
Third sampling capacitance: cs3
Fourth sampling capacitance: cs4
A first transistor: m1
A second transistor: m2
A third transistor: m3
A fourth transistor: m4
A fifth transistor: m5
A sixth transistor: m6
A seventh transistor: m7
An eighth transistor: m8
A ninth transistor: m9
A tenth transistor: m10
An eleventh transistor: m11
A twelfth transistor: m12
A thirteenth transistor: m13
A fourteenth transistor: m14
A fifteenth transistor: m15
A sixteenth transistor: m16
A seventeenth transistor: m17
An eighteenth transistor: m18
A nineteenth transistor: m19
A twentieth transistor: m20
A twenty-first transistor: m21
A twentieth transistor: m22
A twentieth transistor: m23
A twenty-fourth transistor: m24
A first current source: s1
A second current source: s2
First system reference voltage: VDD1
Second system reference voltage: VDD2
Third system reference voltage: VDD3
Fourth system reference voltage: VDD4
A first reference voltage source: vr1
A second reference voltage source: vr2
Third reference voltage source: vr3
Fourth reference voltage source: vr4
Fifth system reference voltage: vr5
Sixth system reference voltage: vr6
A first buffer amplifier: BOP1
A second buffer amplifier: BOP2
A first delay unit: DC1
A first inverter: INV1
A first AND gate: AG1
A second delay unit: DC2
A second inverter: INV2
A second AND gate: AG2
First delay reference frequency: DVREF1
First inversion signal: INVS1
First pulse delay time: tau p1
Second delay reference frequency: DVREF2
The second inverted signal: INVS2
Second pulse delay time: tau p2
The first control signal: vctrl1
Output frequency: vvco (human Vvco)
The second charge pump controls current: IDN1
The fourth charge pump controls current: IDN2
The third charge pump controls current: IUP2
The first charge pump controls current: IUP1
A first capacitance: c1
A second capacitance: c2
Phase error: PSER.
Claims (10)
1. A phase-locked loop circuit comprising:
a delay locked loop for phase locking a first reference frequency and a second reference frequency to an input frequency, comprising:
a phase correction circuit configured to adjust the input frequency according to a first control signal or a second control signal and generate the first reference frequency and the second reference frequency;
an integrator for generating the first control signal according to the first reference frequency and the second reference frequency;
a first sub-sampling phase detector configured to sample an output frequency differential pair at the second reference frequency and convert a phase error between the second reference frequency and the output frequency differential pair to output a first charge pump control signal pair; and
a first charge pump circuit for generating the second control signal according to the first charge pump control signal pair; and
a sub-sampling phase-locked loop configured to generate the output frequency differential pair at a predetermined phase-locked loop frequency, and the output frequency differential pair is phase-locked to the first reference signal, comprising:
a second sub-sampling phase detector configured to sample the output frequency differential pair at the first reference frequency and convert a phase error between the first reference frequency and the output frequency differential pair to output a second charge pump control signal pair; and
a second charge pump circuit configured to generate a third control signal according to the second charge pump control signal pair;
a phase frequency detection circuit configured to receive the first reference frequency and a divided frequency signal, the phase frequency detection circuit generating a fourth control signal when a phase error between the first reference frequency and the divided frequency signal is greater than a predetermined dead time;
a voltage controlled oscillator configured to generate the output frequency differential pair according to the third control signal and the fourth control signal; and
a first frequency divider configured to divide the output frequency differential pair to generate the divided signal,
the first sub-sampling phase detector and the second sub-sampling phase detector have symmetrical circuit structures, and the first charge pump circuit and the second charge pump circuit have symmetrical circuit structures, so that the first sub-sampling phase detector and the second sub-sampling phase detector have the same load when sampling the output frequency differential pair respectively.
2. The phase-locked loop circuit of claim 1, wherein the second reference frequency is an inverse of the first reference frequency.
3. The phase locked loop circuit of claim 2, wherein the second sub-sampling phase detector comprises:
a third sampling switch, one end of which receives the first output frequency of the output frequency differential pair, and the control end of which is controlled by the first reference frequency to sample the first output frequency, so as to output a third charge pump control signal of the second charge pump control signal pair from the other end; and
a fourth sampling switch, one end of which receives the second output frequency of the output frequency differential pair, and the control end of which is controlled by the second reference frequency to sample the second output frequency, so as to output a fourth charge pump control signal of the second charge pump control signal pair from the other end thereof.
4. The phase locked loop circuit of claim 3, wherein the first sub-sampling phase detector comprises:
the first sampling capacitor is connected between the other end of the first sampling switch and a first reference voltage source;
and the second sampling capacitor is connected between the other end of the second sampling switch and a second reference voltage source.
5. The phase locked loop circuit of claim 4, wherein the second sub-sampling phase detector comprises:
the third sampling capacitor is connected between the other end of the third sampling switch and a third reference voltage source;
and the fourth sampling capacitor is connected between the other end of the fourth sampling switch and a fourth reference voltage source.
6. The phase locked loop circuit of claim 5, wherein the first charge pump circuit comprises:
a first differential pair circuit for converting the first and second charge pump control signals into a first and second charge pump control currents;
and the first charge pump converts the difference value of the first charge pump control current and the second charge pump control current into the second control signal according to a first pulse control signal and outputs the second control signal.
7. The phase locked loop circuit of claim 6, wherein the second charge pump circuit comprises:
a second differential pair circuit for converting the third and fourth charge pump control signals into a third and fourth charge pump control currents;
and the second charge pump converts the difference value of the third charge pump control current and the fourth charge pump control current into the third control signal according to a second pulse control signal and outputs the third control signal.
8. The phase locked loop circuit of claim 7 wherein the first charge pump circuit further comprises a first current mirror circuit to replicate the first and second charge pump control currents and input to the first charge pump.
9. The phase locked loop circuit of claim 8 wherein the second charge pump circuit further comprises a second current mirror circuit to replicate the third and fourth charge pump control currents and input to the second charge pump.
10. The phase-locked loop circuit of claim 9, wherein the first differential pair circuit comprises:
a first transistor, wherein a first terminal of the first transistor is connected to a first system reference voltage, and a second terminal of the first transistor is connected to a third terminal of the first transistor;
a second transistor, wherein a first terminal of the second transistor is connected to a third terminal of the first transistor, a second terminal of the second transistor receives the first charge pump control signal, and the third terminal of the second transistor is connected to a second system reference voltage through a first current source;
a third transistor, wherein a first terminal of the third transistor is connected to the first system reference voltage, and a second terminal of the third transistor is connected to a third terminal of the third transistor;
and a fourth transistor, wherein a first terminal of the fourth transistor is connected to the third terminal of the third transistor, a second terminal of the fourth transistor receives the second charge pump control signal, and a third terminal of the fourth transistor is connected to the second system reference voltage through the first current source.
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