CN112117263A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The disclosed embodiments relate to a semiconductor structure and a method for fabricating the same. A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite the first active surface. The second semiconductor die is located over the first semiconductor die and includes a second semiconductor substrate having a second active surface and a second back surface opposite the second active surface. The second semiconductor die is bonded to the first semiconductor die by bonding the second active surface to the first back surface at the first hybrid bonding interface in a vertical direction. In the lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The disclosed embodiments relate to a semiconductor structure and a method for fabricating the same.

Background

In recent years, the semiconductor industry has experienced rapid growth due to the continued increase in integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density comes from the continuous reduction in minimum feature size (minimum feature size), which enables more components to be integrated into a given area. For example, the integrated components occupy an area close to the surface of the semiconductor wafer; however, there are physical limitations to the density achievable in two-dimensional (2D) integrated circuit formation. For example, one of these limitations arises from the significant increase in the number and length of interconnections between semiconductor devices as the number of semiconductor devices increases. Since existing integrated circuit design rules require that the pitch of the conductive wiring layout be reduced in the semiconductor structure, there is an ongoing effort to develop new mechanisms for forming semiconductor structures.

Disclosure of Invention

The embodiment of the present disclosure provides a semiconductor structure including a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite the first active surface. The second semiconductor die is located over the first semiconductor die and includes a second semiconductor substrate having a second active surface and a second back surface opposite the second active surface. The second semiconductor die is bonded to the first semiconductor die by bonding the second active surface to the first back surface at a first hybrid bonding interface in a vertical direction. The first dimension of the first semiconductor die is greater than the second dimension of the second semiconductor die in a lateral direction.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-4 are schematic cross-sectional views illustrating various stages in a semiconductor die fabrication method according to some embodiments of the present disclosure.

Fig. 5-24 are schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

Fig. 25 is a schematic top view showing relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure.

Fig. 26A is an enlarged schematic cross-sectional view illustrating a bonding interface between a semiconductor die and a carrier die located beneath the semiconductor die in the dashed-line region a outlined in fig. 11 according to some embodiments of the present disclosure.

Fig. 26B is an enlarged schematic cross-sectional view illustrating a bonding interface between a semiconductor die and a carrier die located beneath the semiconductor die according to some embodiments of the present disclosure.

Fig. 27A is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of the die stack in the dashed-line region B outlined in fig. 17, according to some embodiments of the present disclosure.

Fig. 27B is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of a die stack according to some embodiments of the present disclosure.

Fig. 28A is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of the die stack in the dashed-line region C outlined in fig. 19, according to some embodiments of the present disclosure.

Fig. 28B is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of a die stack according to some embodiments of the present disclosure.

Fig. 28C is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of a die stack according to some embodiments of the present disclosure.

Fig. 29A is an enlarged schematic cross-sectional view illustrating a configuration of an outermost level of the die stack in the dashed-line region D outlined in fig. 19, according to some embodiments of the present disclosure.

Fig. 29B is an enlarged schematic cross-sectional view showing the configuration of the outermost tier of the die stack according to some embodiments of the present disclosure.

Fig. 30-44 are schematic cross-sectional views respectively illustrating semiconductor structures according to some embodiments of the present disclosure.

Fig. 45 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

Fig. 46A and 46B are schematic top views respectively showing relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure.

Fig. 47 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

Fig. 48A and 48B are schematic top views respectively showing relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure.

Fig. 49-56 are schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

Fig. 57 is a schematic top view showing relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure.

Figure 58 is a schematic cross-sectional view illustrating an application of a semiconductor structure according to some embodiments of the present disclosure.

[ description of symbols ]

10A, 10A ', 10A ", 10B': semiconductor die

10A' ", 10B": thinned semiconductor die

10A (1): first level/internal level

10A (2): second level/internal level

10A (T): the topmost level

10A (T-1): (T-1) th level/internal level

10B: carrier die/semiconductor die

10B (0): base hierarchy

20. 40: insulating packaging body

20': insulating material

20a, 20b, S60: surface of

20S, 40S, 60S, 70S, 100S, 110S, 130SW, 150SW, 230S, 230SW, S5: side wall

30: conductive terminal

31: bump

32: metal top cover

50. 51, 160, 240: insulating layer

50(0), 50(1), 50 (T-1): isolation structure

50a, 51 a: first lateral part

50b, 51 b: second lateral part

50c, 51 c: connecting part

50c ', 51 c': planarized connecting portion

60: electromagnetic interference shielding layer

60A: electromagnetic interference shielding material

70: protective layer

100: die stacking

100b, 110b ', 110b ", 110b '", 130b, 160b, 210b ', 210b ", 230b, 240 b: bottom surface

110. 210: semiconductor substrate

120. 220, and (2) a step of: internal connection structure

130. 230: conducting hole

140. DI1, DI2, DI3, DI 4: dielectric layer

150: joint conductor

150 a: bonding pad

150 b: bonding via

A. B, C, D: dashed area/box

AP: conducting pad

BE: beveled edge

BS: back side

C1: first assembly

C2: second assembly

CT: terminal with a terminal body

D1, D2: depth of field

FS: front side

I-I, II-II, III-III, IV-IV: cross section line

IF1, IF 2: bonding interface

MP: metallization pattern

OP: opening of the container

P1a, P1b, P1c, P1d, P2a, P2b, P2c, P2d, P3a, P3b, P3c, P3d, P4a, P4b, P4c, P4d, P5, P6, P7: semiconductor structure

PL: passivation layer

R1, R2: depressions

RE: rounded edge

S1, S3: front surface

S2, S4: back surface

SC: component assembly

And SE: sharp edge

SS1, SS 2: stacking structure

T1, T2, T3, T4, T5, T6, T10A, T10B, T50, T51, T60: thickness of

TB1, TB2, TB3, TB 4: temporary bonding layer

TC1, TC2, TC3, TC 4: temporary carrier

TP 1: adhesive tape frame

UF: primer layer

W1, W2, W2': semiconductor wafer

W1': thinned semiconductor wafer

W10B, W100: width of

X, Y: direction of rotation

Z: stacking direction

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are contemplated. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below …", "below …", "lower", "above …", "upper", and the like may be used herein to describe one element or feature's relationship to another element or feature for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Additionally, for ease of description, terms such as "first," "second," "third," and the like may be used herein to describe similar or different elements or features shown in the figures, and may be used interchangeably depending on the order of presence or context of the description.

Some embodiments of the present disclosure may also include other features and processes. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structure may include, for example, test pads (test pads) formed in a redistribution layer or on a substrate to enable testing of a 3D package or 3DIC, use of probes and/or probe cards (probe card), and the like. Verification tests may be performed on the intermediate structures as well as the final structure. In addition, the structures and methods disclosed herein may be used in conjunction with testing methods that include intermediate verification of Known Good Dies (KGD) to improve yield and reduce cost.

Fig. 1-4 are schematic cross-sectional views illustrating various stages in a semiconductor die fabrication method according to some embodiments of the present disclosure. Referring to fig. 1, in some embodiments, a semiconductor wafer W1 is provided. In some embodiments, the semiconductor wafer W1 includes a plurality of semiconductor dies 10A' connected to one another. For example, each of the semiconductor dies 10A' may comprise an integrated circuit device (e.g., a logic die, a memory die, a radio frequency die, a power management die, a micro-electro-mechanical-system (MEMS) die, similar devices, or a combination of these). In some embodiments, the thickness T1 of the semiconductor wafer W1 is in a range from about 720 micrometers (μm) to about 800 μm.

For example, each of the semiconductor dies 10A' includes a semiconductor substrate 110, an interconnect structure 120, a plurality of vias 130, a dielectric layer 140, and a plurality of bonding conductors 150, a plurality of semiconductor devices (not shown) are formed in the semiconductor substrate 110, the interconnect structure 120 is formed on the semiconductor substrate 110, the plurality of vias 130 are formed in the semiconductor substrate 110 and extend into the interconnect structure 120, the dielectric layer 140 is formed on the interconnect structure 120 and opposite the semiconductor substrate 110, and the plurality of bonding conductors 150 are formed over the interconnect structure 120 and laterally (laterally) covered by the dielectric layer 140. In some embodiments, as shown in fig. 1, each of the semiconductor dies 10A 'has a front surface S1 and a bottom surface 110 b' opposite the front surface S1. The bonding conductors 150 are distributed at the front surface S1 and are exposed by the dielectric layer 140 in a accessible manner, and the bottom surface 110 b' can be regarded as a side away from the interconnect structure 120 and the bonding conductors 150.

In some embodiments, the semiconductor substrate 110 comprises a bulk semiconductor, which may be doped or undoped, a semiconductor-on-insulator (SOI) substrate, other supporting substrates (e.g., quartz, glass, etc.), combinations thereof, or the like. In some embodiments, the semiconductor substrate 110 includes an elemental semiconductor (e.g., silicon or germanium in a crystalline, polycrystalline, or amorphous structure, etc.), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide, etc.), an alloy semiconductor (e.g., silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (alinium arsenide, AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (galnas), indium gallium phosphide (galnp), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure. In some embodiments, the alloy SiGe is formed over a silicon substrate. In other embodiments, the SiGe substrate is strained. The semiconductor substrate 110 may include a plurality of semiconductor devices (not shown) formed therein or thereon, and the semiconductor devices may be or may include active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, inductors, etc.) or other suitable electrical components. In some embodiments, the semiconductor device is formed at a side of the semiconductor substrate 110 proximate to the interconnect structure 120.

The semiconductor substrate 110 may include a circuit system (not shown) formed in a front-end-of-line (FEOL) process, and the interconnect structure 120 may be formed in a back-end-of-line (BEOL) process. In some embodiments, the interconnect structure 120 includes an inter-layer dielectric (ILD) layer formed over the semiconductor substrate 110 and covering the semiconductor device and an inter-metal dielectric (IMD) layer formed over the ILD layer. In some embodiments, the ILD and IMD layers are formed of low dielectric constant (low-K) or extremely low dielectric constant (ELK) materials such as oxide, silicon dioxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), Fluorinated Silicate Glass (FSG), SiOxCy, spin-on glass, spin-on polymer, silicon carbon materials, compounds thereof, composites thereof, combinations thereof, or the like. The ILD and IMD layers may include, without limitation, any suitable number of dielectric material layers.

In some embodiments, an interconnect structure 120 is formed on a semiconductor substrate 110, the interconnect structure 120 including one or more dielectric layers (e.g., dielectric layer DI1 shown in fig. 26A) and one or more metallization patterns (e.g., metallization pattern MP shown in fig. 26A). The metallization pattern may be embedded in a dielectric layer (e.g., an IMD layer), and the metallization pattern (e.g., metal lines, metal vias, metal pads, metal traces, etc.) may be formed of a conductive material such as copper, gold, aluminum, the like, or combinations thereof. In some embodiments, the interconnect structures 120 are electrically coupled to each other to semiconductor devices formed in and/or on the semiconductor substrate 110 and to external components (e.g., a plurality of test pads, a plurality of bonding conductors, etc.). For example, metallization patterns in the dielectric layer route electrical signals between semiconductor devices of the semiconductor substrate 110. The semiconductor device is interconnected with metallization patterns to perform one or more functions including memory structures (e.g., memory cells), processing structures, input/output circuitry, or the like. The outermost layer of the interconnect structure 120 may be a passivation layer (e.g., passivation layer PL shown in fig. 26A) made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics, polyimide, combinations of these, or the like. In some embodiments, each of the semiconductor dies 10A' includes a conductive pad (e.g., conductive pad AP shown in fig. 26A) disposed over and electrically coupled to the top metallization pattern of the interconnect structure 120, and the passivation layer of the interconnect structure 120 may have an opening that exposes at least a portion of the conductive pad for testing or for further electrical connection.

In some embodiments, the via 130 is formed to extend into the semiconductor substrate 110. The via 130 may be in physical and electrical contact with the metallization pattern of the interconnect structure 120. For example, when the via 130 is initially formed, the via 130 is embedded in the semiconductor substrate 110 and may not extend to the bottom surface 110 b' of the semiconductor substrate 110. That is, with the semiconductor wafer W1, the via 130 is not exposed to the semiconductor substrate 110 in an accessible manner.

For example, each of the vias 130 can include a barrier material (e.g., TiN, Ta, TaN, Ti, or the like; not shown) and a conductive material (e.g., copper, tungsten, aluminum, silver, combinations thereof, or the like; not shown). For example, a barrier material may be formed between the conductive material and the semiconductor substrate 110.

In an alternative embodiment, a dielectric liner (not shown) (e.g., silicon nitride, oxide, polymer, combinations thereof, etc.) may further optionally be formed between the barrier material of the via 130 and the semiconductor substrate 110. In some embodiments, the via 130 is formed by: a recess is formed in the semiconductor substrate 110 and a dielectric liner, barrier material, and conductive material are deposited in the recess, respectively, removing excess material on the semiconductor substrate 110. For example, the plurality of recesses of the semiconductor substrate 110 are lined with a dielectric liner in order to laterally separate the semiconductor substrate 110 and the via 130. The via 130 may be formed by using a via-first (via-first) manner. For example, the via 130 is formed during the formation of the interconnect structure 120. Alternatively, the via 130 may be formed using via-last (via-last) and may be formed after the interconnect structure 120 is formed. The present disclosure is not limited thereto.

In some embodiments, a dielectric layer 140 is formed on the interconnect structure 120. For example, the dielectric layer 140 includes one or more layers (e.g., dielectric layers DI2, DI3, DI4 shown in fig. 26A) formed of a dielectric material (e.g., silicon nitride, silicon oxide, high-density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), Undoped Silicate Glass (USG), the like, or combinations thereof). In some embodiments, the bonding is then performed using a dielectric layer 140 that laterally covers the bonding conductors 150. It is understood that the dielectric layer 140 may include a layer of etch stop material (not shown) sandwiched between layers of dielectric material, depending on process requirements. For example, the layer of etch stop material is different from the overlying or underlying layer of dielectric material. The layer of etch stop material may be formed of a material having a high etch selectivity relative to an overlying or underlying layer of dielectric material so as to serve to stop etching of the layer of dielectric material. The structure of the dielectric layer 140 will be described in detail later in conjunction with the drawings.

In some embodiments, bond conductors 150, such as a plurality of bond vias (bond via) (e.g., bond via 150b shown in fig. 26A) and/or a plurality of bond pads (e.g., bond pad 150a shown in fig. 26A), are formed over the interconnect structure 120 to provide external electrical connections to circuitry and semiconductor devices. In the present disclosure, the bonding conductors 150 each have a bonding pad on which two or more bonding through holes are provided. The bond conductor 150 may be formed of a conductive material such as copper, gold, aluminum, the like, or combinations thereof. Bonding conductor 150 may be electrically coupled to the semiconductor devices of semiconductor substrate 110 through interconnect structure 120. The bond conductor 150 may be substantially flush with the dielectric layer 140 for bonding. The above examples are provided for illustrative purposes, other embodiments may utilize fewer or additional elements (e.g., conductive pads), and details of the semiconductor die will be described later in connection with the enlarged figures. In other words, the semiconductor wafer W1 may also be said to include the semiconductor substrate 110, the interconnect structure 120, the via 130, the dielectric layer 140, and the bonding conductor 150, as shown in fig. 1, for example.

Referring to fig. 2, in some embodiments, a semiconductor wafer W1 is placed on a temporary carrier TC1 through a temporary bonding layer TB 1. The material of temporary carrier TC1 may include glass, metal, ceramic, silicon, plastic, combinations thereof, multilayers thereof, or other suitable materials that may provide structural support for semiconductor wafer W1 in subsequent processing. In some embodiments, temporary carrier TC1 is made of glass, and temporary bonding layer TB1 used to bond semiconductor wafer W1 to temporary carrier TC1 includes a polymer adhesive layer (e.g., Die Attach Film (DAF)), an Ultraviolet (UV) cured layer such as a light-to-heat conversion (LTHC) release coating, an Ultraviolet (UV) glue, or the like that reduces or loses its adhesion when exposed to a radiation source (e.g., UV light or laser). Other suitable temporary adhesives may be used. In some embodiments, temporary carrier TC1 is a silicon wafer, and temporary bonding layer TB1 comprises a silicon-containing dielectric material (e.g., silicon oxide, silicon nitride, etc.) or other suitable dielectric material for bonding. For example, the bonding includes oxide-to-oxide bonding (oxide-to-oxide bonding), and the dielectric layer 140 of the semiconductor wafer W1 is bonded to the temporary bonding layer TB 1. Alternatively, temporary bonding layer TB1 may be omitted.

In some embodiments, as shown in fig. 2, front side FS of semiconductor wafer W1 (e.g., front surface S1 of semiconductor die 10A ') is attached to temporary carrier TC1 with back side BS of semiconductor wafer W1 (e.g., bottom surface 110b ' of semiconductor die 10A ') facing upward for subsequent processing. For example, the front side FS is opposite to the back side BS along the stacking direction Z of the semiconductor substrate 110 and the interconnect structure 120.

Referring to fig. 2 and 3, in some embodiments, semiconductor wafer W1 is thinned by, for example, an etching, grinding, Chemical Mechanical Polishing (CMP) process, a combination thereof, or other suitable thinning technique to form thinned semiconductor wafer W1'. For example, a thinning process is performed on the backside BS of the semiconductor wafer W1 (e.g., the bottom surface 110b ' of the semiconductor die 10A ') to obtain a thinned semiconductor wafer W1 ' having a reduced thickness T2. That is, the reduced thickness T2 of the thinned semiconductor wafer W1' is less than the thickness T1 of the semiconductor wafer W1. In some embodiments, the reduced thickness T2 is in a range from about 40 μm to about 200 μm. As shown in fig. 3, after the thinning process, the vias 130 have not been exposed in an accessible manner through the backside BS of the thinned semiconductor wafer W1' (e.g., the bottom surfaces 110b "of the semiconductor die 10A"). In other words, for each semiconductor die 10A ", the bottom surface 130b of the via 130 is not exposed by the bottom surface 110 b" of the semiconductor die 10A "in an accessible manner.

With continued reference to fig. 4, in some embodiments, after the wafer backside thinning process, the thinned semiconductor wafer W1' is mounted on a tape frame TP 1. For example, the structure shown in fig. 3 is flipped over (e.g., upside down in the stacking direction Z) such that the backside BS of the thinned semiconductor wafer W1' (e.g., the bottom surfaces 110b (of the semiconductor substrate 110) of the semiconductor die 10A ") is disposed on the tape frame TP 1. Next, a de-bonding process may be performed on the temporary carrier TC1 to release from the thinned semiconductor wafer W1'. For example, external energy (e.g., UV light or laser) is applied on the temporary bonding layer TB 1. Alternatively, the removal process of the temporary carrier TC1 may include a mechanical peeling process, a grinding process, an etching process, or the like. In some embodiments, a cleaning process is performed using a suitable solvent, cleaning chemistry, or other cleaning technique to remove the residue of temporary bonding layer TB1 from thinned semiconductor wafer W1'. Subsequently, a singulation process (singulation process) is performed on the thinned semiconductor wafer W1' to obtain a plurality of separated individual semiconductor dies 10A ″. As shown in fig. 4, for example, the separate respective semiconductor dies 10A "each have a front surface S1 and a bottom surface 110 b".

For example, during the singulation process, the tape frame TP1 holds the thinned semiconductor wafer W1 'in place, and a cutting tool (e.g., a saw) may be used to cut through the thinned semiconductor wafer W1' along a scribe line (not shown). In other embodiments, the singulation process is performed prior to mounting on the tape frame TP 1. In some embodiments, the semiconductor dies 10A "included in the thinned semiconductor wafer W1' are tested for functionality and performance by probing (probing) prior to dicing/singulation, and only Known Good Dies (KGD) are selected from the tested semiconductor dies 10A" and used for subsequent processing.

In some embodiments, temporary carrier TC1 shown in fig. 2 and 3 may be replaced by a tape frame TP 1. For example, the semiconductor wafer W1 is mounted on the first tape frame with the front side FS of the semiconductor wafer W1 facing the first tape frame, and then the thinning process is performed on the back side BS of the semiconductor wafer W1. Subsequently, the thinned semiconductor wafer W1 ' is transferred to be mounted on the second tape frame with the backside BS of the thinned semiconductor wafer W1 ' (e.g., the bottom surfaces 110b "of the semiconductor die 10A") facing the second tape frame, and then the singulation process is performed with the second tape frame holding the thinned semiconductor wafer W1 ' in place during the singulation process. It should be noted that the above examples are provided for illustrative purposes, and that the formation of semiconductor die 10A "may be formed in any logical order not limited by the present disclosure.

Fig. 5-24 are schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure, and are taken along the cross-sectional line I-I depicted in fig. 25. Fig. 25 is a schematic top view showing relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure. Fig. 26A is an enlarged schematic cross-sectional view illustrating a bonding interface between a semiconductor die and a carrier die located beneath the semiconductor die in the dashed-line region a outlined in fig. 11 according to some embodiments of the present disclosure. Fig. 27A is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of the die stack in the dashed-line region B outlined in fig. 17, according to some embodiments of the present disclosure. Fig. 28A is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of the die stack in the dashed-line region C outlined in fig. 19, according to some embodiments of the present disclosure. Fig. 29A is an enlarged schematic cross-sectional view illustrating a configuration of an outermost level of the die stack in the dashed-line region D outlined in fig. 19, according to some embodiments of the present disclosure. A method of manufacturing a semiconductor structure includes bonding a die stack (e.g., 100) to a carrier die (e.g., 10B), wherein forming the die stack involves a stacked plurality of semiconductor dies (e.g., 10A and 10A'). For ease of understanding, like elements are designated with like reference numerals and, for simplicity, will not be described in detail herein.

Referring to fig. 5, in some embodiments, at least one semiconductor die 10B' is provided. For example, a semiconductor wafer (not shown) is processed in the manner described in fig. 1-4 to produce a respective plurality of semiconductor die 10B ', and thus, for simplicity, the formation of semiconductor die 10B' is not described in detail herein. The semiconductor dies 10B' may each include a similar structure as the semiconductor die 10A ". For example, each of the semiconductor dies 10B 'has a front surface S3 and a bottom surface 210B' opposite the front surface S3, and includes a semiconductor substrate 210, an interconnect structure 220 and a plurality of vias 230, the semiconductor substrate 210 having a plurality of semiconductor devices formed therein, the interconnect structure 220 formed over the semiconductor substrate 210 and including a plurality of dielectric layers proximate the front surface S3 and a plurality of metallization patterns, the vias 230 formed in the semiconductor substrate 210 and extending into the dielectric layers of the interconnect structure 220 to make physical and electrical contact with the metallization patterns of the interconnect structure 220. The vias 230 of each of the semiconductor die 10B' may be electrically coupled to the semiconductor device and the metallization pattern of the interconnect structure 220.

For illustrative purposes, only two semiconductor dies 10B' are shown in fig. 5; however, the number of semiconductor die 10B' is not limited to the present disclosure. The number of semiconductor die 10B' may be one or more than one based on design layout and requirements.

It should be noted that various layers and features of each of the semiconductor dies 10B' are omitted from the figure. For example, the interconnect structure 220 may include a passivation layer (not shown) formed over the top metallization pattern of the interconnect structure 220 to provide a degree of protection to the underlying structures. The passivation layer may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics, polyimide, combinations of these, or the like. The conductive pads may now be covered by a passivation layer for protection.

It is understood that semiconductor die cut from different semiconductor wafers may have different properties and functions. In some embodiments, semiconductor die 10B' and semiconductor die 10A "are singulated from different semiconductor wafers, which may differ in function and properties. For example, the semiconductor die 10B' depicted in fig. 5 is a logic die (e.g., a system-on-a-chip (SoC), a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), etc.). On the other hand, the semiconductor die 10A "set forth in fig. 4 is, for example, a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, a Synchronous Dynamic Random Access Memory (SDRAM), a NAND (NAND) flash memory, etc.). As shown in fig. 5, for example, two semiconductor dies 10B' are shown for illustration purposes; however, the number of semiconductor dies 10B' is not limited to that depicted in this disclosure and may be selected and specified based on requirements and design layout.

Referring to fig. 6 and 7, in some embodiments, semiconductor die 10B' is disposed on temporary carrier TC2 by temporary bonding layer TB 2. For example, a semiconductor wafer including semiconductor die 10B' is probed and tested prior to singulation. After the singulation process is performed, only known good semiconductor die 10B' are picked and placed on temporary carrier TC 2. In some embodiments, a temporary bonding layer TB2 is deposited over temporary carrier TC2, and the front surface S3 of each of semiconductor die 10B' is attached to temporary carrier TC2 by temporary bonding layer TB 2. In an alternative embodiment, temporary bonding layer TB2 may be omitted. The formation and/or materials of temporary bonding layer TB2 and temporary carrier TC2 are similar to the formation and/or materials of temporary bonding layer TB1 and temporary carrier TC1 depicted in fig. 2 and thus will not be described in detail herein. As shown in fig. 6, for example, the bottom surface 210B 'of the semiconductor die 10B' faces upward for subsequent processing.

Thereafter, for each of the semiconductor dies 10B ', a thinning process (e.g., etching, grinding, CMP process, or the like) is performed on the bottom surface 210B' of the semiconductor substrate 210 until the via 230 is exposed by the bottom surface 210B ″ of the semiconductor substrate 210, so as to form a thinned semiconductor die 10B ". For example, after semiconductor die 10B 'is attached to temporary bonding layer TB2, semiconductor die 10B' is thinned to form thinned semiconductor die 10B ", the thinned semiconductor die 10B" each having a thickness T3 in the range of approximately 5 μm to 100 μm. In some embodiments, thickness T3 is less than thickness T2. As shown in fig. 7, in some embodiments, in each of the thinned semiconductor dies 10B ", the bottom surface 230B of the via 230 is exposed by the bottom surface 210B" of the semiconductor substrate 210 in an accessible manner. For example, in each thinned semiconductor die 10B ", the bottom surface 230B of the via 230 is substantially flush and coplanar with the bottom surface 210B" of the semiconductor substrate 210. In each of the thinned semiconductor dies 10B ", when the semiconductor substrate 210 is a silicon substrate, the via 230 penetrating the semiconductor substrate 210 is referred to as a Through Semiconductor Via (TSV) or a through silicon via.

Referring to fig. 8, in some embodiments, thinned semiconductor die 10B "is recessed such that vias 230 protrude from semiconductor substrate 210. In other words, the semiconductor substrate 210 of each of the thinned semiconductor dies 10B "is partially removed to obtain a bottom surface 210B, and a portion of each of the vias 230 protrudes out of the bottom surface 210B of the semiconductor substrate 210. After the depression, in the cross-section shown in fig. 8, a plurality of depressions R1 are formed, wherein each of the depressions R1 is formed on the bottom surface 210b and between the protruding portions of two adjacent via holes 230. For example, the recesses R1 each have a depth D1 (as measured along the stacking direction Z) that ranges approximately from 0.5 μm to 1.5 μm.

During the recessing process, the semiconductor substrate 210 of each of the thinned semiconductor dies 10B "may be partially removed by etching. For example, the etching process has a high etch-rate selectivity (etch-rate selectivity) for the material of the semiconductor substrate 210 with respect to the material of the via hole 230 and the material of the temporary bonding layer TB 2. For example, the amount of removal of the semiconductor substrate 210 may be controlled by adjusting the etching time. In some embodiments, via 230 and temporary bonding layer TB2 may remain intact during recessing. The etching process may include dry etching, wet etching, or a combination thereof. In some embodiments, a cleaning process is performed using a suitable solvent, cleaning chemistry, or other cleaning technique to remove residues of the etching process.

Referring to fig. 9, in some embodiments, an isolation layer 50 is formed over temporary carrier TC2 and over thinned semiconductor die 10B ". In some embodiments, the isolation layer 50 includes a first lateral portion 50a, a second lateral portion 50b, and a connection portion 50 c. For example, as shown in fig. 9, a first lateral portion 50a is disposed on the temporary bonding layer TB2 and extends over the temporary bonding layer TB2, a second lateral portion 50b is disposed on and extends over the bottom surface 210b of the semiconductor substrate 210 and the bottom surface 230b and the sidewall 230s of the via hole 230, and a connection portion 50c is disposed on the first lateral portion 50a and extends to be in contact with the second lateral portion 50 b. In some embodiments, isolation layer 50 has a thickness T50 that ranges approximately from 0.5 μm to 1.6 μm, where thickness T50 is measured as the minimum distance between opposing sides of isolation layer 50. As shown in fig. 9, the second lateral portion 50b fills the recess R1. In one embodiment, the thickness T50 is greater than the depth D1, however the disclosure is not so limited. In an alternative embodiment, the thickness T50 is substantially equal to the depth D1. In other words, the isolation layer 50 is thick enough to cover the protruding portion of the via hole 230.

In some embodiments, the first lateral portion 50a and the second lateral portion 50b extend laterally, for example, along the direction X and/or the direction Y depicted in fig. 9. For example, direction X is different from direction Y, and direction X and direction Y are independently perpendicular to stacking direction Z. In some embodiments, the connecting portion 50c extends vertically to connect the first lateral portion 50a with the second lateral portion 50 b. For example, the connecting portion 50c may extend upward in a straight line form as shown in fig. 9. However, the connecting portion 50c may extend upward in a stepped form (e.g., the connecting portion 51c in fig. 15).

In some embodiments, the isolation layer 50 may be conformally formed over the temporary carrier TC2 by, for example, a spin-on, Chemical Vapor Deposition (CVD) process, or the like. In some embodiments, the material of the isolation layer 50 may include a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), or the like (e.g., silicon oxynitride, silicon carbide, polymer, or the like). Alternatively, a native oxide may be formed on the bottom surface 210B of the semiconductor substrate 210 of each of the thinned semiconductor dies 10B "prior to forming the isolation layer 50. As shown in fig. 9, for example, a portion of the via 230 protruding from the bottom surface 210b of the semiconductor substrate 210 is surrounded by the second lateral portion 50b of the isolation layer 50.

Referring to fig. 9 and 10 together, in some embodiments, the isolation layer 50 is partially removed to expose the via 230. In such an embodiment, the isolation layer 50 is patterned by a planarization process, wherein one first lateral portion 50a and the planarized connection portion 50 c' connected to the one first lateral portion 50a together constitute one isolation structure 50(0), and the second lateral portion 50b of the isolation layer 50 is planarized to form the isolation layer 240 disposed on the bottom surface 210 b. The planarization process may include, for example, a CMP process or the like. To this end, a carrier die 10B is fabricated. In some embodiments, the thicknesses T10B of the carrier die 10B each range approximately between 3 μm to 90 μm. In some embodiments, the thickness T10B is less than or substantially equal to the thickness T3. In the present disclosure, in semiconductor structure P1a, carrier dies 10B are each referred to as a base level 10B (0) of one die stack. It should be noted that various layers and features of the semiconductor die are omitted from the figure, and the carrier die 10B may include more elements formed therein to perform different functions.

In some embodiments, for each carrier die 10B as shown in fig. 10, the isolation layer 240 reveals the vias 230 in an accessible manner for further electrical connection. In some embodiments, the thickness T4 of isolation layer 240 of carrier die 10B ranges approximately from 0.3 μm to 1 μm. After the planarization process, a cleaning process may optionally be performed to clean and remove residues generated by the planarization process, for example. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method. In some embodiments, during the planarization of the isolation layer 50, the via 230 may also be planarized. In some embodiments, the thickness T50 of isolation layer 50 is greater than or substantially equal to the depth D1 of recess R1, and the thickness T4 of isolation layer 240 is less than or substantially equal to the depth D1 of recess R1.

In some embodiments, the bottom surface 240b of the isolation layer 240 is substantially flush with the bottom surface 230b of the via 230. That is, the bottom surface 240b of the isolation layer 240 is substantially coplanar with the bottom surface 230b of the via hole 230. In some embodiments, as shown in fig. 10, a portion of each of the via holes 230 protruding from the bottom surface 210b of the semiconductor substrate 210 is laterally covered by the isolation layer 240, and the bottom surface 230b of the via hole 230 is exposed by the isolation layer 240 in an accessible manner. In some embodiments, with such planarization, the carrier dies 10B are formed separated from each other by the isolation structures 50 (0). In the present disclosure, as shown, for example, in fig. 10, the carrier dies 10B each have a front surface S3 and a back surface S4 (e.g., bottom surface 240B), the back surface S4 being opposite the front surface S3.

Referring to fig. 11, in some embodiments, a first set of a plurality of semiconductor dies 10A "is provided, wherein these semiconductor dies 10A" are stacked on a semiconductor die 10B. For example, the semiconductor die 10A "and the carrier die 10B are fabricated separately as described in connection with fig. 1-4 and 5-10, respectively. In some embodiments, semiconductor die 10A "may be removed from tape frame TP1 (shown in fig. 4) using, for example, a pick and place process or other suitable attachment technique to mount semiconductor die 10A" on carrier die 10B. Semiconductor die 10A "may be tested prior to bonding such that only Known Good Die (KGD) are used for bonding. In the present disclosure, the semiconductor die 10A "and the carrier die 10B are bonded together in a face-to-back configuration. As shown in fig. 11, front surfaces S1 of semiconductor die 10A ″ respectively face back surfaces S4 of carrier die 10B, for example.

For illustration purposes, only one semiconductor die 10A "is shown disposed on one carrier die 10B in fig. 11; however, the number of semiconductor dies 10A "disposed on one carrier die 10B is not limited to the present disclosure. The number of semiconductor dies 10A "may be one or more than one based on design layout and requirements. For example, in an alternative embodiment, a plurality of semiconductor dies 10A "(see fig. 45) are disposed on one carrier die 10B.

In some embodiments, a bonding process is performed to bond the semiconductor die 10A "to the carrier die 10B. For example, as shown in fig. 11 and 26A (showing an enlarged cross-sectional view indicated by the dashed box (or dashed area) a shown in fig. 11), the bonding interface IF1 between one semiconductor die 10A ″ and the corresponding underlying carrier die 10B includes metal-to-metal bonding (e.g., copper-to-copper bonding) and dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding, oxide-to-nitride bonding, or nitride-to-nitride bonding). That is, the bonding process includes a hybrid bonding process. For example, the bond conductors 150 of semiconductor die 10A "and the vias 230 of carrier die 10B are bonded together by copper-to-copper bonds (referred to as direct metal-to-metal bonds), and the dielectric layer 140 (e.g., dielectric layer DI4) of semiconductor die 10A" and the isolation layer 240 of carrier die 10B are bonded together by oxide-to-nitride bonds (referred to as direct dielectric-to-dielectric bonds). In the present disclosure, the bonding interface IF1 may be referred to as a hybrid bonding interface.

It should be noted that the above joining method is merely an example and is not intended to be limiting. In some embodiments, as shown in fig. 26A, there is an offset between the sidewall 150SW of the joint conductor 150 and the sidewall 230SW of the via 230 located below the joint conductor 150. In other words, since the bonding conductor 150 has a larger bonding surface than the via hole 230, even if misalignment occurs, direct metal-to-metal bonding can be achieved, thereby exhibiting better reliability. In some embodiments where the size of the bond conductor 150 is smaller than the size of the corresponding via 230, the dielectric layer 140 of the semiconductor die 10A "immediately adjacent to the bond conductor 150 may be bonded to the portion of the via 230 of the carrier die 10B.

In some embodiments, the via 130 may taper (e.g., taper) from the interconnect structure 120 to the bottom surface 110b ″. Alternatively, as shown in fig. 11 and 26A, for example, the via 130 has substantially vertical (vertical) sidewalls. In a cross-sectional view along the stacking direction Z, the shape of the via 130 may depend on design requirements and is not intended to be limiting in this disclosure. On the other hand, in a top (plan) view on the X-Y plane, the shape of the via 130 may depend on design requirements, and may be a circular shape, an elliptical shape, a rectangular shape, a polygonal shape, or a combination thereof; the present disclosure is not limited thereto. Similar geometric specifications may also be applied to the vias 230 of the carrier die and therefore will not be described in detail herein.

For example, as shown in fig. 11 and 26A, each bond conductor 150 of one semiconductor die 10A "distributed at the front surface S1 is in physical and electrical contact with the respective one via 230 of the semiconductor die 10B located below the bond conductor 150. In some embodiments, such bond conductors 150 are in physical and electrical contact with corresponding metallization patterns MP overlying bond conductors 150, as shown in fig. 26A. However, the present disclosure is not limited thereto; in an alternative embodiment, such bond conductors 150 can be in physical and electrical contact with respective conductive pads AP overlying the bond conductors 150, as shown in fig. 26B.

Referring to fig. 12, in some embodiments, isolation structure 50(0) is removed from temporary carrier TC 2. For example, the isolation structure 50(0) may be removed by etching or the like; the present disclosure is not limited thereto. For example, the etching process may include dry etching, wet etching, or a combination thereof. In one embodiment, as shown in fig. 12, the isolation layer 240 of each carrier die 10B exposed by the overlying semiconductor die 10A "remains during the removal of the isolation structure 50 (0). However, in alternative embodiments, the isolation layer 240 of each carrier die 10B exposed by the overlying semiconductor die 10A "may be removed simultaneously during the removal of the isolation structures 50 (0).

Referring to fig. 12 and 13 together, in some embodiments, a thinning process (e.g., grinding, CMP, or the like) may be performed on the bottom surface 110b "of the semiconductor die 10A" to form a thinned semiconductor die 10A' ". In some embodiments, via 130 is exposed by bottom surface 110b '"of thinned semiconductor die 10A'". That is, after semiconductor die 10A "is bonded to carrier die 10B, semiconductor die 10A" is thinned to form thinned semiconductor die 10A '", thinned semiconductor die 10A'" having a thickness T5 approximately ranging from 40 μm to 200 μm. As shown in fig. 13, for example, in each of the thinned semiconductor dies 10A '", the bottom surface 130b of the via 130 is exposed by the bottom surface 110 b'" of the semiconductor substrate 110 in an accessible manner. For example, in each thinned semiconductor die 10A '″, the bottom surface 130b of the via 130 is substantially flush and coplanar with the bottom surface 110 b' ″ of the semiconductor substrate 110. In each of thinned semiconductor die 10A' ″, since via 130 extends through semiconductor substrate 110, when semiconductor substrate 110 is a silicon substrate, via 130 is referred to as a through-semiconductor via (TSV) or a through-silicon via.

Referring to fig. 14, in some embodiments, thinned semiconductor die 10A' ″ is recessed such that vias 130 protrude from semiconductor substrate 110. In other words, semiconductor substrate 110 of each of thinned semiconductor dies 10A' "is partially removed to obtain bottom surface 110b, and portions of each of vias 130 protrude out of bottom surface 110b of semiconductor substrate 110. After the recessing, in the cross-section shown in fig. 14, a plurality of recesses R2 are formed, wherein each of the recesses R2 is formed on the bottom surface 110b and between the protruding portions of two adjacent vias 130. For example, the recesses R2 each have a depth D2 (as measured along the stacking direction Z) that ranges approximately from 0.5 μm to 1.5 μm. The recessing process is similar to the process described in connection with fig. 8 and thus will not be described in detail herein.

Referring to fig. 15, in some embodiments, isolation layer 51 is formed over temporary carrier TC 2. In some embodiments, the isolation layer 51 includes a first lateral portion 51a, a second lateral portion 51b, and a connection portion 51 c. For example, as shown in fig. 15, the first lateral portion 51a is disposed on the temporary bonding layer TB2 and extends over the temporary bonding layer TB2, the second lateral portion 51b is disposed on the bottom surface 110b of the semiconductor substrate 110 and the bottom surface 130b and the sidewall 130s of the via 130 and extends over the bottom surface 110b of the semiconductor substrate 110 and the bottom surface 130b and the sidewall 130s of the via 130, and the connection portion 51c is disposed on the first lateral portion 51a and extends to be in contact with the second lateral portion 51 b. In some embodiments, isolation layer 51 has a thickness T51 that ranges approximately from 0.5 μm to 1.6 μm, where thickness T51 is measured as the minimum distance between opposing sides of isolation layer 51. As shown in fig. 15, the second lateral portion 51b fills the recess R2. In one embodiment, the thickness T51 is greater than the depth D2, however the disclosure is not so limited. In an alternative embodiment, the thickness T51 is substantially equal to the depth D2. In other words, the isolation layer 51 is thick enough to cover the protruding portion of each of the via holes 130. As shown in fig. 15, for example, the portion of the via 130 protruding from the bottom surface 110b of the semiconductor substrate 110 is surrounded by the second lateral portion 51b of the isolation layer 51.

In some embodiments, as shown in fig. 15, the first lateral portion 51a and the second lateral portion 51b extend laterally (e.g., in the direction X and/or the direction Y), and the connection portion 51c may extend upward in a stepped fashion (e.g., in the stacking direction Z in addition to the direction X and/or the direction Y). The formation and material of the isolation layer 51 may be the same as the formation process of the isolation layer 50 as described in fig. 9, and thus, will not be described in detail herein. In one embodiment, thickness T51 of isolation layer 51 may be the same as thickness T50 of isolation layer 50. In an alternative embodiment, the thickness T51 of isolation layer 51 may be different than the thickness T50 of isolation layer 50.

Referring to fig. 15 and 16 together, in some embodiments, the isolation layer 51 is partially removed to expose the via 130. In such an embodiment, the isolation layer 51 is planarized, wherein one first lateral portion 51a and the planarized connection portion 51 c' connected to the one first lateral portion 51a together constitute one isolation structure 50(1), and the second lateral portion 51b of the isolation layer 51 is planarized to form the isolation layer 160 disposed on the bottom surface 110 b. The planarization process may include performing by, for example, a CMP process or the like. Thus, a semiconductor die 10A is fabricated. In some embodiments, thickness T10A of semiconductor die 10A ranges approximately from 3 μm to 50 μm. In some embodiments, the thickness T10A is less than or substantially equal to the thickness T5. In the present disclosure, in semiconductor structure P1a, semiconductor die 10A is referred to herein as the first level 10A (1) of the die stack. It should be noted that various layers and features of the semiconductor die are omitted from the figure, and the semiconductor die 10A may include more elements formed therein to perform different functions.

In some embodiments, as shown in fig. 16, the isolation layer 160 reveals the vias 130 in an accessible manner for further electrical connection. In some embodiments, the thickness T6 of isolation layer 160 ranges approximately from 0.3 μm to 1 μm. After the planarization process, a cleaning process may optionally be performed to clean and remove residues generated by the planarization process, for example. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method. In some embodiments, during the planarization of the isolation layer 51, the via 130 may also be planarized. In some embodiments, the thickness T51 of isolation layer 51 is greater than or substantially equal to the depth D2 of recess R2, and the thickness T6 of isolation layer 160 is less than or substantially equal to the depth D2 of recess R2.

In some embodiments, the bottom surface 160b of the isolation layer 160 is substantially flush with the bottom surface 130b of the via 130. That is, the bottom surface 160b of the isolation layer 160 is substantially coplanar with the bottom surface 130b of the via 130. In some embodiments, as shown in fig. 16, a portion of each of the via holes 130 protruding from the bottom surface 110b of the semiconductor substrate 110 is laterally covered by the isolation layer 160, and the bottom surface 130b of the via hole 130 is exposed by the isolation layer 160 in an accessible manner. In some embodiments, with such planarization, the semiconductor dies 10A are formed separated from one another by the isolation structures 50 (1). In the present disclosure, as shown in fig. 16, for example, semiconductor dies 10A each have a front surface S1 and a back surface S2 (e.g., bottom surface 160b), back surface S2 being opposite front surface S1. That is, for example, front surfaces S1 of semiconductor die 10A (e.g., first level 10A (1) of the die stack) respectively face and are bonded to back surfaces S4 of carrier die 10B (e.g., base level 10B (0) of the die stack).

Referring to fig. 17, in some embodiments, a second set of a plurality of semiconductor dies 10A "is provided and these semiconductor dies 10A" are stacked on the semiconductor dies 10A of the first tier 10A (1), respectively. In the present disclosure, each semiconductor die 10A "(from the second group) is disposed on one of the semiconductor dies 10A of the first level 10A (1) in a face-to-back configuration for forming a second level of the die stack (e.g., 10A (2) depicted in fig. 18). For example, front surfaces S1 of semiconductor die 10A "(from the second group) respectively face back surfaces S2 of semiconductor die 10A of first level 10A (1). Similar to the process as set forth in fig. 11, semiconductor die 10A "may be tested before semiconductor die 10A" is removed from tape frame TP1 (shown in fig. 4) for mounting on semiconductor die 10A of first level 10A (1) and before bonding, such that only Known Good Die (KGD) are used for bonding.

In some embodiments, the bonding process is performed by hybrid bonding to bond the semiconductor die 10A ″ to the semiconductor die 10A. For example, as shown in fig. 17 and 27A (showing an enlarged cross-sectional view indicated by the dashed box (or dashed area) B shown in fig. 17), a bond interface IF2 between one semiconductor die 10A ″ and a corresponding underlying semiconductor die 10A includes a metal-to-metal bond (e.g., a copper-to-copper bond) and a dielectric-to-dielectric bond (e.g., an oxide-to-oxide bond, an oxide-to-nitride bond, or a nitride-to-nitride bond). For example, bond conductor 150 of semiconductor die 10A "and via 130 of semiconductor die 10A are bonded together by a copper-to-copper bond (referred to as a direct metal-to-metal bond), and dielectric layer 140 of semiconductor die 10A" (e.g., dielectric layer DI4) and isolation layer 160 of semiconductor die 10A are bonded together by an oxide-to-nitride bond (referred to as a direct dielectric-to-dielectric bond). In the present disclosure, the interface IF2 may be referred to as a hybrid interface.

It should be noted that the above joining method is merely an example and is not intended to be limiting. As shown in fig. 27A, for example, there is an offset between the sidewall 150SW of the bonding conductor 150 and the sidewall 130SW of the via 130 located below the bonding conductor 150. In other words, since the bonding conductor 150 has a larger bonding surface than the via hole 130, even if misalignment occurs, direct metal-to-metal bonding can be achieved, thereby exhibiting better reliability. In some embodiments where the size of the bond conductor 150 is smaller than the size of the corresponding via 130, the dielectric layer 140 of the semiconductor die 10A "immediately adjacent to the bond conductor 150 may be further bonded to portions of the via 130 of the semiconductor die 10A, such as a metal-to-dielectric bond.

As shown in fig. 17 and 27A, for example, each bond conductor 150 of one semiconductor die 10A "distributed at the front surface S1 is in physical and electrical contact with the respective one via 130 of the semiconductor die 10A located below the bond conductor 150. In some embodiments, such bond conductors 150 are in physical and electrical contact with a corresponding metallization pattern MP overlying bond conductors 150, as shown in fig. 27A. However, the present disclosure is not limited thereto; in an alternative embodiment, referring to fig. 27B, such bond conductors 150 can be in physical and electrical contact with respective conductive pads AP overlying the bond conductors 150.

Referring to fig. 18, in some embodiments, the steps set forth in fig. 12-17 are repeated to form a plurality of die stacks 100 over a plurality of carrier dies 10B in base level 10B (0). As shown in fig. 18, one die stack 100 is disposed on one carrier die 10B. In some embodiments, the die stacks 100 each include a topmost tier 10A (t), wherein the topmost tier 10A (t) includes the semiconductor die 10A "depicted in fig. 4. It should be understood that the symbol T indicates the number of levels for each die stack 100, and the die stacks 100 respectively disposed on the base level 10B (0) may each include any number of levels. For example, T is an integer greater than 1. For example, as shown in fig. 18, the semiconductor die 10A ″ has vias 130 that are not exposed. In some embodiments, in each of the die stacks 100, the semiconductor die 10A "in the topmost level 10A (T) is thicker than any of the underlying semiconductor dies 10A of the interior levels (e.g., 10A (1) to 10A (T-1)). For example, the thickness T2 of the semiconductor die 10A "of the topmost tier 10A (T) is greater than the thickness T10A of one tier of other semiconductor dies 10A in the interior tiers (e.g., 10A (1) through 10A (T-1)).

For example, in each die stack 100, the semiconductor die 10A at the second level 10A (2) is fabricated by performing the method described in connection with fig. 13-16 on the structure depicted in fig. 17, and thus the semiconductor die 10A at the first level 10A (1) and the second level 10A (2) may be similar or identical in configuration, function, and nature. That is, the semiconductor die 10A at the first level 10A (1) through the (T-1) th level 10A (T-1) of each die stack 100 may be similar or identical in configuration, function, and nature due to the use of similar formation steps. For example, the die stacks 100 each have sidewalls 100S with a planar surface. In some embodiments, along direction X, the width W10B of each carrier die 10B is greater than the width W100 of (each semiconductor die 10A/10A "of) each die stack 100. As shown in fig. 18, in some embodiments, there is an offset between the sidewall 100S of one die stack 100 and the sidewall S5 (see fig. 19) of the carrier die 10B located below the one die stack 100.

In some embodiments, the semiconductor dies (e.g., 10A and 10A ") in levels (e.g., such as interior levels 10A (1)/10A (2). 10A (T-1) and topmost level 10A (T), etc.) may be tested prior to bonding such that only Known Good Dies (KGDs) are used to form the die stack 100, increasing manufacturing yield. In some embodiments where the semiconductor die (e.g., 10A and 10A ") are memory dies, because the semiconductor dies are vertically stacked and bonded, the die stack 100 may enable faster inter-memory communication during operation, which in turn may increase data bandwidth and enable faster data access and data storage. In some embodiments, during operation, the semiconductor die at the first tier 10A (1) may help manage data storage and data format interoperability between respective semiconductor die at other tiers (e.g., 10A (2) to 10A (T-1) and 10A (T)) stacked on the semiconductor die and/or the carrier die 10B at the base tier 10B (0).

In some embodiments, the semiconductor dies (e.g., 10A and 10A ") of the die stack 100 are vertically stacked and bonded by hybrid bonding. For example, for every two adjacent levels of one die stack 100, the upper level is bonded to the lower level in a face-to-back configuration. In some embodiments, as shown in fig. 18, the front surface S1 of the second level 10A (2) is joined to the back surface S2 of the first level 10A (1). With this bonding (without using any other external connections), there is no gap between the die at two adjacent stacked levels, thus achieving a semiconductor structure P1a with a better form factor and a higher density of die stacks in the device. As shown in fig. 18, for example, the die stacks 100 are separated and isolated from each other by the isolation structures 50(T-1), and the carrier dies 10B are also separated and isolated from each other by the isolation structures 50 (T-1).

Referring to FIG. 19, in some embodiments, isolation structure 50(T-1) is removed from temporary carrier TC 2. For example, the isolation structure 50(T-1) may be removed by etching or the like; the present disclosure is not limited thereto. The etching process is similar to the step set forth in fig. 12 and therefore will not be described in detail herein. That is, for example, the die stacks 100 are separated and isolated from each other by gaps, and the carrier dies 10B are also separated and isolated from each other by gaps.

As shown in fig. 19 and 28A, which show enlarged cross-sectional views indicated by dashed boxes (or dashed areas) C shown in fig. 19, at least one of the semiconductor substrates 110 of the semiconductor die 10A in an interior level, e.g., 10A (1) through 10A (T-1), may have a rounded edge (rounded edge) RE. For example, for each of semiconductor dies 10A, rounded edge RE is connected to bottom surface 110b and sidewalls 110s of semiconductor substrate 110. In some embodiments, the dielectric layer 140 of the semiconductor die 10A at the second level 10A (2) is a substantially flat surface such that a gap is formed between the rounded edge RE of the semiconductor die 10A at the first level 10A (1) and the dielectric layer 140 of the semiconductor die 10A at the second level 10A (2). For such embodiments, the gaps may be filled in successive steps by later formed layers/elements, such as dielectric layers, conductive layers, or layers having at least one dielectric layer and at least one conductive layer. That is, the rounded edge RE may be covered by a later formed layer/element. The present disclosure is not limited thereto. In alternative embodiments, the gap may not be filled and the rounded edge RE may not be covered by any layer/element. In some embodiments, the rounded edge RE is formed during the backside thinning process (e.g., the step set forth in connection with fig. 13). For example, a grinding pad (grinding pad) in contact with the edge of the semiconductor die rounds the edge of the semiconductor die. By rounding the formation of the edge RE, the semiconductor die 10A may dissipate stress in the edge/corner regions caused by mechanical/thermal stress and bonding, thereby preventing cracking (cracking).

In other embodiments, as shown in fig. 28B, the rounded edge RE may BE replaced by a bevel edge (bevel edge) BE, wherein the bevel edge BE is connected to the bottom surface 110B and the sidewall 110s of the semiconductor substrate 110. In some embodiments, the dielectric layer 140 of the semiconductor die 10A at the second level 10A (2) is a substantially flat surface such that a gap is formed between the bevel edge BE of the semiconductor die 10A at the first level 10A (1) and the dielectric layer 140 of the semiconductor die 10A at the second level 10A (2). For such embodiments, the gaps may be filled in successive steps by later formed layers/elements, such as dielectric layers, conductive layers, or layers having at least one dielectric layer and at least one conductive layer. That is, the bevel edge BE may BE covered by a later formed layer/element. However, in alternative embodiments, the gap may not BE filled and the bevel edge BE may not BE covered by any layer/element. In some embodiments, the bevel edge BE is formed by a singulation mark formed at the dicing lane for a singulation process (e.g., the steps set forth in connection with fig. 4). For example, the singulation marks used to indicate the boundaries of the semiconductor die tilt the edges of the semiconductor die. By the formation of the bevel edge BE, the semiconductor die 10A may dissipate stress in the edge/corner regions caused by mechanical/thermal stress and bonding, thereby preventing cracking.

In still other embodiments, as shown in fig. 28C, the bottom surface 110b and the sidewall 110s of the semiconductor substrate 110 may be directly connected at a sharp edge (sharp edge) SE. In such an embodiment, no gap is formed between the sharp edge SE of the semiconductor die 10A at the first level 10A (1) and the dielectric layer 140 of the semiconductor die 10A at the second level 10A (2). In some embodiments, the sharp edge SE may or may not be covered by any layer/element.

As shown in fig. 19 and 29A (showing an enlarged cross-sectional view indicated by a dashed box (or dashed area) D shown in fig. 19), the semiconductor substrate 110 of the semiconductor die 10A ″ at the topmost level 10A (t) may have a bevel edge BE. For example, for semiconductor die 10A, the bevel edge BE is connected to the bottom surface 110b "and the sidewalls 110s of the semiconductor substrate 110. For such an embodiment, the bevel edge BE may BE covered in successive steps by later formed layers/elements, such as dielectric layers, conductive layers or layers having at least one dielectric layer and at least one conductive layer. The present disclosure is not limited thereto. In an alternative embodiment, the bevel edge BE may not BE covered by any layer/element.

However, the present disclosure is not limited thereto. In other embodiments, as shown in fig. 29B, the bottom surface 110B ″ of the semiconductor substrate 110 and the sidewall 110s may be directly connected at the sharp edge SE. In some embodiments, the sharp edge SE may or may not be covered by any layer/element.

Referring to fig. 20, in some embodiments, an electromagnetic interference shielding material (electromagnetic interference shielding material)60A is disposed over the temporary carrier TC2, the electromagnetic interference shielding material 60A being disposed on the die stack 100 and the carrier die 10B of the base level 10B (0). In some embodiments, the electromagnetic interference shielding material 60A conformally covers the die stack 100 and the carrier die 10B of the base level 10B (0). In some embodiments, the EMI shielding material 60A has a range approximately between

To

Thickness T60, wherein thickness T60 is measured as the minimum distance between the opposing sides of emi shielding material 60A. For example, the electromagnetic interference shielding material 60A covers at least the sidewalls 100S and the bottom surface 100B of the die stack 100, and further covers portions of the sidewalls S5 and the back surface S4 of the carrier die 10B of the base level 10B (0).

In some embodiments, the electromagnetic interference shielding material 60A may be made of a conductive material. The material for the electromagnetic interference shielding material 60A may include copper, nickel, an alloy of nickel and iron, an alloy of copper and nickel, silver, etc., but is not limited thereto. In some embodiments, the electromagnetic interference shielding material 60A may be fabricated using electrolytic plating, electroless plating, sputtering, Physical Vapor Deposition (PVD), chemical vapor deposition, or other suitable metal deposition process. If desired, a patterning process may optionally be performed to expose portions of temporary bonding layer TB 2. The patterning process may include an etching process such as dry etching, wet etching, or a combination thereof.

Referring to fig. 21, in some embodiments, after formation of emi shielding material 60A, insulative material 20' is formed over temporary carrier TC2 to encapsulate emi shielding material 60A, die stack 100, and carrier die 10B. For example, the insulating material 20' may be a molding compound, epoxy, the like, or other suitable electrically insulating material, and may be applied by compression molding, transfer molding, or the like. In some embodiments, the emi shielding material 60A, the die stack 100, and the carrier die 10B are overmolded, and then the insulating material 20' is thinned using, for example, grinding, Chemical Mechanical Polishing (CMP), a combination thereof, or other suitable thinning process to reduce the overall thickness of the structure. For example, the bottom surface 100b of the die stack 100 (e.g., the bottom surface 110b "of the semiconductor die 10A") is exposed by the insulating material 20' after thinning.

In some embodiments, during the thinning of the insulating material 20', the EMI shielding material 60A is also patterned to form the EMI shielding layer 60. In some embodiments, a thinning step may be performed, for example, on the overmolded insulating material 20 'to flush the surface 20b of the insulating material 20', the bottom surface 100b of the die stack 100 (e.g., the bottom surface 110b of the semiconductor die 10A "), and the surface S60 of the electromagnetic interference shield layer 60. For example, surface 20b of insulating material 20', bottom surface 100b of die stack 100 (e.g., bottom surface 110b of semiconductor die 10A "), and surface S60 of electromagnetic interference shield layer 60 are substantially flush with one another. In other words, surface 20b of insulating material 20' is substantially coplanar with bottom surface 100b of die stack 100 (e.g., bottom surface 110b of semiconductor die 10A ") and surface S60 of emi shielding layer 60. As shown in fig. 21, for example, the electromagnetic interference shielding layer 60 does not extend over the bottom surface 100B of the die stack 100 (e.g., the bottom surface 110B of the semiconductor die 10A "), and the carrier die 10B and the die stack 100 disposed on the carrier die 10B are separated from the insulating material 20' by the electromagnetic interference shielding layer 60.

Insulating material 20' may include a low moisture absorption rate (moisture absorption rate) and may be rigid after curing for protecting emi shielding layer 60, die stack 100, and carrier die 10B. The electromagnetic interference shield layer 60 is used to reduce or suppress an electromagnetic field in a space by blocking the electromagnetic field using a barrier made of a conductive material or a magnetic material. In some embodiments, the EMI shielding layer 60 may reduce coupling of radio waves, electromagnetic fields, and electrostatic fields, for example. In some embodiments, the EMI shield 60 may be in electrical contact with a ground (not shown) to make electrical ground.

In some embodiments, semiconductor substrate 110 of semiconductor die 10A "may also be patterned during thinning of insulating material 20', although the disclosure is not limited thereto. In other embodiments, the thinning process may be omitted and the emi shielding material 60A, the die stack 100, and the carrier die 10B are buried or covered by the insulating material 20'. In such an embodiment, the EMI shielding material 60A acts as an EMI shielding layer and is in electrical contact with a ground (not shown) to be electrically grounded.

Referring to fig. 22, in some embodiments, another temporary carrier TC3 is optionally fitted to insulation 20' opposite temporary carrier TC 2. In some embodiments in which insulating material 20 'is thinned to expose semiconductor die 10A "at topmost level 10A (t), temporary carrier TC3 is bonded to insulating material 20' (e.g., surface 20b) and bottom surface 100b of die stack 100 (e.g., bottom surface 110 b" of semiconductor die 10A ") by temporary bonding layer TB 3. A lift-off process may be performed in which the temporary carrier TC2 and the temporary bonding layer TB2 are released from the carrier die 10B at the base level 10B (0), thereby exposing the front surface S3 of the carrier die 10B and the surface 20a of the insulating material 20'. For example, along the stacking direction Z, a surface 20a of the insulating material 20 'is opposite to a surface 20b of the insulating material 20'. In some embodiments, the front surface S3 of carrier die 10B is cleaned for further processing after stripping off temporary carrier TC 2. The lift-off process has been described in fig. 4 and, therefore, for simplicity, is not described in detail herein.

Referring to fig. 23, in some embodiments, after removal of the temporary carrier TC2 and the temporary bonding layer TB2, a plurality of conductive terminals 30 are subsequently formed at the exposed front surface S3 of the carrier die 10B. The conductive terminals 30 may be formed using, for example, sputtering, printing, plating, deposition, or the like. The conductive terminal 30 may be formed of a conductive material including copper, aluminum, gold, nickel, silver, palladium, tin, solder, metal alloys, the like, or combinations thereof. For example, each of the conductive terminals 30 includes a bump 31. The bumps 31 may be micro-bumps, metal posts, bumps formed by electroless nickel-palladium immersion gold (ENEPIG), controlled collapse chip connection (C4) bumps, Ball Grid Array (BGA) bumps, or the like. In embodiments where the bumps 31 are micro-bumps, the bump pitch between two adjacent bumps 31 ranges from about 35 μm to about 55 μm. The bumps 31 may be solderless and may have substantially vertical (upright) sidewalls. In some embodiments, each of the conductive terminals 30 includes a metal cap 32 formed on top of a bump 31 by, for example, plating, printing, or similar process. For example, the material of the metal cap 32 includes nickel, tin-lead, gold, silver, palladium, nickel-palladium-gold, nickel-gold, the like, or any combination of these.

In some embodiments, prior to forming the conductive terminals 30, as shown in fig. 23, the protective layer 70 is formed at the base level 10B (0) of the die stack 100. In some embodiments, protective layer 70 is disposed on carrier die 10B and insulating material 20 'and extends to cover front surface S3 of carrier die 10B and surface 20a of insulating material 20'. In other words, the protective layer 70 is in contact with the insulating material 20' and the carrier die 10B. For example, the protective layer 70 includes a passivation material such as silicon oxide, silicon nitride, undoped silicate glass, polyimide, or other suitable insulating material for protecting underlying structures. In some embodiments, the protective layer 70 includes a plurality of openings OP that expose at least portions of underlying conductive features (not shown) in the interconnect structure 220 of each of the carrier dies 10B for further electrical connection. For example, as shown in fig. 23, the conductive terminals 30 are formed to be in physical and electrical contact with the conductive features in the interconnect structure 220 of the carrier die 10B exposed through the opening OP formed in the protective layer 70.

Alternatively, the protective layer 70 may be omitted, and the present disclosure is not limited thereto. In such an embodiment, the conductive terminals 30 are formed directly on the carrier die 10B to make physical and electrical contact with the conductive features in the interconnect structure 220 of the carrier die 10B.

Alternatively, the protective layer 70 may be replaced with a redistribution routing structure (not shown) comprising one or more dielectric layers and one or more metallization layers arranged alternately. In such an embodiment, the conductive terminal 30 is formed on the redistribution routing structure to electrically contact the conductive feature in the interconnect structure 220 of the carrier die 10B through a metallization layer in the redistribution routing structure.

Referring to fig. 24, in some embodiments, temporary carrier TC3 and temporary bonding layer TB3 are removed from insulating material 20' and die stack 100 by a lift-off process. For example, the lift-off process includes applying energy to the temporary bonding layer, mechanical peeling, etching, or other suitable removal technique. Subsequently, a singulation process is performed to form a plurality of separated respective semiconductor structures P1 a. Singulation may be performed along dicing lanes (not shown) by, for example, sawing, laser dicing, or similar processes. The insulating material 20' may be cut through to form an insulating enclosure 20. The insulating encapsulant 20 exposes the bottom surface 100b of the die stack 100 exposed by the emi shielding layer 60 and is disposed at the portions of the sidewalls 100S of the die stack 100 and the sidewalls S5 and the back surface S4 of the carrier die 10C covered by the emi shielding layer 60.

In some embodiments, as shown in fig. 24, the semiconductor structure P1a has a carrier die 10B, a die stack 100 disposed on the carrier die 10B, an insulating encapsulant 20 formed over the carrier die 10B and the die stack 100, an electromagnetic interference shielding layer 60 sandwiched between the insulating encapsulant 20 and the carrier die 10B and between the insulating encapsulant 20 and the die stack 100, a protective layer 70 disposed over the carrier die 10B and the insulating encapsulant 20, and conductive terminals 30 disposed over the insulating encapsulant 20. In some embodiments, the carrier die 10B is, for example, a logic die configured to perform read, program, erase, and/or other operations, and the die stack 100 is, for example, a memory stack including memory dies stacked on one another and programmed by the carrier die 10B. In some embodiments, semiconductor structure P1a is referred to as a (semiconductor) device package. For example, the semiconductor die 10A/10A "in the die stack 100 of the semiconductor structure P1a may be a High Bandwidth Memory (HBM) die, and the carrier die 10B may be a logic die that provides control functions for these memory dies. In other words, the semiconductor die 10A/10A "and the carrier die 10B in the die stack 100 are bonded together by hybrid bonding, and are electrically connected and in electrical communication with each other. Other types of dies may be employed in semiconductor structure P1a depending on product requirements. In this disclosure, die stack 100, along with carrier die 10B, is referred to as a stack structure SS 1.

In some embodiments, after singulation, the sidewalls S5 of the carrier die 10B covered by the electromagnetic interference shield layer 60 are further covered by the insulating encapsulant 20. For example, the sidewalls 20S of the insulating encapsulation 20 may be substantially flush with the sidewalls 70S of the protection layer 70 after singulation. That is, the sidewalls 20S of the insulating encapsulation 20 are aligned with the sidewalls 70S of the protection layer 70. In some embodiments, as shown in fig. 24, the sidewalls 100S of the die stack 100 are distal to the sidewalls 20S of the insulating encapsulant 20, and the sidewalls S5 of the carrier die 10B are also distal to the sidewalls 20S of the insulating encapsulant 20.

As shown in fig. 24 and fig. 25 (top plan view on the X-Y plane), for semiconductor structure P1a, the positioning location of die stack 100 is within the positioning location of carrier die 10B and within the positioning location of insulating encapsulant 20, and the positioning location of carrier die 10B is within the positioning location of insulating encapsulant 20. In other words, the perimeter of the die stack 100 is smaller than the perimeter of the carrier die 10B and the perimeter of the insulating encapsulant 20, and the perimeter of the carrier die 10B is smaller than the perimeter of the insulating encapsulant 20.

However, the present disclosure is not limited thereto. Fig. 30-44 are schematic cross-sectional views respectively illustrating semiconductor structures according to some embodiments of the present disclosure. For ease of understanding, like elements are designated with like reference numerals and are not described in detail herein.

In alternative embodiments, additional insulating enclosures may be included. The semiconductor structure P1b illustrated in fig. 30 is similar to the semiconductor structure P1a illustrated in fig. 24, except that the semiconductor structure P1b further includes an insulating encapsulant 40. For example, as shown in fig. 30, the insulating encapsulant 40 is at least between the passivation layer 70 and the insulating encapsulant 20. In some embodiments, insulating encapsulant 40 is formed prior to forming insulating encapsulant 20 such that insulating encapsulant 40 further covers sidewalls S5 of carrier die 10B covered by emi shielding layer 60. For example, the insulating encapsulant 40 not only further covers the portion of the back surface S4 of the carrier die 10B exposed by the die stack 100 and covered by the emi shielding layer 60, but also covers the portion of the sidewalls 100S of the die stack 100 covered by the emi shielding layer 60. That is, the insulating encapsulant 40 is further partially located between the insulating encapsulant 20 and the carrier die 10B. As shown in fig. 30, for example, the sidewalls 20S of the insulating encapsulant 20 and the sidewalls 70S of the protection layer 70 are substantially coplanar and aligned with the sidewalls 40S of the insulating encapsulant 40.

In some embodiments, the insulating encapsulant 40 may be conformally formed by, for example, spin coating, deposition, or similar process. In some embodiments, the material of the insulating encapsulation 40 may include a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), or the like (e.g., silicon oxynitride, silicon carbide, polymer, or the like). The present disclosure is not particularly limited. In the present disclosure, the insulating encapsulation 40 is different from the insulating encapsulation 20.

In yet another alternative embodiment, referring to semiconductor structure P1c depicted in fig. 31, insulating encapsulant 20 is replaced with insulating encapsulant 40. The semiconductor structure P1c illustrated in fig. 31 is similar to the semiconductor structure P1a illustrated in fig. 24, except that the semiconductor structure P1c employs an insulating encapsulant 40 instead of the insulating encapsulant 20. For example, the insulating encapsulation 40 completely covers the electromagnetic interference shield layer 60. As shown in fig. 31, for example, the sidewalls 70S of the protection layer 70 are substantially coplanar and aligned with the sidewalls 40S of the insulating encapsulant 40.

In other alternative embodiments, referring to semiconductor structure P1d depicted in fig. 32, no insulating encapsulant (e.g., 20, 40) is present. The semiconductor structure P1d depicted in fig. 32 is similar to the semiconductor structure P1a depicted in fig. 24, except that the die stack 100 and the carrier die 10B are covered only by the emi shielding layer 60. As shown in fig. 32, for example, the sidewall 70S of the protective layer 70 is substantially coplanar and aligned with a side of the portion of the emi shielding layer 60 that is located on the sidewall S5 of the carrier die 10B.

In some embodiments, the semiconductor structures P2a through P2d illustrated in fig. 33 through 36 may each include an isolation structure (e.g., 50(T-1) illustrated in fig. 18) therein, as compared to the semiconductor structures P1a through P1 d. For example, the semiconductor structure P2a depicted in fig. 33 is similar to the semiconductor structure P1a depicted in fig. 24, except that in the semiconductor structure P2a, the isolation structure 50(T-1) remains on the carrier die 10B and the die stack 100. As shown in fig. 33, isolation structure 50(T-1) covers portions of sidewalls 100S of die stack 100, sidewalls S5 of carrier die 10B, and back surface S4 of carrier die 10B exposed by die stack 100. For example, the isolation structure 50(T-1) is located between the die stack 100/carrier die 10B and the insulating encapsulant 20. As shown in FIG. 33, a protective layer 70 is located over the carrier die 10B, isolation structure 50(T-1), EMI shielding layer 60, and insulating encapsulant 20, and the sidewalls of the interior levels (e.g., 10A (1) through 10A (T-1)) are covered by the isolation structure 50 (T-1). Similarly, as shown in fig. 34 to 36, isolation structures may also be introduced into the semiconductor structures P1b, P1c and P1d to form semiconductor structures P2b, P2c and P2d, respectively.

On the other hand, in some embodiments, the semiconductor structures P3a to P3d illustrated in fig. 37 to 40, respectively, may not include an electromagnetic interference shielding element (e.g., 60 or 60A) therein, as compared to the semiconductor structures P2a to P2 d.

In some embodiments, the semiconductor structures P4a through P4d illustrated in fig. 41 through 44, respectively, may not include emi shielding elements (e.g., 60 or 60A) therein, as compared to the semiconductor structures P1a through P1 d. The semiconductor structure P4a depicted in fig. 41 is similar to the semiconductor structure P1a depicted in fig. 24, except that in the semiconductor structure P4a, the emi shielding layer 60 is removed from the carrier die 10B and the die stack 100. As shown in fig. 41, the sidewalls 100S of the die stack 100, the sidewalls S5 of the carrier die 10B, and the back surface S4 of the carrier die 10B exposed by the die stack 100 are in physical contact with the insulating encapsulant 20. Similarly, as shown in fig. 41 to 44, the emi shielding elements may also be removed from the semiconductor structures P1b, P1c and P1d to form semiconductor structures P4b, P4c and P4d, respectively.

Fig. 45 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure. Fig. 46A and 46B are schematic top views respectively showing relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure. For ease of understanding, like elements are designated with like reference numerals and are not described in detail herein. For example, fig. 45 is a schematic cross-sectional view of semiconductor structure P5 taken along cross-sectional line II-II depicted in fig. 46A.

The semiconductor structure P5 illustrated in fig. 41 is similar to the semiconductor structure P1a illustrated in fig. 24, except that in the semiconductor structure P4a, a plurality of die stacks 100 are disposed on one base level 10B (0). In other words, in semiconductor structure P5, a plurality of semiconductor dies (e.g., 10A and 10A ") are disposed on one carrier die 10B. In some embodiments, the die stack 100 is bonded to the carrier die 10B at the base level 10B (0) in a face-to-back configuration by hybrid bonding. Together, die stack 100 and carrier die 10B are referred to as a stack structure SS2 in this disclosure.

As shown in fig. 45 and 46A, for example, the die stacks 100 are arranged on the carrier die 10B in a matrix, such as an N × N or N × M array (N, M >0, N may or may not be equal to M). The array size of the die stack 100 may be specified and selected based on requirements and is not limited to the present disclosure. In some embodiments, the die stacks 100 are arranged in a 1 x 3 array as depicted in fig. 46A. However, the present disclosure is not limited thereto; in an alternative embodiment, the die stacks 100 may be arranged in a 2 x 2 array as depicted in fig. 46B.

In some embodiments, for semiconductor structure P5, the positioning location of die stack 100 is within the positioning location of carrier die 10B and within the positioning location of insulating encapsulant 20, and the positioning location of carrier die 10B is within the positioning location of insulating encapsulant 20. In other words, the carrier die 10B and the insulating encapsulant 20 overlap the plurality of die stacks 100 arranged side-by-side.

Fig. 47 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure. Fig. 48A and 48B are schematic top views respectively showing relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure. For ease of understanding, like elements are designated with like reference numerals and are not described in detail herein. For example, fig. 47 is a schematic cross-sectional view of semiconductor structure P6 taken along cross-sectional line III-III shown in fig. 48A.

The semiconductor structure P6 illustrated in fig. 47 is similar to the semiconductor structure P1a illustrated in fig. 24, except that the semiconductor structure P4a includes a plurality of stacked structures SS1 (illustrated in fig. 24). As shown in fig. 47 and 48A, for example, stacked structures SS1 are arranged side-by-side in a matrix, such as in an N × N or N × M array (N, M >0, N may or may not be equal to M). The array size of stacked structure SS1 may be specified and selected based on requirements and is not limited by the present disclosure. In some embodiments, stacked structures SS1 are arranged in a 1 x 3 array as depicted in fig. 48A. However, the present disclosure is not limited thereto; in an alternative embodiment, stacked structures SS1 may be arranged in a 2 x 2 array as depicted in fig. 48B.

As shown in fig. 47 and fig. 48 (top plan view on the X-Y plane), for semiconductor structure P6, the positioning location of each die stack 100 is within the positioning location of each carrier die 10B and within the positioning location of insulating encapsulant 20, and the positioning location of each carrier die 10B is within the positioning location of insulating encapsulant 20. In other words, the perimeter of each die stack 100 is less than the perimeter of each carrier die 10B and the perimeter of the insulating encapsulant 20, and the perimeter of each carrier die 10B is less than the perimeter of the insulating encapsulant 20.

In addition, stacked structure SS1 may be partially or entirely replaced by stacked structure SS2 depicted in fig. 45. The present disclosure is not limited thereto.

Fig. 49-56 are schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. Fig. 57 is a schematic top view showing relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure. For example, fig. 49 is a schematic cross-sectional view of semiconductor structure P7 taken along cross-sectional line IV-IV shown in fig. 57. For ease of understanding, like elements are designated with like reference numerals and are not described in detail herein.

Referring to fig. 49, in some embodiments, a semiconductor wafer W2 is provided. In some embodiments, the semiconductor wafer W2 includes a plurality of semiconductor dies 10B' connected to one another. Details of semiconductor die 10B' are already set forth in fig. 5 and, therefore, are not repeated herein for simplicity. For example, each of the semiconductor dies 10B' may comprise an integrated circuit device (e.g., a logic die, a memory die, a radio frequency die, a power management die, a microelectromechanical system (MEMS) die, the like, or a combination of these).

Referring to fig. 50, in some embodiments, a semiconductor wafer W2 is disposed on a temporary carrier TC4 through a temporary bonding layer TB 4. In some embodiments, a temporary bonding layer TB4 is deposited on temporary carrier TC4, and semiconductor wafer W2 is bonded to temporary carrier TC4 by temporary bonding layer TB4 by placing front surface S3 of semiconductor die 10B' in contact with temporary bonding layer TB 4. Alternatively, temporary bonding layer TB4 may be omitted. The formation and/or materials of temporary bonding layer TB4 and temporary carrier TC4 are similar to the formation and/or materials of temporary bonding layer TB1 and temporary carrier TC1 illustrated in fig. 2 and thus will not be described in detail herein. As shown in fig. 50, for example, the bottom surface 210B 'of the semiconductor die 10B' faces upward for subsequent processing.

Referring to fig. 51, in some embodiments, semiconductor wafer W2 is processed to form a semiconductor wafer W2' having a plurality of semiconductor die 10B connected to one another. In some embodiments, the semiconductor die 10B is referred to as a carrier die 10B. For example, the semiconductor wafer W2 is processed through the steps illustrated in fig. 7 to 10, and therefore, for the sake of brevity, will not be described again. As shown in fig. 51, each of the carrier dies 10B includes a semiconductor substrate 210, an interconnect structure 220, an isolation layer 240, and a plurality of vias 230, the semiconductor substrate 210 having a plurality of semiconductor devices formed therein, the interconnect structure 220 formed over the semiconductor substrate 210 and including a plurality of dielectric layers and a plurality of metallization patterns proximate the front surface S3, the isolation layer 240 formed over the semiconductor substrate 210 opposite the interconnect structure 220, and the vias 230 formed in the semiconductor substrate 210 extending into the dielectric layers of the interconnect structure 220 to be in physical and electrical contact with the metallization patterns of the interconnect structure 220 and through the isolation layer 240. The vias 230 of each of the carrier dies 10B may be electrically coupled to semiconductor devices in the semiconductor substrate 210 through the metallization pattern of the interconnect structure 220. In some embodiments, the semiconductor dies 10B each have a front surface S3 and a back surface S4 opposite the front surface S3. In some embodiments, each of the carrier dies 10B is referred to as a base level 10B (0) of a die stack 100.

Referring to fig. 52, in some embodiments, a first set of a plurality of semiconductor die 10A "is provided, wherein these semiconductor die 10A" are stacked on a carrier die 10B. For example, a semiconductor die 10A "is fabricated as described in connection with fig. 1-4. In some embodiments, the semiconductor die 10A "is bonded to the carrier die 10B in a face-to-back configuration by a hybrid bonding process. The bonding process and bonding relationship/configuration are illustrated in fig. 11 in conjunction with fig. 26A and 26B (showing enlarged cross-sectional views indicated by dashed box (or dashed area) a), and thus will not be described in detail herein. For example, as shown in fig. 52, the front surfaces S1 of semiconductor die 10A ″ are respectively bonded to the back surfaces S4 of carrier die 10B.

Referring to fig. 53, in some embodiments, a first group of semiconductor die 10A "is processed to form a plurality of semiconductor die 10A of a first level 10A (1) in a die stack 100. For example, the semiconductor die 10A "is processed by the steps set forth in fig. 12-16, and thus, for brevity, will not be described again. As shown in fig. 53, each of the semiconductor dies 10A includes a semiconductor substrate 110, an interconnect structure 120, a plurality of via holes 130, a dielectric layer 140, a plurality of bonding conductors 150, and an isolation layer 160, a plurality of semiconductor devices (not shown) are formed in the semiconductor substrate 110, the interconnect structure 120 is formed on the semiconductor substrate 110, the plurality of via holes 130 are formed in the semiconductor substrate 110 and extend into the interconnect structure 120, the dielectric layer 140 is formed on the interconnect structure 120 and is opposite to the semiconductor substrate 110, the plurality of bonding conductors 150 are formed on the interconnect structure 120 and are laterally covered by the dielectric layer 140, the isolation layer 160 is disposed on the semiconductor substrate 110 opposite to the interconnect structure 120, and the via holes 130 penetrate the isolation layer 160. In some embodiments, semiconductor dies 10A each have a front surface S1 and a back surface S2 opposite the front surface S1. For example, as shown in fig. 53, the semiconductor dies 10A are separated from each other by an isolation structure 50(1), wherein the isolation structure 50(1) is located above the semiconductor wafer W2'.

Referring to fig. 54, in some embodiments, a second set of a plurality of semiconductor dies 10A "is provided and these semiconductor dies 10A" are stacked on the semiconductor dies 10A of the first tier 10A (1), respectively. In the present disclosure, each semiconductor die 10A "(from the second group) is disposed in a face-to-back configuration on one of the semiconductor dies 10A of the first level 10A (1) for forming a second level of the die stack 100 (e.g., 10A (2) depicted in fig. 55). In some embodiments, the semiconductor die 10A "(from the second group) is bonded to the semiconductor die 10A of the first level 10A (1) by a hybrid bonding process. The bonding process and bonding relationships/configurations are illustrated in fig. 17 in conjunction with fig. 27A and 27B (showing enlarged cross-sectional views indicated by dashed boxes (or dashed areas) B), and thus are not described in detail herein. For example, as shown in fig. 54, the front surfaces S1 of semiconductor die 10A "(from the second group) are bonded to the back surfaces S2 of semiconductor die 10A of the first level 10A (1), respectively. For example, the via 130 is not yet exposed to the semiconductor substrate 110 in an accessible manner.

Referring to fig. 55, in some embodiments, a die stack 100 is formed over the carrier die 10B. For example, each of the die stacks 100 includes at least one interior level, such as 10A (1) -10A (T-1), and a topmost level 10A (T). In some embodiments, the structure depicted in fig. 54 is processed to form a die stack 100. For example, in each die stack 100, each internal level (e.g., 10A (2) through 10A (T-1)) may be fabricated by the same steps as forming the first level 10A (1) described in fig. 53, and the topmost level 10A (T) may be fabricated by the process described in fig. 54, and thus, for brevity, no further description is provided. That is, the semiconductor die 10A at the internal levels (e.g., 10A (1) through 10A (T-1)) may be fabricated individually by repeating the steps as described in fig. 12-16, and the topmost level 10A (T) may be fabricated by repeating the steps as described in fig. 17. As such, the semiconductor die 10A at the first level 10A (1) through the (T-1) th level 10A (T-1) of each die stack 100 may be similar or identical in configuration, function, and nature due to the use of similar formation steps. In some embodiments, the isolation structures are removed from the semiconductor wafer W2' after the die stack 100 is formed. For example, for every two adjacent levels of each die stack 100, the upper level is bonded to the lower level in a face-to-back configuration. By this bonding (without using any other external connections), semiconductor structure P7 is achieved with a better form factor and with a higher density of die stacks in the device.

Referring to FIG. 56, in some embodiments, semiconductor structure P7 is fabricated by processing the structure depicted in FIG. 55 with the steps set forth in FIGS. 20-24, and therefore, for the sake of brevity, will not be described again. In some embodiments, the semiconductor structure P7 has a carrier die 10B, a die stack 100, an insulating encapsulant 20, an electromagnetic interference shielding layer 60, a protective layer 70, and conductive terminals 30, the die stack 100 disposed on the carrier die 10B, the insulating encapsulant 20 formed on the carrier die 10B and the die stack 100, the electromagnetic interference shielding layer 60 sandwiched between the insulating encapsulant 20 and the carrier die 10B and between the insulating encapsulant 20 and the die stack 100, the protective layer 70 disposed on the carrier die 10, and the conductive terminals 30 disposed on the insulating encapsulant 20. As shown in fig. 56, for example, sidewalls 20S of insulating encapsulant 20 are aligned with sidewalls S5 of carrier die 10B, sidewalls 60S of electromagnetic interference shield layer 60, and sidewalls 70S of protective layer 70. That is, the sidewalls 20S of the insulating encapsulation 20 may be substantially flush and coplanar with the sidewalls S5 of the carrier die 10B, the sidewalls 60S of the emi shielding layer 60, and the sidewalls 70S of the protection layer 70.

As shown in fig. 56 and 57 (top plan view on the X-Y plane), for semiconductor structure P7, the positioning location of die stack 100 is within the positioning location of carrier die 10B and within the positioning location of insulating encapsulant 20, where the edge of carrier die 10B overlaps the edge of insulating encapsulant 20. In other words, the perimeter of the die stack 100 is smaller than the perimeter of the carrier die 10B and the perimeter of the insulating encapsulant 20, and the perimeter of the carrier die 10B is substantially equal to the perimeter of the insulating encapsulant 20.

In addition, modifications to the semiconductor structure P1a may also be adopted by the semiconductor structures P5, P6 and P7. Since details of the modification of the semiconductor structure P1a are set forth in fig. 30 to 44, they will not be described again for the sake of brevity.

Figure 58 is a schematic cross-sectional view illustrating an application of a semiconductor structure according to some embodiments of the present disclosure. For ease of understanding, like elements are designated with like reference numerals and are not described in detail herein. Referring to FIG. 58, a component assembly SC is provided that includes a first component C1 and a second component C2 disposed above the first component C1. First component C1 may be or include an interposer, a package substrate, a Printed Circuit Board (PCB), a printed wiring board, and/or other carrier capable of carrying an integrated circuit. In some embodiments, the second component C2 mounted on the first component C1 is similar to one of the semiconductor structures P1a-P1d, P2a-P2d, P3a-P3d, P4a-P4d, P5, P6, and P7 described above. For example, one or more semiconductor structures (e.g., P1a-P1d, P2a-P2d, P3a-P3d, P4a-P4d, P5, P6, and P7) may be electrically coupled to first component C1 through a plurality of terminals CT. The terminals CT may be conductive terminals 30.

In some embodiments, a primer layer UF is formed between the gaps of the first and second components C1 and C2 to cover the terminals CT at least laterally. Alternatively, primer layer UF is omitted. In one embodiment, the primer layer UF may be formed by primer dispensing (underfill dispensing) or any other suitable method. In some embodiments, the primer layer UF may be the same or different material as the insulating encapsulant 20, 40, and the disclosure is not limited thereto. Due to the primer layer UF, the bonding strength between the first component C1 and the second component C2 is enhanced.

In some other embodiments, the second component C2 mounted on the first component C1 may be an integrated fan-out (InFO) package including at least one semiconductor structure (e.g., P1a-P1d, P2a-P2d, P3a-P3d, P4a-P4d, P5, P6, and P7 described above in connection with fig. 24, 31-44, 45, 47, and 56) packaged therein. For example, the second component C2 includes a plurality of semiconductor structures (e.g., any combination of semiconductor structures P1a-P1d, P2a-P2d, P3a-P3d, P4a-P4d, P5, P6, and P7) arranged side by side and surrounded by a package encapsulant (not shown; e.g., a molding compound). The second component C2 may further include fan-out redistribution structures (not shown) formed on the package encapsulant and the semiconductor structures laterally encapsulated by the package encapsulant, and the fan-out redistribution structures may be electrically coupled to the semiconductor structures. In such an embodiment, the terminals CT may be controlled collapse chip connection (C4) bumps, Ball Grid Array (BGA) bumps, other suitable terminals having dimensions larger than conductive terminals of the semiconductor structure, and/or the like. For example, the terminals CT are formed on the fan-out rewiring structure to be electrically coupled to the first component C1, and these semiconductor structures are electrically coupled to the terminals CT through the fan-out rewiring structure.

Other packaging techniques may be used to form the component assembly SC and are not limited in this disclosure. For example, the component assembly SC is formed using a Wafer Level Packaging (WLP), a chip-on-wafer-on-substrate (CoWoS) process on a wafer-on-substrate, a chip-on-chip-on-substrate (CoCoS) process on a wafer-on-substrate, or the like. The component assemblies SC may be part of an electronic system for use in, for example, a computer (e.g., a high performance computer), a computing device for use in conjunction with an artificial intelligence system, a wireless communication device, a computer-related peripheral device, an entertainment device, and the like. A component assembly SC comprising the semiconductor structures discussed herein may provide high bandwidth data communications. It should be noted that other electronic applications are also possible. Alternatively, the additional terminal may be in physical and electrical contact with the first component C1 opposite the terminal CT for electrical connection with any other external component.

According to some embodiments, a semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite the first active surface. The second semiconductor die is located over the first semiconductor die and includes a second semiconductor substrate having a second active surface and a second back surface opposite the second active surface. The second semiconductor die is bonded to the first semiconductor die by bonding the second active surface to the first back surface at a first hybrid bonding interface in a vertical direction. The first dimension of the first semiconductor die is greater than the second dimension of the second semiconductor die in a lateral direction.

In accordance with some embodiments, in the semiconductor structure, wherein the first semiconductor die further comprises a plurality of first vias penetrating the first semiconductor substrate and the second semiconductor die further comprises a plurality of second vias penetrating the second semiconductor substrate, and wherein the plurality of first vias are respectively bonded to the plurality of second vias at the first hybrid bond interface, and the first semiconductor die is in electrical connection and communication with the second semiconductor die through the plurality of first vias and the plurality of second vias. In accordance with some embodiments, in the semiconductor structure, wherein the second semiconductor die comprises a first stack having a plurality of second semiconductor dies, wherein two adjacent second semiconductor dies in the first stack having the plurality of second semiconductor dies are bonded to each other by another hybrid bonding interface and a second active surface of one of the two adjacent second semiconductor dies is bonded to a second back surface of the other of the two adjacent second semiconductor dies at the other hybrid bonding interface, wherein the plurality of second semiconductor dies in the first stack are electrically connected and in electrical communication with each other through the plurality of second vias and with the first semiconductor die through the plurality of first vias and the plurality of second vias. In the semiconductor structure, according to some embodiments, wherein the stacked structure further comprises: a third semiconductor die comprising a third semiconductor substrate and a plurality of third vias embedded in the third semiconductor substrate, and having a third active surface and a third back surface opposite the third active surface, wherein: the third semiconductor die is bonded to the outermost second semiconductor die by bonding the third active surface to a second back surface of the outermost second semiconductor die in the first stack opposite the first semiconductor die at a second hybrid bond interface along the vertical direction, a third dimension of the third semiconductor die is substantially equal to the second dimension of each second semiconductor die along the lateral direction, and the plurality of third vias are respectively bonded to a plurality of second vias of the outermost second semiconductor die at the second hybrid bond interface, and the third semiconductor die is in electrical connection and communication with the first semiconductor die and the first stack having the plurality of second semiconductor dies. In the semiconductor structure according to some embodiments, wherein the second semiconductor die further comprises at least one second stack of a plurality of second semiconductor dies on the first semiconductor die, and the at least one second stack of the plurality of second semiconductor dies and the first stack of the plurality of second semiconductor dies are arranged side-by-side along the lateral direction, wherein two adjacent second semiconductor dies in the at least one second stack of the plurality of second semiconductor dies are bonded to each other by another hybrid bonding interface, and the second active surface of one of the two adjacent second semiconductor dies is bonded to the second back surface of the other of the two adjacent second semiconductor dies at the another hybrid bonding interface, wherein the plurality of second semiconductor dies in the at least one second stack are electrically connected to each other and electrically connected through the plurality of second vias And communicating with and electrically connecting and communicating with the first semiconductor die through the plurality of first via holes and the plurality of second via holes. In the semiconductor structure, according to some embodiments, wherein the stacked structure further comprises: a third semiconductor die comprising a third semiconductor substrate and a plurality of third vias embedded in the third semiconductor substrate, and having a third active surface and a third back surface opposite the third active surface, wherein: the third semiconductor die is bonded to an outermost second semiconductor die in the first stack by bonding the third active surface to a second back surface of the outermost second semiconductor die in the first stack opposite the first semiconductor die at a second hybrid bonding interface along the vertical direction, a third dimension of the third semiconductor die is substantially equal to the second dimension of each second semiconductor die in the first stack, and the plurality of third vias are respectively bonded to a plurality of second vias of the outermost second semiconductor die in the first stack at the second hybrid bond interface, and the third semiconductor die is in electrical connection and communication with the first semiconductor die and the first stack having the plurality of second semiconductor dies; and at least one fourth semiconductor die comprising a fourth semiconductor substrate and a plurality of fourth vias embedded in the fourth semiconductor substrate and having a fourth active surface and a fourth back surface opposite the fourth active surface, wherein: the at least one fourth semiconductor die is bonded to an outermost second semiconductor die in the at least one second stack by bonding the fourth active surface to a second back surface of the outermost second semiconductor die in the at least one second stack opposite the first semiconductor die at a third hybrid bonding interface along the vertical direction, a fourth dimension of the at least one fourth semiconductor die is substantially equal to the second dimension of each second semiconductor die in the at least one second stack along the lateral direction, and the plurality of fourth vias are respectively bonded to a plurality of second vias of the outermost second semiconductor die in the at least one second stack at the third hybrid bonding interface, and the at least one fourth semiconductor die is in electrical connection and communication with the first semiconductor die and the at least one second stack having the plurality of second semiconductor dies . In the semiconductor structure according to some embodiments, wherein the second semiconductor substrate further comprises a sidewall and a rounded edge, the rounded edge connecting the second back surface and the sidewall; or a sidewall and a beveled edge connecting the second back surface and the sidewall. According to some embodiments, the semiconductor structure further comprises: a plurality of conductive terminals on the first active surface of the first semiconductor die and electrically connected to the first semiconductor die. According to some embodiments, in the semiconductor structure, wherein the stacked structure comprises two or more stacked structures.

According to some embodiments, a semiconductor structure includes a semiconductor device, a plurality of conductive terminals, and a connection structure. The semiconductor device includes a base level and a die stack. The base level includes a first die. The die stack is bonded to the base level and includes a plurality of second dies arranged into at least one inner level and an outermost level. The die stack is bonded to the base level by a first hybrid bonding interface. The at least one inner tier is joined with the outermost tier by a second hybrid joining interface. There is an offset between sidewalls of the base level and sidewalls of the die stack, wherein the first die and the plurality of second dies are in electrical communication with each other. The plurality of conductive terminals are located over and electrically connected to the semiconductor device. The connection structure is located between the semiconductor device and the plurality of conductive terminals, wherein the base level is located between the connection structure and the die stack, and the at least one inner level is located between the base level and the outermost level.

According to some embodiments, the semiconductor structure further comprises: an insulating encapsulation covering the semiconductor device, wherein the base level is located between the insulating encapsulation and the connection structure and between the die stack and the connection structure, wherein sidewalls of the insulating encapsulation and sidewalls of the connection structure are substantially coplanar, and the connection structure comprises a protection layer or a redistribution routing structure. In the semiconductor structure, according to some embodiments, wherein the sidewalls of the insulating encapsulation are further substantially coplanar with the sidewalls of the base level. According to some embodiments, the semiconductor structure further comprises: a first insulating encapsulation over the semiconductor device and covering the base level; and a second insulating encapsulation over the first insulating encapsulation and covering the die stack, wherein sidewalls of the first insulating encapsulation and sidewalls of the second insulating encapsulation are substantially coplanar with sidewalls of the connection structure, and the connection structure includes a passivation layer or a redistribution routing structure. In the semiconductor structure according to some embodiments, wherein the sidewalls of the first insulating encapsulation and the sidewalls of the second insulating encapsulation are further substantially coplanar with the sidewalls of the base level. According to some embodiments, the semiconductor structure further comprises: an isolation element at least partially covering sidewalls of the semiconductor device, wherein the isolation element extends from the base level towards the die stack, wherein a material of the isolation element comprises a conductive layer or a dielectric layer. According to some embodiments, in the semiconductor structure, wherein the die stack comprises two or more die stacks. According to some embodiments, in the semiconductor structure, wherein the semiconductor device comprises two or more semiconductor devices.

According to some embodiments, a method of fabricating a semiconductor structure comprises: forming at least one stacked structure comprising: providing a base level comprising a first semiconductor die, and forming a die stack comprising a plurality of second semiconductor dies on the base level by hybrid bonding, wherein in a lateral direction a first dimension of the base level is larger than a second dimension of the die stack, and the first semiconductor die is electrically connected to the plurality of second semiconductor dies; forming a connection structure over the at least one stack structure, the base level being located between the connection structure and the die stack; and disposing a plurality of conductive terminals over the at least one stacked structure and electrically connecting the plurality of conductive terminals to the first semiconductor die, the connection structure being located between the plurality of conductive terminals and the base level.

In the method according to some embodiments, wherein the die stack comprises a bottommost level, a topmost level, and at least one internal level between the bottommost level and the topmost level, and the bottommost level, the at least one internal level, and the topmost level each comprise one or more than one of the plurality of second semiconductor dies, wherein forming the die stack on the base level by hybrid bonding comprises: hybrid bonding a front surface of the bottommost tier to a back surface of the base tier to electrically connect the first semiconductor die with the one or more of the plurality of second semiconductor dies of the bottommost tier; hybrid bonding a front surface of the at least one internal level to a back surface of the bottommost level to electrically connect the one or more of the plurality of second semiconductor dies of the at least one internal level with the one or more of the plurality of second semiconductor dies of the bottommost level; and hybrid bonding the front surface of the topmost tier to the back surface of the at least one internal tier to electrically connect the one or more of the plurality of second semiconductor dies of the at least one internal tier with the one or more of the plurality of second semiconductor dies of the topmost tier. According to some embodiments, in the method, wherein forming the die stack on the base level by hybrid bonding comprises forming a plurality of die stacks on the base level by hybrid bonding.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (1)

1. A semiconductor structure, comprising:

a stacked structure comprising:

a first semiconductor die comprising a first semiconductor substrate having a first active surface and a first back surface opposite the first active surface; and

a second semiconductor die located over the first semiconductor die, comprising a second semiconductor substrate having a second active surface and a second back surface opposite the second active surface, and bonded to the first semiconductor die by bonding the second active surface to the first back surface at a first hybrid bonding interface in a vertical direction,

wherein a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die in a lateral direction.

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