CN112108196A - Active matrix digital micro-fluidic chip substrate and manufacturing method thereof - Google Patents
Active matrix digital micro-fluidic chip substrate and manufacturing method thereof Download PDFInfo
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- CN112108196A CN112108196A CN202011110117.7A CN202011110117A CN112108196A CN 112108196 A CN112108196 A CN 112108196A CN 202011110117 A CN202011110117 A CN 202011110117A CN 112108196 A CN112108196 A CN 112108196A
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- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 239000011159 matrix material Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 230000002209 hydrophobic effect Effects 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 37
- 238000000151 deposition Methods 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 239000011651 chromium Substances 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 238000005019 vapor deposition process Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 11
- 239000007788 liquid Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
- B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
- B01L3/50—Containers for the purpose of retaining a material to be analysed, e.g. test tubes
- B01L3/502—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures
- B01L3/5027—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
- B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
- B01L3/50—Containers for the purpose of retaining a material to be analysed, e.g. test tubes
- B01L3/502—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures
- B01L3/5027—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip
- B01L3/502707—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip characterised by the manufacture of the container or its components
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
- B01L2200/00—Solutions for specific problems relating to chemical or physical laboratory apparatus
- B01L2200/10—Integrating sample preparation and analysis in single entity, e.g. lab-on-a-chip concept
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
- B01L2300/00—Additional constructional details
- B01L2300/08—Geometry, shape and general structure
- B01L2300/0887—Laminated structure
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- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Dispersion Chemistry (AREA)
- Analytical Chemistry (AREA)
- General Health & Medical Sciences (AREA)
- Hematology (AREA)
- Clinical Laboratory Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses an active matrix digital microfluidic chip substrate and a manufacturing method thereof, wherein the active matrix digital microfluidic chip substrate comprises a substrate and a transistor arranged on the substrate; a source electrode, a source electrode outgoing line, a drain electrode and a drain electrode outgoing line of the transistor are arranged on the substrate on the same layer, the source electrode and the source electrode outgoing line are of an integrally formed structure, the drain electrode and the drain electrode outgoing line are of an integrally formed structure, and the active layer is arranged between the source electrode and the drain electrode; insulating layers are coated on the upper surfaces of the source electrode, the source electrode outgoing line, the drain electrode outgoing line and the active layer, a grid electrode outgoing line is arranged on the upper surface of the insulating layer, a grid electrode is arranged at the position of the active layer, and the grid electrode outgoing line are of an integrally formed structure; the upper surfaces of the grid and the grid outgoing line are coated with a dielectric layer, and the upper surface of the dielectric layer is coated with a hydrophobic layer. The invention avoids the influence of the source electrode and the drain electrode of the traditional active matrix digital microfluidic chip substrate adopting a bottom gate structure on the etching of the active layer during the manufacturing, and greatly improves the stability of a transistor device.
Description
Technical Field
The invention relates to the technical field of digital microfluidic, in particular to an active matrix digital microfluidic chip substrate and a manufacturing method thereof.
Background
With the development of the MEMS technology, the dielectric wetting digital microfluidic technology has made a great progress in its processing technology and microfluidic control, and it can implement the processing of dispensing, transferring, mixing, separating, etc. of droplets and perform different operations on a plurality of droplets simultaneously, and can integrate the sample preparation, reaction, detection, etc. operation units of biological, medical, etc. analysis processes onto a micron-scale chip, and fully automatically complete the whole analysis process.
At present, the traditional active matrix digital microfluidic chip substrate adopts a bottom gate transistor structure, namely, a gate is arranged at the bottom layer. However, the bottom gate transistor structure design has the problems of complex structure, large influence of the data signal line on liquid drop driving and unstable device performance. Meanwhile, the active matrix digital microfluidic chip substrate with the bottom gate transistor structure needs at least 4 photoetching processes during manufacturing, each photoetching process needs film layer deposition, gluing, photoetching, developing, etching and stripping, the processing process is complex, and the production cost is high. Chinese patent No. CN210279192U, entitled "a digital microfluidic chip substrate and digital microfluidic chip" discloses a digital microfluidic chip substrate, which optimizes the structure compared with the conventional active matrix digital microfluidic chip substrate, but still has a bottom gate transistor structure and a multi-film layer design, and does not avoid the influence of back channel etching on the stability of the transistor device. The reason is that the process route of the bottom gate structure is to prepare a gate → an insulating layer → an active layer → a source, a drain → a dielectric layer → a hydrophobic layer on a substrate in sequence, wherein wet etching is usually adopted when preparing the source and the drain (metal layers), taking the source and the drain as copper materials as an example, after etching solution is used for wet etching a copper metal thin film on the active layer, copper ions remain in the exposed active layer (channel), and the existence of the copper ions increases the leakage current of the thin film transistor, so that the output characteristic curve changes, and the performance of the device is affected.
Disclosure of Invention
The invention aims to provide an active matrix digital microfluidic chip substrate, and the invention also aims to provide a manufacturing method of the active matrix digital microfluidic chip substrate.
In order to achieve the purpose, the invention can adopt the following technical scheme:
the active matrix digital microfluidic chip substrate comprises a substrate and a transistor arranged on the substrate; the source electrode, the source electrode outgoing line, the drain electrode and the drain electrode outgoing line of the transistor are arranged on the substrate on the same layer, the source electrode and the source electrode outgoing line are of an integrally formed structure, the drain electrode and the drain electrode outgoing line are also of an integrally formed structure, and the active layer is arranged between the source electrode and the drain electrode; insulating layers are coated on the upper surfaces of the source electrode, the source electrode outgoing line, the drain electrode outgoing line and the active layer, a grid electrode outgoing line is arranged on the upper surface of the insulating layer, a grid electrode is arranged at the position of the active layer, and the grid electrode outgoing line are of an integrally formed structure; the upper surfaces of the grid and the grid outgoing line are coated with dielectric layers, and the upper surfaces of the dielectric layers are coated with hydrophobic layers.
The transistors disposed on the substrate are plural, and the plural transistors are arranged in a matrix arrangement.
The source lead-out wires are arranged on the substrate along the transverse direction, and the grid lead-out wires are arranged along the insulating layer in the column direction.
The invention relates to a method for manufacturing an active matrix digital microfluidic chip substrate, which comprises the following steps:
step 8, depositing the dielectric layer on the upper surfaces of the grid and the grid lead-out wire; the dielectric layer material is selected from silicon nitride or parylene, preferably silicon nitride, so that good bonding force is ensured between the dielectric layer material and the insulating layer, and the film thickness is 1000 nm;
and 9, coating or depositing the hydrophobic layer on the dielectric layer, wherein the thickness of the hydrophobic layer is 3000 nm.
The invention has the advantages that: 1, the influence of a source electrode and a drain electrode of a traditional active matrix digital microfluidic chip substrate adopting a bottom gate structure on active layer etching during manufacturing is avoided, and the stability of a transistor device is greatly improved; 2, the source outgoing line and the drain outgoing line are close to the substrate and far away from the hydrophobic layer (liquid drops are positioned on the hydrophobic layer), so that the influence of the voltage of the source outgoing line and the drain outgoing line on the liquid drop driving when a signal is loaded is avoided, and the liquid drop driving is smoother; 3, the structure is simple in design, the situation that a via hole needs to be formed in the insulating layer for connection between the drain electrode and a drain electrode lead-out wire is avoided, the complex process steps of deposition, exposure, etching and the like are reduced, the production period is shortened, the product quality is improved, and the production cost is reduced; 4, the insulating layer and the dielectric layer of the active matrix digital microfluidic chip are made of the same material, so that the bonding force of the film layer is improved, and the breakdown voltage of the film layer is improved.
Drawings
Fig. 1 is a schematic structural view of the present invention.
Fig. 2 is a partial schematic view of a plurality of transistors according to the present invention arranged in a matrix arrangement.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 and 2, the active matrix digital microfluidic chip substrate of the present invention includes a substrate 1 and a plurality of transistors 2 disposed on the substrate; the plurality of transistors 2 are arranged in a matrix arrangement.
A source electrode 3, a source electrode outgoing line 3.1, a drain electrode 4 and a drain electrode outgoing line 4.1 of each transistor 2 are arranged on the substrate 1 on the same layer, the source electrode 3 and the source electrode outgoing line 3.1 are of an integrally formed structure, the source electrode outgoing line 3.1 is transversely arranged on the substrate 1, the drain electrode 4 and the drain electrode outgoing line 4.1 are also of an integrally formed structure, and an active layer 5 is arranged between the source electrode 3 and the drain electrode 4; an insulating layer 6 is coated on the upper surfaces of the source electrode 3, the source electrode leading-out wire 3.1, the drain electrode 4, the drain electrode leading-out wire 4.1 and the active layer 5, a grid electrode leading-out wire 7.1 is arranged on the upper surface of the insulating layer 6, a grid electrode 7 is arranged on the upper surface of the insulating layer 6 at the position of the active layer 5, the grid electrode 7 and the grid electrode leading-out wire 7.1 are of an integrally formed structure, and the grid electrode leading-out wires 7.1 are arranged along the column; the upper surfaces of the grid 7 and the grid outgoing line 7.1 are coated with a dielectric layer 8, and the upper surface of the dielectric layer 8 is coated with a hydrophobic layer 9.
The invention relates to a method for manufacturing an active matrix digital microfluidic chip substrate, which comprises the following steps:
step 8, depositing a dielectric layer 8 on the upper surfaces of the grid 7 and the grid outgoing line 7.1; the material of the dielectric layer 8 is selected from silicon nitride or parylene, preferably silicon nitride, so that good bonding force with an insulating layer is ensured, and the film thickness is 1000 nm;
and 9, coating or depositing a hydrophobic layer 9 on the dielectric layer 8, wherein the thickness of the hydrophobic layer is 3000 nm.
The working principle of the invention is as follows:
the gate lead-out 7.1 applies a gate voltage Vgs to the gate 7, which generates an electric field that causes a change in the thickness of the conductive channel of the active layer 5, the transistor 2 is turned on and thus controls the current flowing through the source 3 and the drain 4, thereby driving the movement of the droplets on the surface of the hydrophobic layer 9.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly. In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
In addition, the meaning of "and/or" appearing throughout is to include three juxtapositions, exemplified by "A and/or B," including either the A or B arrangement, or both A and B satisfied arrangement. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Claims (10)
1. An active matrix digital microfluidic chip substrate comprises a substrate and a transistor arranged on the substrate; the method is characterized in that: the source electrode, the source electrode outgoing line, the drain electrode and the drain electrode outgoing line of the transistor are arranged on the substrate on the same layer, the source electrode and the source electrode outgoing line are of an integrally formed structure, the drain electrode and the drain electrode outgoing line are also of an integrally formed structure, and the active layer is arranged between the source electrode and the drain electrode; insulating layers are coated on the upper surfaces of the source electrode, the source electrode outgoing line, the drain electrode outgoing line and the active layer, a grid electrode outgoing line is arranged on the upper surface of the insulating layer, a grid electrode is arranged at the position of the active layer, and the grid electrode outgoing line are of an integrally formed structure; the upper surfaces of the grid and the grid outgoing line are coated with dielectric layers, and the upper surfaces of the dielectric layers are coated with hydrophobic layers.
2. The active matrix digital microfluidic chip substrate according to claim 1, wherein the transistors disposed on the substrate are a plurality of transistors, and the plurality of transistors are arranged in a matrix arrangement.
3. The active matrix digital microfluidic chip substrate according to claim 1 or 2, wherein the source lead lines are arranged on the substrate in a transverse direction, and the gate lead lines are arranged in a column direction of the insulating layer.
4. A method for manufacturing the active matrix digital microfluidic chip substrate according to claim 1, comprising the steps of:
step 1, depositing a first metal film on the substrate through a physical vapor deposition process;
step 2, manufacturing the source electrode, a source electrode outgoing line, a drain electrode outgoing line and a groove between the source electrode and the drain electrode on the first metal film through a photoetching process;
step 3, depositing a layer of indium gallium zinc oxide or amorphous silicon in the groove by a vapor deposition process;
step 4, manufacturing the active layer in the groove through a photoetching process;
step 5, depositing the insulating layer on the upper surfaces of the source electrode, the source electrode outgoing line, the drain electrode outgoing line and the active layer through a chemical vapor deposition process;
step 6, depositing a second metal film on the upper surface of the insulating layer through a physical vapor deposition process;
step 7, manufacturing the grid and a grid outgoing line on the second metal film through a photoetching process;
step 8, depositing the dielectric layer on the upper surfaces of the grid and the grid lead-out wire;
and 9, coating or depositing the hydrophobic layer on the dielectric layer.
5. The method for manufacturing the active matrix digital microfluidic chip substrate according to claim 4, wherein the first metal film is made of chromium or copper, and the thickness of the film layer is 300 nm.
6. The method for manufacturing the active matrix digital microfluidic chip substrate according to claim 4, wherein the thickness of the indium gallium zinc oxide or the amorphous silicon layer is 120 nm.
7. The method for manufacturing the active matrix digital microfluidic chip substrate according to claim 4, wherein the insulating layer has a thickness of 500nm and is made of silicon oxynitride or silicon nitride.
8. The method for manufacturing the active matrix digital microfluidic chip substrate according to claim 4, wherein the second metal film is made of chromium, aluminum, titanium or copper, and has a thickness of 300 nm.
9. The method for manufacturing the active matrix digital microfluidic chip substrate according to claim 4, wherein the dielectric layer is made of silicon nitride or parylene and has a thickness of 1000 nm.
10. The method of claim 4, wherein the hydrophobic layer has a thickness of 3000 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011110117.7A CN112108196A (en) | 2020-10-16 | 2020-10-16 | Active matrix digital micro-fluidic chip substrate and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011110117.7A CN112108196A (en) | 2020-10-16 | 2020-10-16 | Active matrix digital micro-fluidic chip substrate and manufacturing method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090050895A1 (en) * | 2007-08-24 | 2009-02-26 | Tokyo Electron Limited | Semiconductor manufacturing method, semiconductor manufacturing apparatus, and display unit |
| CN102522337A (en) * | 2011-12-16 | 2012-06-27 | 北京大学 | Preparation method of top gate zinc oxide film transistor |
| CN107644936A (en) * | 2017-09-27 | 2018-01-30 | 信利半导体有限公司 | A kind of OTFT and preparation method thereof |
| CN210279192U (en) * | 2019-04-19 | 2020-04-10 | 北京京东方传感技术有限公司 | Digital microfluidic substrate and digital microfluidic chip |
| CN212396773U (en) * | 2020-10-16 | 2021-01-26 | 安图实验仪器(郑州)有限公司 | Active matrix digital micro-fluidic chip substrate |
-
2020
- 2020-10-16 CN CN202011110117.7A patent/CN112108196A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090050895A1 (en) * | 2007-08-24 | 2009-02-26 | Tokyo Electron Limited | Semiconductor manufacturing method, semiconductor manufacturing apparatus, and display unit |
| CN102522337A (en) * | 2011-12-16 | 2012-06-27 | 北京大学 | Preparation method of top gate zinc oxide film transistor |
| CN107644936A (en) * | 2017-09-27 | 2018-01-30 | 信利半导体有限公司 | A kind of OTFT and preparation method thereof |
| CN210279192U (en) * | 2019-04-19 | 2020-04-10 | 北京京东方传感技术有限公司 | Digital microfluidic substrate and digital microfluidic chip |
| CN212396773U (en) * | 2020-10-16 | 2021-01-26 | 安图实验仪器(郑州)有限公司 | Active matrix digital micro-fluidic chip substrate |
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