CN1121065C - 动态随机存取存储器的电容器的制造方法 - Google Patents
动态随机存取存储器的电容器的制造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000003990 capacitor Substances 0.000 title claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 108
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 claims abstract description 33
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims description 58
- 238000005530 etching Methods 0.000 claims description 25
- 238000003860 storage Methods 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
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- 238000011065 in-situ storage Methods 0.000 claims description 5
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- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 claims 1
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H01L28/40—Capacitors
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- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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Abstract
一种DRAM存储单元的电容器的制造方法包括:在层间介电层和氮化物层中形成接触窗开口;以第一多晶硅层填满接触窗开口,形成存储节接触窗;形成一氧化层;限定及蚀刻以形成中间堆叠结构;在此结构侧壁形成第一多晶硅间隙壁;去除部分氧化层,露出第一多晶硅间隙壁的顶部;形成氮化物间隙壁,其并不延伸至第一多晶硅间隙壁的顶部;形成第二多晶硅间隙壁;去除氧化层;去除氮化物间隙壁及氮化物层,形成一下存储节;以及在下存储节上形成一薄电容器介电层以及一导电层。
Description
技术领域
本发明涉及一种半导体存储器的制造方法,且特别是涉及一种动态随机存取存储器(DRAM)电容器的制造方法。
背景技术
集成电路制作工艺中集成度的不断增加,提升动态随机存取存储器的集成密度已成为一趋势,然而,动态随机存取存储器存储单元的密度越高,电容器在动态随机存取存储器存储单元所能利用的面积就越小。为了使电容器的面积减小的同时,仍能维持一可靠的标准,因此在电容器所占的空间(footprint)缩小的同时,仍能维持每个电容器的电容量是很重要的。近来,还发展出三维空间的电容器结构用以增加存储单元电容量,例如:双叠式(double-stacked)、鳍状构造(fin-structure)、分散堆叠式(spread-stacked)或皇冠型构造(crown structure)等电容器。
对于如何发展出这些能将制作成本减至最低,且将半导体元件的制作成品率增至最高的电容器的制作方法而言,也成为研究开发上的一大挑战。
发明概述
有鉴于此,本发明的主要目的就是提供一种动态随机存取存储器存储单元中电容器的制造方法,以便在减小电容器所占的空间的同时,保持充足的电容量。
为实现上述目的,本发明的动态随机存取存储器存储单元中电容器的制造方法包括以下步骤:首先,在一层间介电层中,形成一氮化物层,在该层间介电层以及该氮化物层上,形成一接触窗开口,在该接触窗开口以及该氮化物层上,形成一第一多晶硅层,在该第一多晶硅层上,形成一氧化层,限定及蚀刻该氧化层以及该第一多晶硅层,形成一中间堆叠结构于接触窗开口上方,在该中间堆叠结构侧壁形成一第一多晶硅间隙壁,去除部分该氧化层及该中间堆叠结构,露出该第一多晶硅间隙壁的顶部,在该第一多晶硅间隙壁中,形成氮化物间隙壁,该氮化物间隙壁并不延伸至该第一多晶硅间隙壁的顶部,在该氮化物间隙壁及该第一多晶硅间隙壁上,形成一第二多晶硅间隙壁,去除该氧化层、该氮化物间隙壁及该氮化物层,形成下存储节,并在下存储节上形成一介电层以及一导电层。
附图的简要说明
为使本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举一优选实施例,并配合附图作详细说明。附图中:
图1至3是显示一种现有技术的皇冠型电容(crown shaped capacitor)的制造流程剖面图;以及
图4至9是显示根据本发明的优选实施例的电容制造流程剖面图。
优选实施方式的详细描述
本发明提供一个用在位线上的电容器的制造方法,此电容器广泛被应用在动态存取存储器存储单元上。
图1是以现有技术在半导体基底101上,形成一存取晶体管(accesstransistor)103,在存取晶体管103表面上形成一层间介电层(interlayerdielectric,ILD)105,典型的层间介电层105是由二氧化硅、硅酸四乙酯(Tetraethylorthosilicate,TEOS)以及硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)层所组成,用以当作绝缘层及平坦化层(planarization)。之后,在层间介电层105上沉积一层氮化物层107,此氮化硅层107以氮化硅(Si3N4)为优选,且优选地利用化学气相沉积法(Chemical Vapor Deposition,CVD)形成,并具有大约1500至2000埃范围之间的厚度。接着,以现有技术在氮化物层107及层间介电层105中构图(patterning)及蚀刻(etching)形成一接触窗开口(contact hole)。
请参照图2,是利用化学气相沉积法在一接触窗开口上,形成一第一多晶硅层111,其为沉积且原位掺杂多晶硅(in-situ doped polysilicon),厚度范围介于1000至2000埃之间,此沉积且原位掺杂多晶硅层,还填满底部的接触窗开口,在接触窗开口中形成一存储节接触窗109。接着,在第一多晶硅层111上形成一氧化层113,优选的氧化层113是以现有方式所形成的硅酸四乙酯或硼磷硅酸盐玻璃,厚度约为4000至6000埃,然后,构图及蚀刻氧化层113及第一多晶硅层111,形成中间堆叠(intermediate stack)结构,如图2所示。
接着,请参照图3,在该第一多晶硅层111以及氧化层113的侧壁形成多晶硅侧壁间隙壁115,其中,多晶硅侧壁间隙壁115的形成方式,可以采用现有方法沉积另一层厚度在500至2000埃之间的多晶硅层,再以回蚀刻法(etch back)蚀刻形成,如图3所示,为现有的皇冠型结构电容器。
接着,请参照图4,以湿式沉浸氧化物蚀刻法(wet dip oxide etch)将部分氧化层113移除,该湿式沉浸氧化物蚀刻法的优选选择,是利用稀释的氟化氢(HF)溶液或缓冲氧化蚀刻,而在多晶硅侧壁间隙壁115之间残留的氧化层113的优选厚度范围约在1000至2000埃。其中,氮化物层107是用以作为层间介电层105的湿式沉浸氧化物蚀刻法的阻挡层。
接着,请参照图5,在图4的该结构上形成一氮化物层(以氮化硅为优选),厚度范围约在500至2000埃之间,再以现有的各相异性蚀刻法(Anisotropic Etch)形成一氮化物间隙壁117,利用过蚀刻法(over etch)蚀刻暴露出多晶硅侧壁间隙壁115顶部厚度范围约在600至1500埃之间,过蚀刻法同时会去除厚度范围约在600至1500埃之间的氮化物层107,因为过蚀刻后保留部分的氮化物层107是相当重要的,因此蚀刻之前必需形成具有足量的厚度的氮化物层107。
接着,请参照图6,沉积一厚度范围在500至1000埃之间的一第二多晶硅层,再以现有的各相异性蚀刻法在氮化物间隙壁117的侧壁形成一第二多晶硅间隙壁119,此蚀刻最好利用在露出第一多晶硅间隙壁115顶部停止,这样,使得第二多晶硅间隙壁119与暴露的第一多晶硅间隙壁115顶部之间彼此导通连接。
接着,请参照图7,以湿式沉浸氧化物蚀刻法去除氧化层113,湿式沉浸氧化蚀刻的优选选择,是利用稀释的氟化氢溶液或缓冲氧化蚀刻。其中,氮化物层107是用以作为层间介电层105的蚀刻阻挡层。
接着,请参照图8,以湿式沉浸氮化物蚀刻法(wet dip nitride etch)去除氮化物层107和氮化物间隙壁117,其中,以使用热磷酸(H3PO4)溶液为优选,蚀刻完成后的结构为如图8所示的一动态随机存取存储器的电容下存储节(bottom storage node),此下存储节通常为一具有蘑菇状悬突的冠状结构(mushroom shaped overhangs)。虽然图中显示为剖面图,但可由以上说明辨识出,下存储节最好是一圆柱状,而第二多晶硅间隙壁119为一半喇叭口形(half toroidal shape)构造。
最后,欲完成图9所示的电容器,可以用任何现有电容器的介电层121,例如一氧化硅/氮化硅/氧化硅(Oxide/Nitride/Oxide,ONO)层,及形成一沉积且原位掺杂多晶硅上层123,请参照图9,形成本实施例的电容器结构。
综上所述,本发明藉由改进现有的皇冠型电容器,获得更多的电容器面积,且本发明将电容器的面积增大至约为现有皇冠型电容器的2至3倍。
虽然本发明已结合一优选实施例揭露如上,但是其并非用以限定本发明,本领域的技术人员在不脱离本发明的精神和范围内,可作出更动与润饰。
Claims (20)
1.一种动态随机存取存储器存储单元的电容器的制造方法,该制造方法包括下列步骤:
形成一层间介电层;
在该层间介电层上,形成一氮化物层;
在该层间介电层以及该氮化物层中,形成一接触窗开口;
在该氮化物层及该接触窗开口上,形成一第一多晶硅层,并填满该接触窗开口,在该接触窗开口中形成一存储节接触窗;
在该第一多晶硅层上,形成一氧化层;
限定及蚀刻该氧化层及该第一多晶硅层,在该存储节接触窗上方形成一中间堆叠结构;
在该中间堆叠结构侧壁形成一第一多晶硅间隙壁;
去除部分该中间堆叠结构的该氧化层,露出该第一多晶硅间隙壁的顶部;
在该第一多晶硅间隙壁侧壁,形成氮化物间隙壁,该氮化物间隙壁并不延伸至该第一多晶硅间隙壁的顶部;
在该氮化物间隙壁及该第一多晶硅间隙壁上,形成一第二多晶硅间隙壁;
去除该氧化层;
去除该氮化物间隙壁及该氮化物层,形成一下存储节;以及
在该下存储节上形成一薄电容器介电层以及一导电层。
2.如权利要求1所述的制造方法,其中,该层间介电层材料由氧化硅、硅酸四乙酯及硼磷硅玻璃组成。
3.如权利要求1所述的制造方法,其中,该第一及第二多晶硅间隙壁为一沉积且原位掺杂多晶硅。
4.如权利要求1所述的制造方法,其中,该氧化层具有4000至6000埃范围之间的厚度,且为硼酸四乙酯以及硼磷硅玻璃之一。
5.如权利要求1所述的制造方法,其中,该氧化层的厚度在1500至2000埃范围之间。
6.如权利要求1所述的制造方法,其中,将部分该氧化层去除,使剩余该氧化层厚度范围在1000至2000埃之间。
7.如权利要求1所述的制造方法,其中,该氮化物层及该氮化物间隙壁为氮化硅。
8.如权利要求1所述的制造方法,氮化物间隙壁蚀刻时是利用过蚀刻法使第一多晶硅间隙壁顶部露出600至1500埃之间。
9.一种在一存储节接触窗上形成一下存储节的制造方法,在一层间介电层及一氮化物层中形成该存储节接触窗,该方法包括下列步骤:
在该存储节接触窗及该氮化物层上形成一第一多晶硅层;
在该第一多晶硅层上形成一氧化层;
限定及蚀刻该氧化层及该第一多晶硅层,在该存储节接触窗上形成一中间堆叠结构;
在该中间堆叠结构侧壁形成一多晶硅间隙壁;
去除部分该中间堆叠结构的该氧化层,露出该第一多晶硅间隙壁的顶部;
在该第一多晶硅间隙壁侧壁,形成一氮化物间隙壁,该氮化物间隙壁并不延伸至该第一多晶硅间隙壁的顶部;
在该多晶硅间隙壁及该氮化物间隙壁上,形成一第二多晶硅间隙壁;
去除该氧化层;以及
去除该氮化物间隙壁及该氮化物层。
10.如权利要求9所述的制造方法,其中,该氧化层具有4000至6000埃范围之间的厚度,且为硅酸四乙酯及硼磷硅酸盐玻璃两者之一。
11.如权利要求9所述的制造方法,其中,该氧化层厚度在4000至6000埃之间。
12.如权利要求9所述的制造方法,其中,该氮化物层厚度在1500至2000埃之间。
13.如权利要求9所述的制造方法,其中,去除部分该氧化层使剩余该氧化物层厚度在1000至2000埃之间。
14.如权利要求9所述的制造方法,其中,该氮化物层及该氮化物间隙壁为氮化硅。
15.如权利要求9所述的制造方法,氮化物间隙壁蚀刻时是利用过蚀刻法使第一多晶硅间隙壁顶部露出600至1500埃之间。
16.一种在一存储节接触窗上形成一下存储节的制造方法,在一层间介电层及一氮化物层中形成该存储节接触窗,该方法包括下列步骤:
在该存储节接触窗上形成一皇冠型多晶硅结构,该皇冠型多晶硅结构已具有一氧化层填充部分该皇冠型多晶硅结构;
在该皇冠型多晶硅结构的内侧及外侧形成一氮化物间隙壁,该氮化物间隙壁并不延伸至该皇冠型多晶硅结构的顶部;
在该皇冠型多晶硅结构及该氮化物间隙壁上,形成一第二多晶硅间隙壁;
去除该氧化层;以及
去除该氮化物间隙壁及该氮化物层。
17.如权利要求16所述的制造方法,其中,该氮化物层厚度在1500至2000埃之间。
18.如权利要求16所述的制造方法,其中,该氧化层厚度在1000至2000埃之间。
19.如权利要求16所述的制造方法,其中,该氮化物层及该氮化物间隙壁为氮化硅。
20.如权利要求16所述的制造方法,氮化物间隙壁蚀刻时是利用过蚀刻法使第一多晶硅间隙壁顶部露出600至1500埃之间。
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US09/118,170 US6107139A (en) | 1998-07-17 | 1998-07-17 | Method for making a mushroom shaped DRAM capacitor |
US118170 | 1998-07-17 | ||
US118,170 | 1998-07-17 |
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US6333225B1 (en) * | 1999-08-20 | 2001-12-25 | Micron Technology, Inc. | Integrated circuitry and methods of forming circuitry |
US6429087B2 (en) * | 1999-08-30 | 2002-08-06 | Micron Technology, Inc. | Methods of forming capacitors |
DE10138585A1 (de) * | 2001-08-06 | 2003-03-06 | Infineon Technologies Ag | Speicherzelle |
US6906371B2 (en) * | 2002-08-12 | 2005-06-14 | Infineon Technologies Ag | Wordline gate contact for an MBIT transistor array layout |
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US5444010A (en) * | 1993-05-13 | 1995-08-22 | Hyundai Electronics Industries, Ltd. | Method for forming a stacked capacitor in a semiconductor device |
US5464787A (en) * | 1993-12-30 | 1995-11-07 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device and a method of manufacturing the same |
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US5731130A (en) * | 1996-11-12 | 1998-03-24 | Vanguard International Semiconductor Corporation | Method for fabricating stacked capacitors on dynamic random access memory cells |
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US5643819A (en) * | 1995-10-30 | 1997-07-01 | Vanguard International Semiconductor Corporation | Method of fabricating fork-shaped stacked capacitors for DRAM cells |
US5856220A (en) * | 1996-02-08 | 1999-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a double wall tub shaped capacitor |
KR100207463B1 (ko) * | 1996-02-26 | 1999-07-15 | 윤종용 | 반도체 장치의 커패시터 제조방법 |
TW308727B (en) * | 1996-08-16 | 1997-06-21 | United Microelectronics Corp | Semiconductor memory device with capacitor (4) |
US5759890A (en) * | 1996-08-16 | 1998-06-02 | United Microelectronics Corporation | Method for fabricating a tree-type capacitor structure for a semiconductor memory device |
US5792688A (en) * | 1996-11-06 | 1998-08-11 | Vanguard International Semiconductor Corporation | Method to increase the surface area of a storage node electrode, of an STC structure, for DRAM devices, via formation of polysilicon columns |
US5902124A (en) * | 1997-05-28 | 1999-05-11 | United Microelectronics Corporation | DRAM process |
US5849617A (en) * | 1997-06-24 | 1998-12-15 | Powerchip Semiconductor Corp. | Method for fabricating a nested capacitor |
US5792692A (en) * | 1997-08-18 | 1998-08-11 | Chartered Semiconductor Manufacturing, Ltd. | Method of fabricating a twin hammer tree shaped capacitor structure for a dram device |
US5930622A (en) * | 1997-10-20 | 1999-07-27 | Texas Instruments-Acer Incorporated | Method for forming a DRAM cell with a double-crown shaped capacitor |
US5926719A (en) * | 1997-10-29 | 1999-07-20 | Vanguard International Semiconductor Corporation | Method for fabricating a crown shaped capacitor structure |
TW395052B (en) * | 1998-08-18 | 2000-06-21 | United Microelectronics Corp | Method of manufacturing the capacitor of dynamic random access memory (DRAM) |
US5994197A (en) * | 1999-05-27 | 1999-11-30 | United Silicon Incorporated | Method for manufacturing dynamic random access memory capable of increasing the storage capacity of the capacitor |
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1998
- 1998-07-17 US US09/118,170 patent/US6107139A/en not_active Expired - Lifetime
- 1998-09-01 TW TW087114451A patent/TW383499B/zh not_active IP Right Cessation
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Publication number | Priority date | Publication date | Assignee | Title |
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US5444010A (en) * | 1993-05-13 | 1995-08-22 | Hyundai Electronics Industries, Ltd. | Method for forming a stacked capacitor in a semiconductor device |
US5464787A (en) * | 1993-12-30 | 1995-11-07 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device and a method of manufacturing the same |
US5731130A (en) * | 1996-11-12 | 1998-03-24 | Vanguard International Semiconductor Corporation | Method for fabricating stacked capacitors on dynamic random access memory cells |
US5726086A (en) * | 1996-11-18 | 1998-03-10 | Mosel Vitelic Inc. | Method of making self-aligned cylindrical capacitor structure of stack DRAMS |
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US6107139A (en) | 2000-08-22 |
TW383499B (en) | 2000-03-01 |
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