CN112106031A - Control method, control equipment, control chip and storage medium - Google Patents
Control method, control equipment, control chip and storage medium Download PDFInfo
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Abstract
A control method, a device, a chip and a storage medium, wherein the method comprises the following steps: acquiring the power supply voltage of the chip; when the power supply voltage is smaller than a preset voltage threshold, turning off a flash memory controller in the chip; the flash memory controller is connected with the flash memory, the initial state of data in the flash memory is read only, and when the flash memory acquires an unlocking instruction sent by the flash memory controller, the flash memory can respond to a writing and/or erasing instruction. By the implementation mode, the external memory can be effectively subjected to power-down protection on the basis of not increasing the hardware cost.
Description
Technical Field
The present invention relates to the field of data processing, and in particular, to a control method, device, chip, and storage medium.
Background
Since Flash memory (Flash memory) can store data without current supply and has a Non-Volatile (Non-Volatile) characteristic, most of the embedded products use a design structure of a Micro Controller Unit (MCU) and a Flash memory, and the MCU can read or erase data in the Flash memory. However, most products do not add a power-down protection mechanism for the flash memory, so that when the chip is powered down, data in the flash memory may be abnormally erased.
Disclosure of Invention
The embodiment of the invention discloses a control method, control equipment, a control chip and a storage medium, which can effectively carry out power failure protection on an external memory on the basis of not increasing hardware cost.
In a first aspect, an embodiment of the present invention provides a control method, including:
acquiring the power supply voltage of the chip;
when the power supply voltage is smaller than a preset voltage threshold, turning off a flash memory controller in the chip;
the flash memory controller is connected with the flash memory, the initial state of data in the flash memory is read only, and when the flash memory acquires an unlocking instruction sent by the flash memory controller, the flash memory can respond to a writing and/or erasing instruction.
In a second aspect, an embodiment of the present invention provides a control apparatus, including: a memory and a processor, wherein the processor is capable of,
the memory is used for storing programs;
the processor to execute the memory-stored program, the processor to, when executed:
acquiring the power supply voltage of the chip;
when the power supply voltage is smaller than a preset voltage threshold, turning off a flash memory controller in the chip;
the flash memory controller is connected with the flash memory, the initial state of data in the flash memory is read only, and when the flash memory acquires an unlocking instruction sent by the flash memory controller, the flash memory can respond to a writing and/or erasing instruction.
In a third aspect, an embodiment of the present invention provides a chip, including:
a flash memory controller and a control device according to the second aspect.
In a fourth aspect, the present invention provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the method according to the first aspect.
The embodiment of the invention can obtain the power supply voltage of the chip, and when the power supply voltage is smaller than the preset voltage threshold, the flash memory controller in the chip is turned off, wherein the flash memory controller is connected with the flash memory, the initial state of data in the flash memory is read only, and when the flash memory obtains the unlocking instruction sent by the flash memory controller, the flash memory can respond to the writing and/or erasing instruction. By the implementation mode, the external memory can be effectively subjected to power-down protection on the basis of not increasing the hardware cost.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.
Fig. 1 is a schematic flow chart of a control method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a flash memory according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a control device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Since flash memory can store data even without current supply and has a Non-Volatile (Non-Volatile) characteristic, most embedded products use a design structure of a micro control unit MCU plus flash memory. In one example, the design structure of the MCU and the flash memory is disposed in the unmanned aerial vehicle, the battery of the unmanned aerial vehicle supplies power to the MCU after voltage division, and the MCU sends commands to the flash memory through the flash memory controller in the MCU, including a READ (READ) command, an ERASE (ERASE) command, and a WRITE (WRITE) command.
In practice, it is found that when the unmanned aerial vehicle is shut down, the power supply voltage provided to the MCU gradually decreases, and the flash memory controller in the MCU may send an erase command to the flash memory abnormally, which may cause the computer program and the operating parameters originally stored in the flash memory to be erased, thereby causing the unmanned aerial vehicle to not fly normally when the user starts up the unmanned aerial vehicle next time.
At present, most products are not added with a power failure protection mechanism for an external flash memory, and the power failure protection requirement for the external flash memory cannot be met.
The embodiment of the invention sets the initial state of the data in the flash memory as read-only, and can respond to the writing and/or erasing instruction when the flash memory receives an Unlocking (UNLOCK) instruction sent by a flash memory controller. That is, when the flash memory controller abnormally sends an erase command to the flash memory when the power supply voltage of the chip decreases, the erase command is responded only under the condition that the flash memory receives the unlock command, otherwise, the erase command is not responded, and thus, the probability that the flash memory is abnormally erased can be reduced.
In addition, the embodiment of the invention detects the power supply voltage of the chip in real time, compares the power supply voltage with the preset voltage threshold, and turns off the flash memory controller when the power supply voltage is smaller than the preset voltage threshold, so that the flash memory controller cannot send any command to the flash memory. Therefore, the situation that the unlocking instruction is abnormally generated when the power supply voltage of the chip is reduced can be avoided, and the flash memory can respond to the writing and/or erasing instruction after the flash memory controller sends the unlocking instruction to the flash memory.
By the implementation mode, the data in the flash memory can be effectively subjected to power failure protection on the basis of not increasing the hardware cost, and the content in the flash memory is prevented from being updated abnormally.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The control method provided in the embodiment of the present invention may be executed by a chip, where the chip may include a flash memory controller and a control device. In some embodiments, the flash memory is connected to a flash memory controller in the chip as an external memory of the chip. In some embodiments, the chip may be disposed on a mobile device such as an unmanned aerial vehicle, an unmanned ship, or a mobile robot, and the embodiments of the present invention are not limited in particular.
The following describes schematically a control method provided by an embodiment of the present invention with reference to the drawings.
Referring to fig. 1 specifically, fig. 1 is a schematic flowchart of a control method according to an embodiment of the present invention, where the method may be executed by a control device, and a specific explanation of the control device is as described above. Specifically, the method of the embodiment of the present invention includes the following steps.
S101: and acquiring the power supply voltage of the chip.
In the embodiment of the invention, the control equipment can obtain the power supply voltage of the chip. In some embodiments, the control device may obtain, through the processor, a supply voltage of the chip, and in some embodiments, the chip may be an MCU chip.
In one embodiment, the power supply battery is connected to a plurality of modules, the plurality of modules include a chip, and the power supply voltage of the chip may be a voltage obtained from the power supply battery, or a voltage provided by the power supply battery to the chip, or a voltage obtained after the voltage of the power supply battery is processed, such as voltage division.
S102: and when the power supply voltage is smaller than a preset voltage threshold, turning off a flash memory controller in the chip.
In the embodiment of the present invention, when the power supply voltage is smaller than the preset voltage threshold, the control device may turn off the flash memory controller in the chip. In some embodiments, the flash memory controller may be connected to a flash memory, an initial state of data in the flash memory is read only, and the flash memory is capable of responding to a write and/or erase command when the flash memory obtains an unlock command sent by the flash memory controller.
In some embodiments, the chip includes a voltage Comparator inside, which in one example may be an Analog Comparator (ACMP).
In an embodiment, after monitoring the power supply voltage of the chip, the control device may compare the real-time monitored power supply voltage with a preset voltage threshold through a voltage comparator in the chip, and when the comparison result shows that the power supply voltage is smaller than the preset voltage threshold, the control device may turn off the flash memory controller in the chip.
In an example, the voltage required by the chip during operation is at least 2.6v, that is, when the power supply voltage of the chip is less than 2.6v, the chip may trigger some abnormal commands, so that it may be determined that the preset voltage threshold is 2.6v, and if the power supply voltage of the chip is monitored to be 2.5v in real time, the real-time monitored power supply voltage 2.5v is compared with the preset voltage threshold 2.6v by a voltage comparator in the chip, and when the power supply voltage 2.5v is less than the preset voltage threshold 2.6v, the control device may turn off the flash memory controller in the chip.
In some embodiments, the power supply voltage may be a voltage supplied to the chip, the preset voltage threshold may be determined according to a voltage required by the chip when the chip operates, and the chip may trigger an abnormal command when the voltage supplied to the chip is less than the preset voltage threshold.
In some embodiments, the power supply voltage may also be a battery voltage, and the preset voltage threshold may be determined according to the battery voltage and a voltage required by the chip when operating. Specifically, the voltage may be determined according to a ratio of a battery voltage to a voltage required by the chip when the chip operates, and when the battery voltage is less than a preset voltage threshold, the chip may trigger an abnormal command.
In some embodiments, the power supply voltage may also be a voltage obtained by dividing or the like the battery voltage, and the preset voltage threshold may be determined according to the voltage obtained by dividing or the like the battery voltage and a voltage required by the chip during operation. Specifically, the voltage may be determined according to a ratio of a voltage obtained after the battery voltage is subjected to voltage division and the like and a voltage required by the chip during operation, and when the voltage obtained after the battery voltage is subjected to voltage division and the like is smaller than a preset voltage threshold, the chip may trigger an abnormal command.
Taking the unmanned aerial vehicle as an example, the unmanned aerial vehicle comprises a chip, a flash memory controller in the chip is connected with a flash memory, the initial state of data in the flash memory is read only, and when the flash memory receives an unlocking instruction sent by the flash memory controller, the flash memory can respond to a writing and/or erasing instruction.
For example, during flight of the unmanned aerial vehicle, the computer program and the operating parameters in the flash memory can be read for controlling the flight of the unmanned aerial vehicle; when the firmware of the unmanned aerial vehicle needs to be updated, an unlocking instruction is generated in the chip, and after the flash memory controller sends the unlocking instruction to the flash memory, the flash memory can respond to the writing and/or erasing instruction so as to update the computer program or the operating parameters in the flash memory.
The initial state of the data in the flash memory is set to be read only, and the write and/or erase instruction can be responded when the flash memory receives the unlocking instruction. Therefore, when the flash memory controller abnormally sends the erasing instruction to the flash memory, the erasing instruction can be responded only under the condition that the flash memory receives the unlocking instruction, and the probability that the flash memory is abnormally erased can be effectively reduced.
The battery of the unmanned aerial vehicle supplies power to the plurality of modules comprising the chip, the voltage comparator in the chip compares the power supply voltage of the chip with a preset voltage threshold value, the power supply voltage of the chip is monitored in real time, and when the power supply voltage is reduced to be smaller than the preset voltage threshold value, the flash memory controller in the chip is turned off. The supply voltage may be a battery voltage of the unmanned aerial vehicle, a voltage supplied to the chip, or a voltage after being subjected to voltage division or the like.
When the power supply voltage of the chip is smaller than the preset voltage threshold, an unlocking instruction may be abnormally generated, and after the flash memory controller sends the unlocking instruction to the flash memory, the flash memory can respond to a writing and/or erasing instruction. Therefore, when the power supply voltage is smaller than the preset voltage threshold, the flash memory controller in the chip is turned off, the power supply voltage of the chip can be prevented from dropping, and when an unlocking command is abnormally generated, the flash memory controller sends the unlocking command to the flash memory, so that the flash memory can respond to a writing and/or erasing command.
By the implementation mode, the problem that the unmanned aerial vehicle cannot be normally started when the unmanned aerial vehicle is started next time due to abnormal erasure of the computer program and the operation parameters in the flash memory in the process that the power supply voltage of the chip is gradually reduced when the unmanned aerial vehicle is shut down can be avoided.
In one embodiment, when the flash controller in the chip is turned off, the control device may send an interrupt control instruction to a clock controller in the chip, where the interrupt control instruction is used to instruct to turn off the clock of the flash controller.
For example, if the control device compares the real-time monitored power supply voltage 2.5v with the preset voltage threshold 2.6v through the voltage comparator of the chip, and obtains that the power supply voltage 2.5v is smaller than the preset voltage threshold 2.6v, the control device may send an interrupt control instruction to the clock controller, so that the clock controller turns off the clock of the flash memory controller according to the instruction of the interrupt control instruction.
Therefore, through the implementation of turning off the clock of the flash memory controller, the flash memory controller of the chip can be turned off, so as to ensure that the flash memory controller does not send out abnormal operating instructions.
In one embodiment, the flash memory is an external memory of the chip, and stores a computer program and operating parameters.
In one embodiment, the flash memory includes a plurality of data blocks, the unlocking instruction carries a data block identifier, and a data block corresponding to the data block identifier in the flash memory can respond to a write and/or erase instruction.
Specifically, fig. 2 is an exemplary illustration, and fig. 2 is a schematic structural diagram of a flash memory according to an embodiment of the present invention, as shown in fig. 2, the flash memory includes a plurality of data blocks, such as data block 0, data block 1 to data block 30, and data block 31, and fig. 2 does not show data block 2 to data block 29. Wherein the initial state of each data block is in a read-only state. Assuming that the data block identifier 1 corresponding to the data block 1 is carried in the unlocking instruction obtained by the flash memory, the flash memory may unlock the data block 1 corresponding to the data block identifier 1 according to the data block identifier 1 carried in the unlocking instruction, that is, the data block 1 may further respond to the write-in and/or erase instruction sent by the flash memory controller.
Therefore, by the implementation, when the unlocking instruction for a certain data block is obtained, only the data block is unlocked, and all data in the flash memory are not required to be unlocked when the certain data block is updated, so that flexible updating of the data can be realized, and when the data of the certain data block is updated, the data of other data blocks are ensured not to be modified or erased, and the safety of the data in the flash memory is improved.
As shown in fig. 2, each data block in the flash memory may be further divided into a plurality of data blocks for protection, for example, data block 0 is divided into 16 data blocks for protection, that is, the 16 data blocks are data block 0, data block 1, data block 14, and data block 15. The data block in the data block 1 and the data block in the data block 30 are not shown in fig. 2, and similarly, each of the other data blocks may be equally divided into 16 data blocks for protection. The data block identification further comprises address information of the data blocks, and the data blocks needing to be used can be more flexibly unlocked through the implementation mode, so that the risk of influencing other data blocks is reduced, and the safety of other data blocks is further improved.
In one embodiment, when a data block corresponding to the data block identifier in the flash memory responds to a write and/or erase command, the flash memory controller is further configured to detect an update status of the data block corresponding to the data block identifier.
In an embodiment, the control device may obtain an update completion instruction sent by the flash memory controller, where the update completion instruction carries the data block identifier, and send a LOCK (LOCK) instruction to the flash memory through the flash memory controller, where the LOCK instruction is used to instruct to LOCK the data block corresponding to the data block identifier.
That is to say, when the flash memory controller detects that the data block corresponding to the data block identifier is completely updated, the flash memory controller sends an update completion instruction to the control device, and after receiving the update completion instruction, the control device sends a lock instruction to the flash memory controller, so that the data in the data block is restored to a read-only state after being completely updated, and the security of the data in the flash memory is improved.
Taking fig. 2 as an example, assuming that the unlocking instruction carries the data block identifier 1 of the data block 1, after detecting that the data block 1 corresponding to the data block identifier 1 is updated, the flash memory controller may generate an update completion instruction, and send the update completion instruction to the control device. When the control device acquires the update completion instruction sent by the flash memory controller, the control device may generate a locking instruction according to the data block identifier 1 of the data block 1 carried in the update completion instruction, and send the locking instruction to the flash memory through the flash memory controller, so that the data block 1 in the flash memory is locked.
Therefore, the data block after the updating is completed can be locked again through the implementation mode, so that the data block is prevented from being modified or erased abnormally, and the safety of the data block is further improved.
In the embodiment of the present invention, the control device may obtain a power supply voltage of the chip, and turn off the flash memory controller in the chip when the power supply voltage is smaller than a preset voltage threshold, where the flash memory controller is connected to the flash memory, an initial state of data in the flash memory is read only, and when the flash memory obtains an unlock instruction sent by the flash memory controller, the flash memory can respond to a write-in and/or erase instruction. By the implementation mode, the data in the flash memory can be effectively subjected to power failure protection on the basis of not increasing the hardware cost.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a control device according to an embodiment of the present invention. Specifically, the control device includes: memory 301, processor 302.
In one embodiment, the control device further comprises a data interface 303, wherein the data interface 303 is used for transmitting data information between the control device and other devices.
The memory 301 may include a volatile memory (volatile memory); the memory 301 may also include a non-volatile memory (non-volatile memory); the memory 301 may also comprise a combination of the above types of memory. The processor 302 may be a Central Processing Unit (CPU). The processor 302 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), or any combination thereof.
The memory 301 is used for storing programs, and the processor 302 can call the programs stored in the memory 301 to execute the following steps:
acquiring the power supply voltage of the chip;
when the power supply voltage is smaller than a preset voltage threshold, turning off a flash memory controller in the chip;
the flash memory controller is connected with the flash memory, the initial state of data in the flash memory is read only, and when the flash memory acquires an unlocking instruction sent by the flash memory controller, the flash memory can respond to a writing and/or erasing instruction.
Further, the flash memory is an external memory of the chip, and stores a computer program and operating parameters.
Further, the chip includes a clock controller, and when the memory 301 turns off the flash memory controller in the chip, the chip is specifically configured to:
and sending an interrupt control instruction to the clock controller, wherein the interrupt control instruction is used for indicating to turn off the clock of the flash memory controller.
Further, the flash memory includes a plurality of data blocks, the unlocking instruction carries a data block identifier, and a data block corresponding to the data block identifier in the flash memory can respond to a write-in and/or erase instruction.
Further, when the data block corresponding to the data block identifier in the flash memory responds to a write and/or erase command, the flash memory controller is further configured to detect an update status of the data block corresponding to the data block identifier.
Further, the processor 302 is further configured to:
acquiring an update completion instruction sent by the flash memory controller, wherein the update completion instruction carries the data block identifier;
and sending a locking instruction to the flash memory through the flash memory controller, wherein the locking instruction is used for indicating to lock the data block corresponding to the data block identifier.
Further, the preset voltage threshold is determined according to the voltage required by the chip during operation.
In the embodiment of the present invention, the control device may obtain a power supply voltage of a chip, and turn off the flash memory controller in the chip when the power supply voltage is smaller than a preset voltage threshold, where the flash memory controller is connected to the flash memory, an initial state of data in the flash memory is read only, and when the flash memory obtains an unlock instruction sent by the flash memory controller, the flash memory may respond to a write and/or erase instruction. By the implementation mode, the external memory can be effectively subjected to power-down protection on the basis of not increasing the hardware cost.
An embodiment of the present invention further provides a chip, including: flash memory controller and above-mentioned control device.
Further, the flash memory controller is connected with a flash memory, and the flash memory is an external memory of the chip and stores a computer program and operating parameters.
The embodiment of the invention can obtain the power supply voltage of the chip, and when the power supply voltage is smaller than the preset voltage threshold, the flash memory controller in the chip is turned off, wherein the flash memory controller is connected with the flash memory, the initial state of data in the flash memory is read only, and when the flash memory obtains the unlocking instruction sent by the flash memory controller, the flash memory can respond to the writing and/or erasing instruction. By the implementation mode, the power failure protection can be effectively carried out on the external memory on the basis of not increasing the hardware cost, and the resource occupancy rate is reduced.
The embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method described in the embodiment corresponding to fig. 1 of the present invention is implemented, and the apparatus according to the embodiment corresponding to the present invention described in fig. 3 may also be implemented, which is not described herein again.
The computer readable storage medium may be an internal storage unit of the device according to any of the foregoing embodiments, for example, a hard disk or a memory of the device. The computer readable storage medium may also be an external storage device of the device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), etc. provided on the device.
Further, the computer-readable storage medium may also include both an internal storage unit and an external storage device of the apparatus. The computer-readable storage medium is used for storing the computer program and other programs and data required by the terminal. The computer readable storage medium may also be used to temporarily store data that has been output or is to be output.
The above disclosure is intended to be illustrative of only some embodiments of the invention, and is not intended to limit the scope of the invention.
Claims (17)
1. A control method, comprising:
acquiring the power supply voltage of the chip;
when the power supply voltage is smaller than a preset voltage threshold, turning off a flash memory controller in the chip;
the flash memory controller is connected with the flash memory, the initial state of data in the flash memory is read only, and when the flash memory acquires an unlocking instruction sent by the flash memory controller, the flash memory can respond to a writing and/or erasing instruction.
2. The method of claim 1,
the flash memory is an external memory of the chip and stores a computer program and operating parameters.
3. The method of claim 1, wherein the chip includes a clock controller, and wherein turning off the flash controller in the chip comprises:
and sending an interrupt control instruction to the clock controller, wherein the interrupt control instruction is used for indicating to turn off the clock of the flash memory controller.
4. The method of claim 1,
the flash memory comprises a plurality of data blocks, the unlocking instruction carries a data block identifier, and the data block corresponding to the data block identifier in the flash memory can respond to a writing and/or erasing instruction.
5. The method as claimed in claim 4, wherein the flash memory controller is further configured to detect an update status of the data block corresponding to the data block identifier when the data block corresponding to the data block identifier in the flash memory responds to a write and/or erase command.
6. The method of claim 5, further comprising:
acquiring an update completion instruction sent by the flash memory controller, wherein the update completion instruction carries the data block identifier;
and sending a locking instruction to the flash memory through the flash memory controller, wherein the locking instruction is used for indicating to lock the data block corresponding to the data block identifier.
7. The method of claim 1, wherein the predetermined voltage threshold is determined according to a voltage required by the chip to operate.
8. A control apparatus, characterized by comprising: a memory and a processor, wherein the processor is capable of,
the memory is used for storing programs;
the processor to execute the memory-stored program, the processor to, when executed:
acquiring the power supply voltage of the chip;
when the power supply voltage is smaller than a preset voltage threshold, turning off a flash memory controller in the chip;
the flash memory controller is connected with the flash memory, the initial state of data in the flash memory is read only, and when the flash memory acquires an unlocking instruction sent by the flash memory controller, the flash memory can respond to a writing and/or erasing instruction.
9. The apparatus of claim 8,
the flash memory is an external memory of the chip and stores a computer program and operating parameters.
10. The device of claim 8, wherein the chip comprises a clock controller, and wherein the processor, when turning off the flash controller in the chip, is specifically configured to:
and sending an interrupt control instruction to the clock controller, wherein the interrupt control instruction is used for indicating to turn off the clock of the flash memory controller.
11. The apparatus of claim 8,
the flash memory comprises a plurality of data blocks, the unlocking instruction carries a data block identifier, and the data block corresponding to the data block identifier in the flash memory can respond to a writing and/or erasing instruction.
12. The apparatus of claim 11,
when the data block corresponding to the data block identifier in the flash memory responds to a write and/or erase command, the flash memory controller is further configured to detect an update status of the data block corresponding to the data block identifier.
13. The device of claim 12, wherein the processor is further configured to:
acquiring an update completion instruction sent by the flash memory controller, wherein the update completion instruction carries the data block identifier;
and sending a locking instruction to the flash memory through the flash memory controller, wherein the locking instruction is used for indicating to lock the data block corresponding to the data block identifier.
14. The apparatus of claim 8, wherein the preset voltage threshold is determined according to a voltage required by the chip to operate.
15. A chip, comprising:
a flash memory controller and a control device as claimed in any one of claims 8 to 14.
16. The chip of claim 15,
the flash memory controller is connected with the flash memory, the flash memory is an external memory of the chip, and computer programs and operating parameters are stored in the flash memory.
17. A computer-readable storage medium having a computer program stored therein, characterized in that: the computer program realizing the steps of the method according to any one of claims 1 to 7 when executed by a processor.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016106935A1 (en) * | 2014-12-30 | 2016-07-07 | 北京兆易创新科技股份有限公司 | Flash memory controller and control method for flash memory controller |
| CN106155258A (en) * | 2015-03-27 | 2016-11-23 | 华为技术有限公司 | The circuit of a kind of power down protection and correlation technique |
| CN109411002A (en) * | 2017-08-15 | 2019-03-01 | 华为技术有限公司 | A kind of method and flash controller of reading data |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100255956B1 (en) * | 1997-07-16 | 2000-05-01 | 윤종용 | Ferroelectric memory device and data protection method thereof |
| US6166960A (en) * | 1999-09-24 | 2000-12-26 | Microchip Technology, Incorporated | Method, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an eeprom |
| US9245619B2 (en) * | 2014-03-04 | 2016-01-26 | International Business Machines Corporation | Memory device with memory buffer for premature read protection |
| CN206401032U (en) * | 2016-12-28 | 2017-08-11 | 深圳市航盛电子股份有限公司 | A kind of protection circuit of FLASH abnormity of power supply down Monitor Unit |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016106935A1 (en) * | 2014-12-30 | 2016-07-07 | 北京兆易创新科技股份有限公司 | Flash memory controller and control method for flash memory controller |
| CN106155258A (en) * | 2015-03-27 | 2016-11-23 | 华为技术有限公司 | The circuit of a kind of power down protection and correlation technique |
| CN109411002A (en) * | 2017-08-15 | 2019-03-01 | 华为技术有限公司 | A kind of method and flash controller of reading data |
Non-Patent Citations (1)
| Title |
|---|
| 赵鹏;白石;: "基于随机游走的大容量固态硬盘磨损均衡算法", 计算机学报, no. 05, 15 May 2012 (2012-05-15) * |
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