CN112105119B - Controller for power converter - Google Patents
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- CN112105119B CN112105119B CN202010553598.2A CN202010553598A CN112105119B CN 112105119 B CN112105119 B CN 112105119B CN 202010553598 A CN202010553598 A CN 202010553598A CN 112105119 B CN112105119 B CN 112105119B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/32—Pulse-control circuits
- H05B45/325—Pulse-width modulation [PWM]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/10—Controlling the intensity of the light
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
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Abstract
The application relates to current control for a power converter. The present disclosure relates to accurate analog dimming of Light Emitting Diodes (LEDs). Accurate dimming may require a power converter that precisely controls the current supplied to the LED. Accurate control relies on accurately sensing the level of the LED. When the power converter is operated in Discontinuous Conduction Mode (DCM), for example, at low dimming ratios, the accuracy of the sensed LED level may be affected by the resonant current offset caused by the current oscillation in the power converter. The disclosed circuits and methods provide accurate control of the sensed LED level by compensating for resonant current offset in the LED level.
Description
Cross Reference to Related Applications
The present application claims priority from U.S. patent application Ser. No. 16/787,343, filed on 11/2/2020, which claims the benefit of U.S. provisional application Ser. No. 62/863,189, filed on 18/6/2019. These patent applications are incorporated by reference herein in their entirety.
Technical Field
The present disclosure relates to feedback control of a power converter circuit (i.e., a converter circuit) based on load level measurements, and more particularly to a circuit and method for correcting (i.e., compensating) load level measurements of resonant current that is generated when the converter circuit operates in Discontinuous Current Mode (DCM).
Background
Advances in Light Emitting Diode (LED) technology have enabled consumers to replace traditional lighting. If dimming can be done over a wide range without changing its quality or causing other noticeable artifacts, it may be desirable to increase lighting characteristics such as dimming. Dimming of the LEDs may be achieved using a switching method (i.e., PWM dimming) or an analog method (i.e., analog dimming). In analog dimming, a constant current through the LED is adjusted to increase or decrease the light intensity of the LED. Analog dimming may reduce or eliminate some of the drawbacks associated with the switching method, such as noticeable audible noise associated with the switch or flicker in the light noticeable to the eye or video recording device. However, analog dimming faces the challenge of providing a wide dimming range that can accurately control the light intensity of the LED. Embodiments of the present disclosure are presented in this context.
Disclosure of Invention
In at least one aspect, the present disclosure generally describes a system (e.g., an LED system). The system includes a converter circuit (e.g., a buck converter circuit) configured to generate a current or voltage based on a pulse width modulated signal (i.e., a PWM signal), wherein each cycle of the PWM signal includes an on portion and an off portion according to a duty cycle of the PWM signal. The system also includes a load (e.g., an LED) configured to receive the current or voltage generated by the converter circuit, the level of the current or voltage generated by the converter circuit corresponding to the duty cycle of the PWM signal. The system also includes a controller (e.g., a current controller) configured to adjust a duty cycle of the PWM signal based on a comparison between a reference level and a load level (e.g., an LED level), the load level corresponding to a measurement of the load level. The measurement of the load level includes a compensation period for correcting an offset between the PWM signal and the current sense signal (corresponding to the current through the transistor of the converter circuit) during the on portion of the PWM signal.
In at least one other aspect, the present disclosure generally describes a controller for a buck converter. The controller includes a duty cycle generation circuit configured to generate a Pulse Width Modulation (PWM) signal that configures the buck converter to provide current to a load coupled to the buck converter. The level of the current corresponds to the duty cycle of the PWM signal. The controller for the buck converter further includes a measurement circuit coupled to the duty cycle generation circuit and configured to determine a load. The determination is based on the current sense signal, the PWM signal, and the compensation period. When the buck converter operates in Discontinuous Conduction Mode (DCM), the compensation period corresponds to an offset between the PWM signal and the current sense signal.
In at least another aspect, the present disclosure generally describes a method for driving an LED. The method includes detecting a Pulse Width Modulation (PWM) signal including a PWM cycle. Each PWM cycle includes an on portion and an off portion. The method further includes detecting a current sense signal during the on portion, the current sense signal corresponding to the LED current and increasing during the on portion. The method further includes determining a compensation time related to an offset between a start time of the on portion of the PWM cycle and a time when the current sense signal increases above zero. The method further includes determining a current sense voltage (e.g., half-peak current sense voltage) by sampling the current sense signal at a time adjusted by the compensation time. The method further includes detecting a drain voltage corresponding to the LED current during the off portion and decreasing during the off portion. The method further includes determining a discharge time associated with a period between a start time of the off portion of the PWM cycle and a time when the drain voltage decreases to zero. The method further includes determining a turn-on time of the LED based on the time of the turn-on portion, the discharge time, and the compensation time. The method further includes multiplying the current sense voltage (e.g., half-peak current sense voltage) and the on-time to determine the LED level. The method further includes comparing the LED level to a reference level, adjusting a duty cycle of the PWM signal, and applying the PWM signal to a buck converter that drives the LED.
The foregoing illustrative summary, as well as other exemplary objects and/or advantages, and implementations of the present disclosure, are further explained in the following detailed description and the accompanying drawings thereof.
Drawings
Fig. 1 is a block diagram of an LED system with dimming control according to an embodiment of the present disclosure.
Fig. 2A is a time-based plot of signals associated with the LED system of fig. 1 operating in a Continuous Conduction Mode (CCM) according to a possible embodiment of the present disclosure.
Fig. 2B is a time-based plot of signals associated with the LED system of fig. 1 operating in Discontinuous Conduction Mode (DCM) according to a possible embodiment of the present disclosure.
Fig. 3 is a graph of LED current (I LED) versus dimming ratio according to a possible embodiment of the present disclosure.
Fig. 4A is a time-based plot of signals associated with the LED system of fig. 1, showing negative resonant current excursions, according to a possible embodiment of the present disclosure.
Fig. 4B is a time-based plot of signals associated with the LED system of fig. 1, showing a positive resonant current offset, according to a possible embodiment of the present disclosure.
Fig. 5 is a block diagram of a resonant offset compensation circuit according to a possible embodiment of the present disclosure.
Fig. 6 is a time-based plot of signals associated with the resonant offset compensation circuit of fig. 5 according to a possible embodiment of the present disclosure.
Fig. 7 graphically illustrates the determination of a compensation period (T COMP) according to a possible embodiment of the present disclosure.
Fig. 8A is a block diagram of a first possible implementation of a Current Sense (CS) comparator for the possible implementation of the resonant offset compensation circuit of fig. 5.
Fig. 8B is a time-based signal associated with the CS comparator of fig. 8A.
Fig. 9A is a block diagram of a second possible implementation of a Current Sense (CS) comparator for the possible implementation of the resonant offset compensation circuit of fig. 5.
Fig. 9B is a time-based signal associated with the CS comparator of fig. 9A.
Fig. 10 is a block diagram of an LED level measurement circuit according to a possible embodiment of the present disclosure.
Fig. 11 is a block diagram of a duty cycle generation circuit according to a possible embodiment of the present disclosure.
Fig. 12 is a detailed block diagram of an LED system with dimming control according to an embodiment of the present disclosure.
Fig. 13 is a flowchart of a method for driving an LED according to an embodiment of the present disclosure.
Fig. 14 and 15 show variations of the embodiments described herein.
The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.
Detailed Description
The present disclosure describes a circuit and method for accurately controlling a converter circuit, particularly when the converter circuit is operating in Discontinuous Current Mode (DCM) to deliver current or voltage to a load. The disclosed circuits and methods may be implemented for analog dimming of LEDs and may address the lack of accurate dimming control at low light levels of LEDs. The disclosed circuits and methods may provide the advantageous result of extending the controllable range of LED light levels without using pulsed dimming, which may have undesirable flicker or noise.
Analog dimming uses direct control of the current level through the LED to adjust its brightness (i.e., level). Fig. 1 is a block diagram of an LED system with dimming control. In system 100, an asynchronous (single switch) switch mode DC-DC converter is used to power the LED diodes (D LED). As shown, the converter may be implemented as a buck converter circuit 110 (i.e., buck converter). The concepts described herein may also be implemented in a boost converter circuit or a buck-boost converter circuit.
Buck converter 110 may include a switch (e.g., transistor Q BUCK), an inductor (L BUCK), and a diode (D BUCK). Buck converter 110 is configured to receive an input voltage (V IN) and output a substantially constant current (I L) to a load. For example, the buck converter outputs a substantially constant current to the LED diode such that the LED produces light of a particular brightness. To regulate the current (i.e., brightness), a pulse width modulated signal (i.e., PWM signal (V PWM)) is applied to the control (e.g., gate) terminal of the transistor (Q BUCK) to cycle the transistor on and off. The PWM signal (V PWM) has a duty cycle defined by the percentage of time that the transistor is on (i.e., turned on) and the total time of the on/off cycle (i.e., period). When the transistor (Q BUCK) is on, the input voltage induces a current (I L) through the LED (D LED) and the inductor (L BUCK) to ground through the turned-on transistor (Q BUCK). When the transistor (Q BUCK) is off, the charged inductor (L BUCK) maintains the current (I L) flowing through the buck converter diode (D BUCK). In this way, an almost constant current through the LED can be maintained. By adjusting the duty cycle of the PWM signal (V PWM), the brightness of the LED (D LED) can be controlled. In addition, an LED capacitor (C LED) may be included to minimize current ripple between on/off states of the circuit. In addition, an input capacitor (C IN) may be included to minimize high frequency noise on the input voltage (V IN).
To maintain or adjust the level of the LED (e.g., light 101 from the LED), the system includes a current controller 200 (i.e., controller). The controller includes a load level measurement circuit (e.g., LED level measurement circuit 210) (i.e., load level calculator circuit) configured to determine a level (e.g., current level, light level) of the LED. The LED level measurement circuit 210 outputs the LED level (V LED) to the duty cycle generation circuit 250 (i.e., duty cycle generation). The duty cycle generation circuit 250 is configured to compare the LED level (V LED) with the reference level signal (V REF). Based on the difference resulting from the comparison, the duty cycle generation circuit 250 is configured to adjust the duty cycle of the PWM signal (V PWM) to minimize the difference. Dimming of the LED (D LED) may be achieved by adjusting the reference level signal (V REF). In addition, accurate dimming control depends, at least in part, on accurate measurement of the level of the LED (e.g., the current corresponding to the LED).
In some implementations, the measurement circuit 210 may be configured to determine the load based on the current sense signal and/or the PWM signal. In some embodiments, the load may be determined based on detection of the load current or voltage. In some implementations, the LED level measurement circuit 210 and the duty cycle generation circuit 250 may be collectively referred to as a duty cycle generator.
LED level measurement circuit 210 may directly or indirectly measure the current (I LED) of the LED to determine the level of the LED corresponding to the intensity of light 101. When making an indirect measurement of the LED level, the system 100 may include a current sense resistor (R CS) coupled to the source terminal of the transistor (Q BUCK) configured to generate a current sense voltage (V CS) corresponding to the current (I CS) through the transistor (Q BUCK). By monitoring the current sense voltage (V CS), the LED current in the on state (i.e., Q BUCK on) can be determined. When transistor 112 is in the on state, LED current (I LED) is equal to inductor current (I L), which increases with the charging of inductor (L BUCK). When transistor 112 is in the off state, the LED current decreases as the inductor (L BUCK) discharges. Depending on the duty cycle of the PWM signal, the LED current may reach zero if the inductor discharges before the PWM cycle repeats (i.e., before the next on condition).
During the on and off portions of the PWM cycle, the LED current changes as the inductor charges and discharges. To simplify duty cycle generation, a single representative value of LED level (i.e., V LED) may be obtained for each PWM cycle. For example, the LED level may correspond to an average LED current during a PWM cycle. Accordingly, the LED level measurement circuit 210 may be configured to determine a voltage (V CSH) that is half of the maximum voltage (V CS,LIM) sensed by the current sense resistor (R CS) during the on-cycle of the PWM signal.
The inductor on-time (T COND) is the time that the LED is on during the cycle time of the PWM signal (T S) (i.e., LED current I LED is greater than zero). The inductor on-time (i.e., on-period) may be calculated as the sum of the on-time (T ON) and the discharge time (T DIS), as shown below.
TCOND＝TON+TDIS (1)
The LED level may be calculated based on V CSH and T COND as follows.
VLED＝VCSH×(TCOND/TS) (2)
The LED level measurement circuit 210 may be configured to receive the current sense voltage from the current sense resistor R CS at each cycle. In addition, the LED measurement circuit 210 may be configured to receive the PWM signal and the drain voltage (V D) of the transistor 112 to determine the inductor on-time (T COND). Since determining the on-time requires determining the discharge time (T DIS) when transistor 112 is off (i.e., when I CS is zero), the drain voltage (V D) can be used to sense the LED current under off conditions. However, for some duty cycles of the PWM signal, it is not necessary to determine the on-time based on the sensed drain voltage (V D), as the on-time may be obtained based on knowledge of the PWM signal. In either case, the duty cycle generation circuit 250 may be configured to compare V LED with V REF and determine and control (i.e., adjust) the off-time (T OFF) of the PWM signal based on the comparison such that the duty cycle of the PWM signal is adjusted. For example, T OFF may be adjusted for the next PWM cycle to minimize the difference between V LED and V REF (measured at the next PWM cycle).
The buck converter 110 may have an operating mode that depends on the duty cycle of the PWM signal. The mode of operation is based on the inductor current (I L) during the PWM cycle. If the inductor current does not discharge to zero during the PWM cycle, the buck converter 110 operates in a continuous conduction mode (i.e., CCM). For example, a PWM signal with a high duty cycle (i.e., short T OFF) may correspond to CCM. If the inductor current discharges to zero during the PWM cycle, buck converter 110 operates in discontinuous conduction mode (i.e., DCM). For example, a PWM signal having a low duty cycle (i.e., a long T OFF) may correspond to DCM.
Fig. 2A and 2B show time-based graphs of signals associated with the system of fig. 1 for a continuous conduction mode (fig. 2A) and a discontinuous conduction mode (fig. 2B). As shown, the PWM signal (V PWM) is a binary (on/off) signal having an on time (T ON) and an off time (T OFF) and a cycle time (T S). The duty cycle of the PWM signal may be determined as T ON/TS x 100%. The duty cycle of the PWM signal in CCM (i.e., T OFF is shorter) is higher than the duty cycle of the DCM signal (i.e., T OFF is longer).
As also shown in fig. 2A and 2B, a current sense voltage (V CS) (i.e., a sensed current signal) corresponding to the transistor current level is shown. In the on state (i.e., during T ON), the sensed current signal corresponds to the inductor current I L (i.e., the LED current I LED). The LED current in CCM is higher than the LED current in DCM. Under off conditions (i.e., during T OFF), the current sense voltage (V CS) is ideally zero because the transistor is off (i.e., non-conductive).
As also shown in fig. 2A and 2B, a sensed drain signal (V D) corresponding to the drain terminal voltage level of the transistor (i.e., inductor L BUCK, voltage level) is shown. In the on state (i.e., during T ON), the drain voltage (V D) corresponds to the low voltage set by the (on) transistor 112 and the current sense resistor (R CS). Input voltage (V IN). The LED current in CCM is higher than the LED current in DCM. In the off state (i.e., during T OFF), the drain voltage is ideally V IN, as the inductor (L BUCK) charges and conducts current.
In CCM, the signal of the system maintains its ideal characteristics. However, in DCM, these signals exhibit non-ideal properties 113. Non-ideal characteristics 113 (e.g., resonant current) may be caused by parasitic capacitances that resonate with the inductor (L BUCK) to produce oscillations when the inductor discharges to zero. The parasitic capacitance may correspond to any component in the system, such as transistor 112 and buck diode (D BUCK).
Resonant oscillations in the current sense voltage (V CS) may cancel the current sense voltage (V CS) making the calculation of the half voltage (V CSH) inaccurate. For example, at the beginning of the PWM cycle, the current sense voltage (V CS) may have a negative value (i.e., negative resonant current offset, negative), causing the LED level measurement circuit to overestimate T ON, resulting in overestimating the LED level (V LED). Alternatively, at the beginning of the PWM cycle, the current sense voltage (V CS) may have a positive value (i.e., a positive resonant current offset, positive offset), causing the LED level measurement circuit to underestimate T ON, resulting in an underestimate of the LED level (V LED).
Fig. 3 shows the effect of resonant current offset on dimming of an LED. The graph includes a plot of LED current (I LED) versus dimming ratio. The dimming ratio is the ratio of light from the LED to the maximum light available from the LED. For example, a dimming ratio of 100% would be that the LED has maximum brightness, while a dimming ratio of 0% would be that the LED has no light. The dimming ratio in the system 100 may be reduced by reducing the duty cycle of the PWM signal. As the duty cycle decreases, the system transitions from CCM operation to DCM operation. For example, as shown in fig. 3, when the LED level is below about 23% of its maximum value, the system operates in DCM. Desirably, the dimming curve is linear such that an increase in LED current causes a corresponding (e.g., proportional) increase in dimming ratio. The linear dimming curve exists in CCM, but in DCM the relationship between LED current and dimming ratio is more complex and deviates from the linear relationship (i.e. shown in dashed lines in the DCM portion of the graph). Deviations of the dimming curve from linearity are called dimming distortions. Dimming distortion may be caused by at least inaccurate estimation of the LED level, which may be due to the resonant current offset of V CS, as previously described.
To reduce dimming distortion, an LED system with dimming control may be configured to detect and compensate for resonant current offset. Thus, the system 100 includes a resonant current offset compensation circuit 270 (i.e., resonant offset compensation). The resonance offset compensation circuit 270 is configured to determine a compensation period T COMP (i.e., compensation time, resonance current offset) that the LED level measurement circuit 210 can use to correct for inaccurate LED level measurements due to positive or negative resonance current offset. Specifically, the inductor on-time (T COND) may be calculated as the sum of the on-time (T ON) and the discharge time (T DIS) adjusted by the compensation time, such as shown below.
TCOND＝TON+TDIS+TCOMP (3)
The measurement of the load level includes a compensation period for correcting an offset between the PWM signal and the current sense signal (corresponding to the current through the transistor of the converter circuit) during the on portion of the PWM signal. This approach has the advantage of accommodating positive, negative, or no offset by the sign and magnitude of T COMP. The on-time (T ON) may be sensed as a period during the PWM cycle in which the current sense voltage (V CS) is positive. In CCM, T ON may correspond to (e.g., be equal to) the period in which the PWM signal is positive. However, in DCM, this may not be the case. V CS is the on portion of the PWM signal, which may be longer or shorter than the period during which V CS is positive. As discussed, this offset between the VCS and PWM on-cycles is due to the resonant effect (e.g., oscillation) experienced when the inductor current is fully discharged. Thus, this offset may be referred to as a resonant current offset. In some embodiments, the offset is a resonant current level (e.g., a level (i.e., amplitude) of oscillations (i.e., current ripple) caused by resonance on the sense current (I CS)) at the beginning of the on portion of the PWM signal in a Discontinuous Conduction Mode (DCM) of the converter circuit.
Thus, in some embodiments, the compensation period T COMP may be included or used for estimation: case 1. Load level; case 2. Compare signals from the reference level and the load level; case 3. Duty cycle. Thus, the duty cycle may be adjusted based on a comparison between the reference level and the load level and/or the compensation period.
Fig. 4A and 4B show time-based graphs of signals associated with the system of fig. 1. The current sense voltage (V CS) (i.e., transistor current level) is shown relative to the PWM signal (V PWM). In the on state (i.e., when the transistor is on), the current sense voltage (V CS) may be used as a sensed value of the LED current (I LED) when the inductor (L BUCK) is charged. As the inductor charges, the LED current steadily rises from zero. Thus, accurate measurement of the period in which the LED current is non-zero may include accurately determining the period in which V CS is positive. However, in DCM, the time 410 at which V CS starts to rise steadily from zero may not be aligned with the time 420 at the start time of the on-portion of the PWM cycle. If LED level measurement circuit 210 is configured to begin timing the rise of V CS at time 420 at the beginning of the on portion of the PWM cycle, the resulting time measurement may be inaccurate by compensating for the offset time (T COMP). Inaccuracy can result in measurements that are too long or too short, which can affect dimming control, as shown in fig. 3. The disclosed techniques may be used to increase the accuracy of load determinations (i.e., determined loads), such as LED level measurements.
As shown in fig. 4A, V CS is negative by negative offset 430 at time 420 when T ON begins. The rising current sense voltage (V CS) crosses zero at time 410 after time 420 at which T ON begins. The negative V CS value does not correspond to inductor conduction (T COND) (i.e., LED illumination), but rather an artifact from resonant (i.e., oscillating) current. Thus, the T COND measurement may need to be reduced by the negative T COMP 440 in order to accurately measure the LED level.
As shown in fig. 4B, v CS is positive by positive offset 450 at time 420 when T ON begins. The rising current sense voltage (V CS) crosses zero at time 410 before time 420 at which T ON begins. All positive VCS values correspond to inductor conduction (T COND) (i.e., LED illumination). Thus, the T COND measurement may need to be increased by the positive T COMP 460 in order to accurately measure the LED level.
The current controller 200 of the system 100 includes a resonance offset compensation circuit 270 configured to detect a period corresponding to T COMP based on the received PWM signal (V PWM) and the current sense voltage (V CS). Under some conditions (e.g., CCM), T COMP generated by circuit 270 may be zero, in which case no compensation is required. Under some conditions (e.g., DCM), T COMP generated by circuit 270 may have a sign based on whether the resonant current offset is positive or negative, as shown in fig. 4A and 4B.
One possible implementation of the resonance offset compensation circuit 270 is shown in fig. 5 (i.e., the orientation is arranged to match the orientation of fig. 1). The resonance offset compensation circuit 270 includes a current sense comparator 285 (i.e., a CS comparator). The current sense comparator 285 is configured to determine a first time and a second time at which the current sense voltage (V CS) reaches the first voltage and the second voltage, respectively. The trigger signal may be included in a communication signal (V COM) transmitted to the counter 280 along with the PWM signal (V PWM). The counter 280 may be configured to determine a first on period (T ON1) between the start of the on portion of the PWM signal and the first trigger signal and a second on period (T ON2) between the first trigger signal and the second trigger signal. Finally, the resonance offset compensation circuit 270 includes a subtractor circuit 275 (i.e., a subtractor) that can calculate T COMP as the difference between at least the first on period (T ON1) and the second on period (T ON2).
Fig. 6 includes a time-based plot of signals associated with an example embodiment of a resonance offset compensation circuit 270. To aid understanding, these graphs will be described in connection with the circuits shown in fig. 1 and 5. At zero time 610, determined by the PWM signal (V PWM), i.e., the start time of the on portion of the PWM cycle, the counter 280 is triggered to begin timing the first on period (T ON1). During the on period (T ON) of the PWM cycle, as the inductor (L BUCK) in the converter 110 charges, the current (I CS) through the transistor 112 increases. The current (I CS) generates a corresponding current sense voltage (V CS) in the current sense resistor (R CS). When the current sense voltage (V CS) matches or exceeds the first threshold voltage (V TH1), the first trigger signal 620 may configure the counter 280 to finish timing and output the first on period (T ON1). Additionally, the first trigger signal 620 may configure the counter 280 to begin timing the second on period (T ON2). The first threshold voltage (V TH1) may be set to a voltage (V CSH) that is half of the expected peak voltage (V CS.LIM) (i.e., peak current) of the on period (T ON). When the current sense voltage (V CS) matches or exceeds a second threshold voltage (e.g., V TH2＝VCS.LIM), the second trigger signal 630 may configure the counter 280 to finish timing and output a second on period (T ON2). Subtractor 275 may calculate the compensation period (T COMP) as the difference between the first on period and the second on period (e.g., T COMP＝TON2–TON1), in which case the compensation period may be negative due to the negative offset in the V CS signal.
For the embodiment shown in fig. 6, the on period of the PWM signal (V PWM) is T ON, but during the on portion of the PWM cycle the actual on time of the LED is T ON+TCOMP, which in this example is shorter due to negative offset (e.g., caused by parasitics under DCM). Also shown in fig. 6 is the LED current sensed to the drain voltage 640 (V D) during the off portion of the PWM signal (V PWM). In other words, during the off portion of the PWM signal, the LED current decreases to zero as the inductor (L BUCK) discharges. The period in which the LED is lit when the inductor (L BUCK) is discharged is a discharge period (T DIS) (i.e., a discharge time). The discharge period (T DIS) may be determined by the drain voltage (V D) of the transistor 112 instead of the conducted current (I CS) because the transistor 112 is configured to not conduct current during the off portion of the PWM signal. For example, T D may be a period defined by time 650 starting at the off portion of the PWM cycle and time 660 when the drain voltage V D crosses zero. In some implementations, T D can be a period defined by time 650 at which the off portion of the PWM cycle begins and time 660 at which V D begins to fall or the inductor current crosses zero. In other words, the discharge time is a period between a start time of the off portion of the PWM cycle and a time when the drain voltage decreases to zero. Accordingly, the LED level measurement circuit 210 may include a zero crossing detector circuit (ZCD) configured to determine when the drain voltage V D begins to fall or when the inductor current crosses zero.
The relationship between the first threshold voltage and the second threshold voltage is not limited to the above-described two-fold (k=2) relationship. Fig. 7 shows a first threshold voltage and a second threshold voltage relative to a current sense voltage (V CS). The second threshold voltage may be proportional to the first threshold voltage by a factor (K) (i.e., V TH2＝K×VTH1). In this case, the compensation period may be defined according to the factors shown below.
TCOMP＝(1/(K-1))·TON2-TON1 (4)
Fig. 8A shows a first possible implementation of CS comparator circuit 285, and fig. 8B shows possible signals associated with the circuit of fig. 8A. In this embodiment, two comparators are used to compare V CS to a first threshold voltage (V TH1) and a second threshold voltage (V TH2), respectively, and each generate a communication signal (V COM1,VCOM2) that can be used to trigger the counter to start and/or end counting. The trigger may be a rising edge in the communication signal. For example, a first comparator may generate a first communication signal (V COM1) providing a T ON1 count trigger signal, and a second comparator may generate a second communication signal (V COM2) providing a T ON2 count trigger signal.
Fig. 9A shows a second possible implementation of CS comparator circuit 285, and fig. 9B shows possible signals associated with the circuit of fig. 9A. In this embodiment, a comparator is used to compare V CS with either the first threshold voltage (V TH1) or the second threshold voltage (V TH2) depending on the state of the V COM signal. The comparator generates a communication signal (V COM) which can be used to trigger the counter to start and/or end counting. The trigger may be a pulse on the communication signal (V COM). The first pulse generates a T ON1 count trigger signal and configures the switch to change the threshold voltage from V TH1 to V TH2. The second pulse generates a T ON2 count trigger signal.
Fig. 10 shows a block diagram of a possible implementation of the LED level measurement circuit 210 of the system 100 of fig. 1. The LED level measurement circuit 210 includes a current sense sample and hold circuit 211 (i.e., CS S/H circuit) configured to determine V CS at a sampling time determined based on V PWM and T COMP. LED level measurement circuit 210 also includes a conduction time detection circuit 212 configured to determine a conduction time T COND based on V PWM、VD (e.g., when V D begins to fall or the inductor current crosses zero) and T COMP. The LED level measurement circuit 210 further includes an LED level calculator circuit 213 that generates an LED level (V LED) based on the on-time (T COND) and the sampled current detection voltage (V CS.SH). For example, the LED level may be calculated as V LED＝VCS.SH×TCOND.
Fig. 11 shows a block diagram of a possible implementation of the duty cycle generation circuit 250 of the system 100 of fig. 1. The circuit 250 includes a differential amplifier configured to generate a feedback signal (V FB) corresponding to the difference (i.e., error) between the LED level (V LED) and the reference signal (V REF). The reference signal may be received from another circuit coupled to the system. For example, the other circuit coupled to the system may be an interface circuit with controls to allow a user to adjust the reference voltage to set the adjustable level of the LED (i.e., dim the LED). The reference signal (V REF) may be a set point of the control loop that adjusts the duty cycle of the transistor for each PWM cycle such that the difference between the LED level (V LED) and the reference signal (V REF) is minimized. The circuit 250 also includes duty cycle control logic 251 configured to convert the feedback signal into a digital (i.e., bi-layer) signal that cycles between an on (e.g., high) level and an off (e.g., low) level during the PWM cycle according to the duty cycle. In other words, the adjustment of the reference level generates a corresponding adjustment of the current of the load.
Fig. 12 is a possible implementation of the system of fig. 1, showing additional details. In operation, the system 100 compares V CS to two reference signals (V CS.LIM1 and V CS.LIM2). The sampling time may be based on the two outputs of the comparator (i.e., T ON_1、TON_2) and the resonant current offset time (T COMP) is calculated as the difference. Next, a current sense voltage is determined. For example, the half-peak current sense voltage (i.e., V CSH) may be determined by sampling V CS at a sampling time adjusted (i.e., compensated) for T COMP. In addition, the inductor on-time (T COND) may be adjusted (i.e., compensated) by the resonant current offset. In some implementations, the inductor on-time (T COND) may be calculated based on the half-peak current sense voltage V CSH and the ratio of the inductor on-time (T COND) to the period of the PWM signal (T S), LED level measurement (i.e., LED calculation). In some implementations, the LED level (V LED) can then be compared to the reference level V REF (i.e., the reference signal) using an amplifier (e.g., a transconductance operational amplifier, OTA). The resulting signal may be used to adjust the duty cycle of the PWM signal (V PWM) through duty cycle control logic. The resulting PWM signal (V PWM) may be amplified using a gate driver and coupled to the gate of the transistor (Q BUCK).
Fig. 13 graphically depicts a method of driving an LED. The method 1300 includes detecting 1310 a PWM signal having an on portion and an off portion for controlling a switch of a DC-DC converter (e.g., a buck converter) to generate a (constant) current for an LED at a level dependent on a duty cycle of the PWM signal. At the beginning of the on portion of the PWM signal, a current sense signal (i.e., corresponding to the LED current) is detected 1315. As the inductor in the converter circuit charges, the current sense voltage (V CS) increases. In other words, the current sense signal corresponds to the charging current of the inductor. The increased V CS is compared to a first threshold to obtain 1330 a first on-time (T ON1) and to a second (e.g., higher) threshold to obtain 1335 a second on-time (T ON2). The compensation time calculation 1345 may be a difference between the first on-time and the second on-time (e.g., T ON2-TON1＝TCOMP). The method further includes sampling 1350 the (increased) current sense signal at a time determined (at least in part) by the compensation time to obtain a half-peak current sense voltage (V CSH).
In a different branch of the flow of the method, method 1300 includes detecting 1320 an on-time of the PWM signal (T ON). Further, at the beginning of the off portion of the PWM signal, a drain voltage (e.g., of a transistor in the converter) may be detected 1325. As the inductor in the converter circuit discharges, the drain voltage (V D) decreases. In other words, the drain voltage corresponds to the discharge current of the inductor. The reduced V D may be compared 1340 with a zero voltage (e.g., using a zero crossing detector, ZCD) to obtain a discharge time (T DIS). The method includes summing 1355 the compensation time, the on-time of the PWM signal, and the discharge time to obtain the on-time of the LED (T COND).
After calculating the half-peak current sense voltage (V CSH) and the on-time (T COND), the method 1300 includes determining 1360 the LED level (V LED) to be proportional to the on-time (T COND) times the half-peak current sense voltage (V CSH). The method further includes comparing 1365 the LED level (V LED) with a dimmable (i.e., adjustable) reference signal (V REF) to obtain a feedback signal (VFB) (i.e., an error signal) that is used to adjust 1370 the duty cycle of the PWM signal transmitted to the buck converter to drive the LED. The method may be repeated for each cycle of the PWM signal.
In the description and/or drawings, exemplary embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term "and/or" includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and are therefore not necessarily drawn to scale. Unless otherwise indicated, certain terms have been used in a generic and descriptive sense only and not for purposes of limitation. For example, while the present disclosure provides details regarding the application of LED dimming, where the LED receives current from the buck converter based on a compensated measurement of LED level, variations are possible. Thus, the disclosed method may be more generally considered advantageous for any controlled converter topology (e.g., buck, boost, buck-boost) by which a compensation period (T COMP) is generated to determine the duty cycle necessary to provide a constant current or voltage to the load.
Variations of the embodiments described herein are shown in fig. 14 and 15. Elements identical to those already described above will not be described in connection with this embodiment. In this embodiment, the LED level measurement circuit 210 and the duty cycle generation circuit 250 (which may be collectively referred to as a duty cycle generator) are replaced by a duty cycle generator 1451. The duty cycle generator is configured to generate a pulse width modulated signal (i.e., PWM signal (V PWM)) to a control (e.g., gate) terminal of the transistor (Q BUCK) to cycle the transistor on and off. In this embodiment, the PWM signal (V PWM) may have at least some (or all) of the features described above.
Details of the duty cycle generator 1451 associated with the embodiment of fig. 14 are shown in fig. 15. This embodiment may be referred to as a Power Factor Correction (PFC) boost converter embodiment. As shown in fig. 15, the duty cycle generator 1451 includes a ZCD detection circuit 1581, a T ON generator 1582, and a flip-flop 1583. The flip-flop may be a set-reset flip-flop having a set input S and a reset input R. The output Q may be a PWM signal (V PWM). The ZCD detection circuit 1510 may be configured to determine when, for example, V D begins to fall or when the inductor current crosses zero, and may send a signal V ZCD to set the flip-flop (via set input S). The T ON generator 1582 may be configured to send a signal T ON to the reset input R. In this embodiment, the on-time T ON is determined based on V FB and T COMP, and in this embodiment, the off-time is determined based on ZCD signal V ZCD. In some embodiments, signal T ON may be based on T ON＝K1*VFB–K2*TCOMP, where K1 and K2 are constants.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. The term "comprising" and variants thereof as used herein is synonymously used with the term "including" and variants thereof, and is an open-ended, non-limiting term. The term "optional" or "optionally" as used herein means that the subsequently described feature, event or circumstance may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where it does not. Ranges may be expressed herein as from "about" one particular value, and/or to "about" another particular value. When such a range is expressed, one aspect includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will also be understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
Some embodiments may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like.
While certain features of the described embodiments have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the detailed description. It is understood that these modifications and variations are presented by way of example only, and not limitation, and that various changes in form and details may be made. Any portion of the devices and/or methods described herein may be combined in any combination, except combinations that are mutually exclusive. The embodiments described herein can include various combinations and/or sub-combinations of the functions, components, and/or features of the different embodiments described.
Claims (8)
1. A controller for a power converter, comprising:
A duty cycle generation circuit configured to generate a pulse width modulated, PWM, signal based on a comparison of a load level and a reference level of a load coupled to the power converter, the PWM signal configuring the power converter to provide a current to the load coupled to the power converter, the current having a level corresponding to a duty cycle of the PWM signal;
A measurement circuit coupled to the duty cycle generation circuit and configured to output the load level to the duty cycle generation circuit, the load level being determined in accordance with a determination of a conduction period of an inductor of the power converter; and
A resonance offset compensation circuit configured to receive a current sense signal from the power converter and the PWM signal from the duty cycle generation circuit, and to determine a compensation period corresponding to an offset between the PWM signal and the current sense signal, the determination of the on period being prevented from being affected by resonance oscillations in discontinuous current mode DCM by the compensation period used by the measurement circuit, the resonance offset compensation circuit comprising:
a current sense comparator configured to generate a first trigger signal when the current sense signal is equal to a first threshold and to generate a second trigger signal when the current sense signal is equal to a second threshold;
A counter configured by the PWM signal to start timing at a start of a conductive portion of the PWM signal, and to output a first on-time when the first trigger signal is received and a second on-time when the second trigger signal is received; and
A subtractor configured to calculate the compensation period based on a difference between the first on-time and the second on-time.
2. The controller for a power converter of claim 1, wherein the controller is coupled to a source terminal of a transistor of the power converter such that the current sense signal corresponding to a charging current of the inductor of the power converter is coupled to the controller when the transistor is turned on by the PWM signal, and wherein the controller is coupled to a drain terminal of the transistor of the power converter such that a drain voltage corresponding to a discharging current of the inductor of the power converter is coupled to the controller when the transistor is turned off by the PWM signal.
3. The controller for a power converter of claim 2, wherein the measurement circuit comprises a conduction time detection circuit configured to determine the conduction period of the inductor as a period corresponding to the charging current and a period corresponding to the discharging current.
4. A controller for a power converter according to claim 3, wherein the measurement circuit is configured to increase or decrease the conduction period in accordance with the compensation period in order to increase the accuracy of the comparison of the load level of the load coupled to the power converter and the reference level.
5. The controller for a power converter of claim 2, wherein the measurement circuit comprises a current sense sample and hold circuit configured to sample the current sense signal at a time adjusted by the compensation period.
6. The controller for a power converter of claim 1, wherein the power converter is a boost converter or a buck converter.
7. The controller for a power converter of claim 1, wherein the duty cycle generation circuit comprises a comparator configured to compare the load level to the reference level.
8. The controller for a power converter of claim 7, wherein the adjustment to the reference level is generated in a corresponding adjustment to the current of the load, the accuracy of the corresponding adjustment resulting from using the compensation period to determine the load level.
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| US201962863189P | 2019-06-18 | 2019-06-18 | |
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| US16/787,343 | 2020-02-11 | ||
| US16/787,343 US10999905B2 (en) | 2019-06-18 | 2020-02-11 | Current control for power converter |
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