CN112104404B

CN112104404B - FPGA (field programmable Gate array) on-orbit debugging method for component flight verification

Info

Publication number: CN112104404B
Application number: CN202010710388.XA
Authority: CN
Inventors: 刘鸿瑾; 张绍林; 白星; 周游; 李天文; 王朋; 李宾; 王红霞; 焦聪; 苏博
Original assignee: Beijing Sunwise Space Technology Ltd
Current assignee: Beijing Sunwise Space Technology Ltd
Priority date: 2020-07-22
Filing date: 2020-07-22
Publication date: 2022-12-09
Anticipated expiration: 2040-07-22
Also published as: CN112104404A

Abstract

The invention discloses an on-orbit debugging method of an FPGA (field programmable gate array) for flight verification of components, which comprises the following steps: the method comprises the following steps that S1, a debugging client is connected with a ground station through a cable, the ground station initiates a transmission request to an antenna terminal of the in-orbit spacecraft through a satellite-ground communication link, and after communication is established, the ground terminal initiates an FPGA (field programmable gate array) downloading or debugging information transmission request; s2, after receiving the request information, the antenna terminal of the in-orbit spacecraft transmits the connection establishment information to the MCU through the Ethernet; s3: the MCU receives and analyzes an Ethernet data packet containing FPGA downloading or debugging information, and then sends the information to the FPGA through a user-defined JTAG link; s4: after receiving the information of the downloading or debugging information request ground station, the FPGA returns response information and handshake data to the MCU; s5: and after receiving the response information and the handshake data returned by the FPGA, the MCU transmits the information to the antenna terminal of the in-orbit spacecraft through the Ethernet.

Description

FPGA (field programmable Gate array) on-orbit debugging method for flight verification of components

Technical Field

The invention relates to a remote debugging method of an FPGA (field programmable gate array) for a component flight test, and provides an on-orbit debugging method based on satellite-ground link and MCU (microprogrammed control unit) remote control aiming at the on-orbit debugging requirements of the FPGA required by application of component flight verification and the like. Need not newly-increased independent JTAG hardware link connection, realize data and control signal's relay processing through MCU, solved and carried out the realizability problem of on-orbit FPGA debugging download and supervision under the unmanned on duty condition.

Background

An MCU (Micro Control Unit) Micro Control Unit, also called a Single Chip Microcomputer (Microcomputer) or a Single Chip Microcomputer (MCU), is to properly reduce the frequency and specification of a Central processing Unit (cpu), and integrate peripheral interfaces such as memory, counter (Timer), USB, a/D conversion, UART, PLC, DMA, etc., and even an LCD driving circuit on a Single Chip to form a Chip-level computer, which is used for different combined Control in different applications.

An FPGA (Field Programmable Gate Array) is a product of further development based on Programmable devices such as PAL and GAL. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), not only solves the defects of custom circuits, but also overcomes the defect that the gate circuit of the original programmable device is limited.

The circuit design completed by the hardware description language (Verilog HDL or VHDL) can be quickly burned to the FPGA for testing through simple synthesis and layout, which is the mainstream of the existing IC design verification technology.

Currently, a mode of "MCU + FPGA" is mostly adopted for designing a flight test platform for components, as shown in fig. 2, and is used for reconstructing a component program on line. The MCU can receive data through the Ethernet, and is convenient for the ground station to inject a new program on line.

However, this method has several problems as follows: at present, the components are reconstructed on line in an MCU + FPGA mode, only the function of remote program downloading can be realized, and remote debugging and testing cannot be carried out. Once the on-orbit FPGA fails, the error processing of the software layer can be realized only through upper computer software, the internal dynamic information of the on-orbit FPGA cannot be collected, and the design defect of the on-orbit FPGA cannot be accurately positioned and solved

Disclosure of Invention

The invention aims to: in order to solve the above problems, the present invention provides the following technical solutions, which support establishing an on-orbit remote downloading and debugging link through satellite-to-ground communication, debugging and monitoring an on-orbit FPGA through a ground terminal, and supporting downloading and debugging of a plurality of FPGA devices of one or more JTAG chains. According to the statistical method of the Starlink constellation, the average end-to-end round trip delay (roundtrip time. RTT) of the medium and low orbit satellite is 51.8ms, so that the link delay guarantee is provided for the remote debugging of the ground terminal through an FPGA EDA tool.

The technical scheme adopted by the invention is as follows:

an on-orbit debugging method of an FPGA (field programmable gate array) for flight verification of components comprises the following steps:

the method comprises the following steps that S1, a debugging client is connected with a ground station through a cable, the ground station initiates a transmission request to an antenna terminal of the in-orbit spacecraft through a satellite-ground communication link, and after communication is established, the ground terminal initiates an FPGA (field programmable gate array) downloading or debugging information transmission request;

s2, after receiving the request information, the on-orbit spacecraft antenna terminal transmits the connection establishment information to the MCU through the Ethernet;

s3: the MCU receives and analyzes an Ethernet data packet containing FPGA downloading or debugging information, and then sends the information to the FPGA through a user-defined JTAG link;

s4: after receiving the information of the downloading or debugging information request ground station, the FPGA returns response information and handshake data to the MCU;

s5: after receiving the response information and the handshake data returned by the FPGA, the MCU transmits the information to an in-orbit spacecraft antenna terminal through the Ethernet;

s6: and the in-orbit spacecraft antenna terminal receives the information and sends the information to the ground station debugging client, so that the link establishment and handshake operation between the ground terminal and the in-orbit tested FPGA are completed.

S7: and the ground terminal carries out on-orbit tested FPGA program downloading and remote debugging operation through the satellite-ground debugging link.

Further, the transmission information in step S1 includes bit streams and debugging information of the FPGA.

Further, in steps S3, S4, and S5, the MCU is a microprocessor designed for aerospace-level radioresistance reinforcement. The single particle carrying and total dose resisting capacity in a space environment is improved through the anti-radiation reinforcement design, and the reliability of on-orbit communication control is guaranteed.

Further, in steps S3, S4, and S5, the MCU is built in with a software/hardware functional module capable of analyzing remote debugging instructions and data received by the ethernet interface, converts ground debugging request data received by the antenna terminal of the in-orbit spacecraft into signals conforming to the standard JTAG timing sequence, transmits the signals to the in-orbit FPGA, converts FPGA feedback response data into ethernet packets, and transmits the ethernet packets to the ground terminal via the antenna terminal of the spacecraft.

Further, the custom JTAG in step S3 includes TCK, TMS, TDO, TDI, GND standard emulator signals, and the signals are 3.3V level standard further.

In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:

1. according to the FPGA on-orbit debugging method for the component-oriented flight test, the problem of cable connection of a JTAG simulator in an ultra-long distance and space environment can be solved through the satellite-ground communication link and the Ethernet, and remote control can be achieved.

2. According to the FPGA on-orbit debugging method for the component flight test, provided by the invention, the space navigation MCU for converting the Ethernet into the JTAG time sequence is supported, so that the on-orbit FPGA can be remotely debugged, the problems that the existing on-orbit FPGA cannot collect internal dynamic information and realize error positioning are solved, an effective way can be provided for helping a ground station to observe the operation state of the on-orbit FPGA on line, the detection means of the operation state of on-orbit equipment is widened, and the on-orbit service life of the space station operation equipment is prolonged.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and that for those skilled in the art, other relevant drawings can be obtained according to the drawings without inventive effort, wherein:

FIG. 1 is a block diagram of an FPGA on-orbit debugging method for component-oriented flight verification provided by the invention

FIG. 2 is a diagram illustrating an online reconfiguration mode of an existing on-track device;

fig. 3 is a block flow diagram of embodiment 1 of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The features and properties of the present invention are described in further detail below with reference to examples.

Example one

The debugging method comprises

S1: the debugging client is connected with a ground station through a cable, the ground station initiates a transmission request to an in-orbit spacecraft antenna terminal through a satellite-ground communication link, and the ground terminal initiates an FPGA (field programmable gate array) downloading or debugging information transmission request after communication is established;

s2: after receiving the request information, the antenna terminal of the in-orbit spacecraft transmits the connection establishment information to the MCU through the Ethernet;

s5: after receiving response information and handshake data returned by the FPGA, the MCU transmits the information to an on-orbit spacecraft antenna terminal through the Ethernet;

s6: and the in-orbit spacecraft antenna terminal receives the information and sends the information to the ground station debugging client terminal, so that the link establishment and handshake operation between the ground terminal and the in-orbit tested FPGA are completed.

The method can realize the remote downloading and remote debugging of the on-track FPGA and support the downloading and debugging of one or more JTAG chains and a plurality of FPGA devices. As shown in fig. 3, the specific operation is as follows:

1) The debugging client is connected with the ground station through a cable and initiates a request for opening a satellite-ground communication link to the ground station;

2) The ground station opens a satellite-ground communication link and initiates a transmission request to an on-orbit spacecraft antenna terminal;

3) Returning a response by the antenna terminal of the on-orbit spacecraft to establish connection;

4) The debugging client opens Xilinx Vivado software, clicks PROGRAM AND DEBUG, opens Open Hardware Manager, clicks Open Target, selects Auto Connect, at this time, there appears localhost, right key localhost, selects Add Xilinx Virtual Cable, fills in Target IP address Port number at Host name AND Port respectively, AND clicks OK.

5) The debugging client sends a TCP/IP request data packet to the in-orbit spacecraft antenna terminal through the ground station, and after receiving the request data packet, the in-orbit spacecraft antenna terminal forwards the data packet to the MCU through the Ethernet;

6) After receiving the request data packet, the MCU analyzes the data packet and responds to ACK (acknowledgement character) to the in-orbit spacecraft antenna terminal, the in-orbit spacecraft antenna terminal packs the ACK and sends the ACK to the ground station, and the ground station returns the ACK to the debugging client after receiving the ACK and establishes Ethernet remote connection;

7) The debugging client selects Xilinx _ tcf/Xilinx/(destination ip): destination port under localhost through Vivado software, finds out on-orbit FPGA equipment and right key Program Device, selects bit files and debugging files needing to be downloaded, and finally executes downloading;

8) The debugging client transmits the new bit stream file and the debugging file to the MCU through the ground station and the on-orbit spacecraft antenna terminal;

9) After receiving the file, the MCU forwards the file to the on-orbit FPGA to complete the remote downloading of the bit stream file and the updating of the debugging file;

10 The debugging client sets a Trigger condition in Trigger Setup-hw _ ila through Vivado software, triggers and starts triggering in Status-hw _ ila, and then the triggering request information is transmitted to an on-orbit FPGA through a complete link;

11 After the on-orbit FPGA completes triggering, corresponding triggering information is returned to the debugging client through a complete link;

12 The Vivado software of the debugging client analyzes the data packet to complete corresponding debugging actions,

example two

Preferably, in the steps S1, S2, S3, S4, S5, S6, and S7, the method can implement remote downloading and remote debugging of an on-track FPGA, and support downloading and debugging of a plurality of FPGA devices in one or more JTAG chains;

preferably, the connection established between the ground terminal and the on-orbit FPGA to be tested is a whole communication link comprising a ground test terminal, a ground communication terminal, an on-orbit spacecraft antenna terminal, an on-orbit control MCU and the on-orbit FPGA to be tested, and after investigation and testing, the link delay is within 100ms, so that the response time requirement of ground debugging software can be met,

preferably, the remote FPGA debugging method is not only suitable for satellite-ground remote debugging, but also suitable for in-orbit cabin debugging of a spacecraft (such as debugging of an off-cabin terminal FPGA in a space station) or ground equipment debugging and testing.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents and improvements made by those skilled in the art within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An FPGA on-orbit debugging method for flight verification of components is characterized by comprising the following steps:

s6: the in-orbit spacecraft antenna terminal receives the information and sends the information to the ground station debugging client, so that the link establishment and the handshake operation between the ground terminal and the in-orbit tested FPGA are completed;

s7: and the ground terminal carries out program downloading and remote debugging operation of the on-orbit tested FPGA through the satellite-ground debugging link.

2. The FPGA on-orbit debugging method for flight verification of components and parts according to claim 1, characterized in that: the transmission information in step S1 includes bit streams and debugging information of the FPGA.

3. The on-orbit debugging method of the FPGA for flight verification of the component as claimed in claim 1, characterized in that: in steps S3, S4 and S5, the MCU is a microprocessor designed for aerospace-level radiation-resistant reinforcement.

4. The FPGA on-orbit debugging method for flight verification of components and parts according to claim 1, characterized in that: in steps S3, S4, and S5, the MCU is built in with a software/hardware functional module capable of analyzing remote debugging instructions and data received by the ethernet interface, converts ground debugging request data received through the in-orbit spacecraft antenna terminal into signals conforming to the standard JTAG timing sequence, transmits the signals to the in-orbit FPGA, converts FPGA feedback response data into ethernet packets, and transmits the ethernet packets to the ground terminal through the spacecraft antenna terminal.

5. The FPGA on-orbit debugging method for flight verification of components and parts according to claim 1, characterized in that: the self-defined JTAG in the step S3 comprises TCK, TMS, TDO, TDI, GND standard simulator signals which are 3.3V level standards.