CN112103292B - Memory and manufacturing method thereof - Google Patents
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- CN112103292B CN112103292B CN202011244805.2A CN202011244805A CN112103292B CN 112103292 B CN112103292 B CN 112103292B CN 202011244805 A CN202011244805 A CN 202011244805A CN 112103292 B CN112103292 B CN 112103292B
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
The embodiment of the disclosure discloses a memory and a manufacturing method thereof, wherein the memory comprises: the channel layer, the tunneling layer, the gate layer and the storage layer are arranged in parallel in sequence; the gating layer is provided with an opening state and a closing state; wherein the gate layer in the on state is electrically conductive and the gate layer in the off state is electrically insulating; the tunneling layer and the gating layer allow charged particles to be transported between the channel layer and the storage layer when the gating layer is in the on state and a voltage applied across the tunneling layer is greater than a threshold voltage; when the gating layer is in the closed state, the tunneling layer and the gating layer block charged particles from being transmitted between the channel layer and the storage layer.
Description
Technical Field
The disclosed embodiments relate to the field of integrated circuits, and in particular, to a memory and a manufacturing method thereof.
Background
In a programming or erasing operation of a memory, it is often necessary to provide an input voltage to cause charged particles to pass through a tunneling layer between a memory layer and a channel layer.
In order to improve the data retention capability of the memory, the thickness of the tunneling layer is typically large. However, when a memory with a thicker tunneling layer is programmed or erased, the input voltage required to be supplied is also larger, which causes the degradation of the memory structure and reduces the reliability of the memory.
Disclosure of Invention
In view of the above, the present disclosure provides a memory and a method for fabricating the same.
According to a first aspect of embodiments of the present disclosure, there is provided a memory, including: the channel layer, the tunneling layer, the gate layer and the storage layer are arranged in parallel in sequence;
the gating layer is provided with an opening state and a closing state; wherein the gate layer in the on state is electrically conductive and the gate layer in the off state is electrically insulating;
the tunneling layer and the gating layer allow charged particles to be transported between the channel layer and the storage layer when the gating layer is in the on state and a voltage applied across the tunneling layer is greater than a threshold voltage;
when the gating layer is in the closed state, the tunneling layer and the gating layer block charged particles from being transmitted between the channel layer and the storage layer.
In some embodiments, the memory further comprises:
and the first dielectric layer is positioned between the gate layer and the storage layer and used for reducing the contact resistance between the gate layer and the storage layer.
In some embodiments, the constituent material of the first dielectric layer includes silicon oxide and/or silicon oxynitride.
In some embodiments, the memory further comprises:
a second dielectric layer and a gate control layer;
the second dielectric layer is positioned between the storage layer and the grid control layer and used for electrically isolating the storage layer from the grid control layer;
the gate control layer is used for controlling the gating layer to be switched between the on state and the off state.
In some embodiments, the memory comprises a two-dimensional floating gate type memory; the channel layer, the tunneling layer, the gating layer, the storage layer, the second dielectric layer and the gate control layer are sequentially stacked from bottom to top.
In some embodiments, the memory comprises a three-dimensional floating gate type memory or a three-dimensional charge trapping type memory, the three-dimensional floating gate type memory or the three-dimensional charge trapping type memory comprising:
a gate stack structure comprising: the third dielectric layers and the grid control layers are alternately stacked from bottom to top in sequence;
the channel layer, the tunneling layer, the gate layer, the storage layer and the second dielectric layer penetrate through the gate stack structure along the stacking direction of the third dielectric layer and the gate control layer;
the tunneling layer, the gate layer and the storage layer are sequentially stacked and wound on the outer side of the channel layer and are arranged between the channel layer and the second medium layer.
In some embodiments, the range of thicknesses of the tunneling layer includes: 5 to 30 angstroms;
the thickness range of the gating layer comprises: 30 angstroms to 200 angstroms.
According to a second aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a memory, including:
forming a channel layer, a tunneling layer, a gate layer and a storage layer which are sequentially arranged in parallel; wherein the gating layer has an on state and an off state; the gate layer in the on state is conductive and the gate layer in the off state is electrically insulating;
the tunneling layer and the gating layer allow charged particles to be transported between the channel layer and the storage layer when the gating layer is in the on state and a voltage applied across the tunneling layer is greater than a threshold voltage;
when the gating layer is in the closed state, the tunneling layer and the gating layer block charged particles from being transmitted between the channel layer and the storage layer.
In some embodiments, the method further comprises:
forming a first dielectric layer covering the gate layer; the first dielectric layer is located between the gate layer and the storage layer and used for reducing contact resistance between the gate layer and the storage layer.
In some embodiments, the constituent material of the first dielectric layer includes silicon oxide and/or silicon oxynitride.
In some embodiments, the method further comprises:
forming a conductive gate control layer; the gate control layer is used for controlling the gating layer to switch between the on state and the off state;
forming a second dielectric layer electrically isolating the storage layer and the gate control layer; and the second dielectric layer is positioned between the storage layer and the grid control layer.
In some embodiments, the memory includes a two-dimensional floating gate memory, and the forming of the channel layer, the tunneling layer, the gate layer, and the memory layer, which are sequentially arranged in parallel, includes:
forming a channel layer on the surface of the substrate; wherein the channel layer is parallel to the plane of the substrate;
the tunneling layer, the gate layer and the storage layer are sequentially formed on the surface of the channel layer from bottom to top in a parallel and stacked mode along the direction perpendicular to the plane of the substrate;
the forming a second dielectric layer electrically isolating the memory layer and the gate control layer includes: forming a second dielectric layer covering the storage layer;
the forming of the conductive gate control layer includes: and forming the grid control layer covering the second dielectric layer.
In some embodiments, the memory comprises a three-dimensional floating gate type memory, the method comprising:
the forming of the conductive gate control layer includes:
forming a first stacked structure on the surface of a substrate; the first stacked structure comprises a grid control layer and a third dielectric layer which are parallel to the substrate and are sequentially and alternately stacked from bottom to top;
the second dielectric layer electrically isolating the storage layer and the grid control layer is formed, and the channel layer, the tunneling layer, the gate layer and the storage layer are sequentially arranged in parallel, and the method comprises the following steps:
forming a first via through the first stacked structure; wherein the first through hole is vertical to the plane of the substrate;
etching the end part of the grid control layer exposed through the first through hole along the direction parallel to the substrate so as to form a groove at the end part of the grid control layer close to the first through hole;
forming a second dielectric layer covering the end part of the grid control layer in the groove;
after the second dielectric layer is formed, filling the groove to form the storage layer;
after the storage layer is formed, sequentially forming the gate layer, the tunneling layer and the channel layer in the first through hole;
the second dielectric layer, the storage layer, the gate layer, the tunneling layer and the channel layer are perpendicular to the plane of the substrate; the tunneling layer, the gate layer, the storage layer and the second dielectric layer are sequentially stacked and surround the outer side of the channel layer.
In some embodiments, the memory comprises a three-dimensional charge-trapping memory,
the forming of the conductive gate control layer includes:
forming a second stacked structure on the surface of the substrate; the second stacking structure comprises a sacrificial layer and a third dielectric layer which are parallel to the substrate and are sequentially and alternately stacked from bottom to top;
removing the sacrificial layer to form a gap between the adjacent third dielectric layers in the second stacked structure;
filling the gap to form the grid control layer;
the second dielectric layer electrically isolating the storage layer and the grid control layer is formed, and the channel layer, the tunneling layer, the gate layer and the storage layer are sequentially arranged in parallel, and the method comprises the following steps:
forming a second via through the second stack structure;
forming a second dielectric layer covering the side wall of the second through hole in the second through hole;
forming the storage layer, the gate layer, the tunneling layer and the channel layer in sequence in the second through hole formed with the second dielectric layer, wherein the storage layer, the gate layer, the tunneling layer and the channel layer cover the second dielectric layer;
the second dielectric layer, the storage layer, the gate layer, the tunneling layer and the channel layer are perpendicular to the plane of the substrate; the tunneling layer, the gate layer, the storage layer and the second dielectric layer are sequentially stacked and surround the outer side of the channel layer.
Compared with a memory with a thicker tunneling layer, the embodiment of the disclosure replaces the thicker tunneling layer in the related art with the gating layer with the on state and the off state, and when the voltage value applied to the thicker tunneling layer is the same as the voltage value applied to the thinner tunneling layer and the gating layer provided by the disclosure, the gating layer in the on state is conductive, so that the electric field intensity applied to the tunneling layer can be increased in the memory provided by the disclosure, the probability that charged particles pass through the tunneling layer is increased, that is, the probability that the charged particles are transmitted between the channel layer and the memory layer is increased.
Therefore, the memory provided by the embodiment of the disclosure can reduce the programming voltage and the erasing voltage, thereby reducing the memory structure degradation phenomenon caused by the larger required programming voltage and erasing voltage, and being beneficial to improving the reliability of the memory.
In addition, when the gating layer provided by the embodiment of the disclosure is in a closed state, the barrier height between the channel layer and the storage layer can be ensured by the thin tunneling layer and the electrically insulated gating layer, which is similar to the barrier height generated by the thick tunneling layer in the related art, thereby being beneficial to ensuring that the data retention capability of the memory is better and the leakage current of the memory is smaller.
Drawings
Fig. 1a to 1e are schematic diagrams illustrating band structures of a floating gate structure memory according to an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating a partial structure of a memory in accordance with an exemplary embodiment;
FIG. 3 is a partial block diagram illustrating another memory in accordance with an exemplary embodiment;
FIG. 4 is a schematic diagram illustrating a partial structure of yet another memory in accordance with an illustrative embodiment;
FIGS. 5 a-5 e are schematic diagrams illustrating a band structure according to an exemplary embodiment;
FIG. 6 is a schematic diagram illustrating a partial structure of yet another memory device in accordance with an exemplary embodiment
FIGS. 7 a-7 e are schematic diagrams illustrating another band structure according to an exemplary embodiment;
FIG. 8 illustrates a floating gate memory band structure diagram in accordance with an exemplary embodiment;
FIG. 9 illustrates a charge trapping memory band structure diagram in accordance with an exemplary embodiment.
Detailed Description
The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.
It is to be understood that the meaning of "on … …," "over … …," and "over … …" in this disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.
In the disclosed embodiment, the term "a is connected to B" includes A, B where a is connected to B in contact with each other, or A, B where a is connected to B in a non-contact manner with other components interposed between the two.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.
The technical means described in the embodiments of the present invention may be arbitrarily combined without conflict.
Fig. 1a to 1e are schematic diagrams illustrating band structures of a floating gate (floating gate) structure memory according to an exemplary embodiment. In fig. 1a to 1e, the constituent materials of the silicon channel, the silicon floating gate and the silicon control gate may be the same conductive material, such as polysilicon (polysilicon) or the like.
FIG. 1a shows the flat band state of a floating gate structure memory. Referring to fig. 1b, a positive voltage is applied to the insulating dielectric layer through the silicon control gate. The applied positive voltage generates an electric field with electric field lines in a first direction between the silicon channel and the silicon control gate. Negatively charged electrons in the silicon channel are subjected to an electric field and the tunnel oxide layer between the silicon channel and the silicon floating gate is band bent. When the energy obtained by the electrons under the action of the electric field is large enough, the electrons in the silicon channel will pass through the tunneling oxide layer and move into the silicon floating gate to perform a programming operation.
FIG. 1c shows the band structure of a floating gate structure memory at the completion of a programming operation. Negatively charged electrons moving from the silicon channel through the tunnel oxide into the silicon floating gate are used to indicate the stored data.
Referring to fig. 1d, a negative voltage is applied to the insulating dielectric layer through the silicon control gate. The applied negative voltage generates an electric field with electric field lines in a second direction between the silicon channel and the silicon control gate. Negatively charged electrons stored in the silicon floating gate are subjected to an electric field and the energy band of the tunnel oxide layer located between the silicon channel and the silicon floating gate bends. When the energy obtained by the electrons under the action of the electric field is large enough, the electrons in the silicon floating gate pass through the tunneling oxide layer and move into the silicon channel to perform an erasing (erase) operation. It will be appreciated that the second direction is parallel and opposite to the first direction described above. FIG. 1e shows the band structure of a floating gate structure memory at the completion of an erase operation.
A programming operation for the flash memory is performed in order to enable charged electrons to pass from the silicon channel through the tunnel oxide into the silicon floating gate, or an erase operation for the flash memory is performed in order to enable charged electrons to pass from the silicon floating gate through the tunnel oxide into the silicon channel.
Generally, the thicker the tunnel oxide layer is, the wider the barrier of the tunnel oxide layer is, the more difficult it is for electrons to pass through the tunnel oxide layer, and the better the data retention capability of the memory. However, when the thicker the tunnel oxide layer, the more energy is required for electrons to pass through the tunnel oxide layer when programming or erasing the memory. That is, the thicker the tunnel oxide layer is, the larger the voltage to be supplied to the memory needs to be, when the memory is programmed or erased.
When the value of the voltage supplied to the memory is increased, the stronger the electric field intensity formed in the tunneling oxide layer under the action of the voltage, the greater the damage to the tunneling oxide layer caused by the charged particles in the process of passing through the tunneling oxide layer, the greater the number of defects generated in the tunneling oxide layer is increased, the degradation of the memory structure is caused, and the reliability of the memory is reduced.
Fig. 2 is a schematic diagram illustrating a memory 100 in accordance with an exemplary embodiment. Referring to fig. 2, the memory 100 includes: the channel layer 110, the tunneling layer 120, the gate layer 130 and the storage layer 140 are sequentially arranged in parallel;
a gating layer 130 having an on state and an off state; wherein the gate layer 130 in the on state is conductive, and the gate layer 130 in the off state is electrically insulated;
the tunneling layer 120 and the gating layer 130 allow charged particles to be transferred between the channel layer 110 and the storage layer 140 when the gating layer 130 is in an on state and a voltage applied across the tunneling layer 120 is greater than a threshold voltage;
when the gate layer 130 is in the off state, the tunneling layer 120 and the gate layer 130 block charged particles from being transferred between the channel layer 110 and the storage layer 140.
The constituent material of the channel layer 110 includes: including silicon, such as amorphous, polycrystalline, or monocrystalline silicon, among others.
The tunneling layer 120 is composed of the following materials: silicon oxide and/or silicon oxynitride.
The threshold voltage of the tunneling layer 120 is related to the material and thickness of the tunneling layer 120. It is noted that when the tunneling layer 130 is in the on state and the voltage applied to the tunneling layer 120 is greater than the threshold voltage, the band bending degree of the tunneling layer 120 is large enough, and the charged particles in the channel layer 110 or the storage layer 140 obtain enough energy to pass through the tunneling layer 120.
The charged particles may include: negatively charged electrons, or positively charged holes, etc.
The gating layer 130 may include: bidirectional threshold switching (OTS), e.g. ZnaTeb、GeaTeb、NbaObOr SiaAsbTecAnd the like. Here, a, b and c may be natural numbers greater than 1.
Illustratively, the gating layer 130 may be controlled to switch between an on state and an off state using an electrical signal. The electrical signal may comprise a voltage.
For example, when no voltage signal is applied to the gate layer 130, the gate layer 130 is in an off state. The gate layer 130 in the off state has a high resistance, and it can be considered that the gate layer 130 is in a high resistance state, and the gate layer 130 in the high resistance state is electrically insulated.
A voltage is applied to the gate layer 130 in the off state, and when the voltage applied to the gate layer 130 in the off state increases to be greater than or equal to a preset threshold voltage of the gate layer 130, the gate layer 130 is switched from the off state to the on state. The gate layer 130 in the on state has a low resistance, and the gate layer 130 in the low resistance state can be considered to be in the low resistance state, and the gate layer 130 in the low resistance state is conductive.
When the voltage applied to the gate layer 130 in the on state is gradually decreased to be less than or equal to the preset threshold voltage, the gate layer 130 is switched from the on state to the off state. It can be appreciated that when the gate layer 130 is switched from the on state to the off state, the gate layer 130 is switched from the low resistance state to the high resistance state.
The constituent material of the storage layer 140 may include at least one of: silicon nitride; silicon oxynitride; silicon.
Illustratively, the range of thicknesses of the tunneling layer 120 includes: 5A to 30A; the thickness range of the gate layer 130 includes: 30 angstroms to 200 angstroms.
Compared with a memory with a thicker tunneling layer, the embodiment of the disclosure replaces the thicker tunneling layer in the related art with the thinner tunneling layer 120 and the gating layer 130 with the on state and the off state, and when the voltage value applied to the thicker tunneling layer is the same as the voltage value applied to the thinner tunneling layer 120 and the gating layer 130 provided by the disclosure, since the gating layer 130 in the on state is conductive and the thickness of the tunneling layer 120 in the disclosure is smaller than that of the thicker tunneling layer in the related art, the memory 100 provided by the disclosure can increase the electric field intensity applied to the tunneling layer 120, so that the probability of the charged particles passing through the tunneling layer 120 is increased, that is, the probability of the charged particles transmitting between the channel layer 110 and the memory layer 140 is increased.
Therefore, the memory 100 provided by the embodiment of the disclosure can reduce the programming voltage and the erasing voltage, thereby reducing the structural degradation phenomenon of the memory 100 caused by the larger required programming voltage and erasing voltage, and being beneficial to improving the reliability of the memory 100.
Moreover, when the gate layer 130 provided in the embodiment of the present disclosure is in the off state, the barrier height between the channel layer 110 and the storage layer 140 can be ensured by the thin tunneling layer 120 and the electrically insulating gate layer 130, which is similar to the barrier height generated by a thicker tunneling layer in the related art, which is beneficial to ensuring that the data retention capability of the memory 100 is better and the leakage current of the memory 100 is smaller.
In some embodiments, as shown with reference to FIG. 3, memory 100 further comprises:
and a first dielectric layer 150 between the gate layer 130 and the memory layer 140 for reducing contact resistance between the gate layer 130 and the memory layer 140.
Illustratively, the constituent material of the first dielectric layer 150 includes silicon oxide and/or silicon oxynitride.
When the gate layer 130 and the memory layer 140 are in direct contact, the contact resistance between the gate layer 130 and the memory layer 140 is large, which is not favorable for promoting the movement of charged particles between the gate layer 130 and the memory layer 140 in the on state.
In the embodiment of the disclosure, by the first dielectric layer 150 disposed between the gate layer 130 and the memory layer 140, compared with the direct contact between the gate layer 130 and the memory layer 140, the contact resistance between the gate layer 130 and the memory layer 140 can be reduced, the interface contact between the gate layer 130 and the memory layer 140 is optimized, the movement of charged particles between the gate layer 130 and the memory layer 140 in the on state is promoted, and the programming voltage and the erasing voltage of the memory 100 are reduced.
In some embodiments, memory 100 further comprises: a second dielectric layer 160 and a gate control layer 170;
a second dielectric layer 160 between the memory layer 140 and the gate control layer 170 for electrically isolating the memory layer 140 from the gate control layer 170;
and a gate control layer 170 for controlling the gate layer 130 to switch between an on state and an off state.
The composition material of the second dielectric layer 160 may include at least one of: silicon oxide; silicon oxynitride; high dielectric constant (k) dielectrics. The high dielectric constant dielectric may comprise aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Or tantalum oxide (Ta)2O5) And the like. Here, the high dielectric constant dielectric includes: a dielectric having a dielectric constant greater than 2.8.
It is noted that the second dielectric layer 160 may include a single-layer structure or a multi-layer structure. For example, the second dielectric layer 160 may include a multi-layer structure formed of a first layer of silicon oxide, silicon nitride, and a second layer of silicon oxide.
The constituent materials of gate control layer 170 include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), conductive silicide, or any combination thereof.
Illustratively, the gate control layer 170 may be electrically connected to an external power source through a conductive interconnect structure. An external power source may perform programming, erasing, or reading operations, etc. on the memory device 100 by inputting an electrical signal to the selected gate control layer 170 to form an electric field in the tunneling layer 120 and the gating layer 130.
In some embodiments, memory 100 further comprises: the device comprises a substrate for bearing a channel layer 110, a tunneling layer 120, a gating layer 130 and a storage layer 140 which are sequentially arranged in parallel.
The substrate may comprise a semiconductor wafer. In some embodiments, the substrate may include a single semiconductor element such as silicon (Si) or germanium (Ge). In other embodiments, the substrate may comprise materials such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In still other embodiments, the substrate may comprise a silicon-on-insulator (SOI) structure or a silicon-germanium-on-insulator (SGOI) structure. It is noted that the substrate may also comprise circuit areas in which, for example, transistor structures are formed.
In some embodiments, referring to FIG. 4, memory 100 comprises a two-dimensional floating gate type memory; the channel layer 110, the tunneling layer 120, the gate layer 130, the storage layer 140, the second dielectric layer 160, and the gate control layer 170 are sequentially stacked from bottom to top.
Illustratively, the two-dimensional floating gate type memory further includes: a substrate. The substrate includes: a source region 181 and a drain region 182. The channel layer 110 may be formed between the source region and the drain region. The tunneling layer 120, the gate layer 130, the storage layer 140, the second dielectric layer 160, and the gate control layer 170 are sequentially stacked on the substrate from bottom to top in a direction perpendicular to a plane of the substrate.
In some embodiments, memory 100 comprises a three-dimensional floating gate or three-dimensional charge trapping memory comprising:
a gate stack structure comprising: the grid control layer 170 and the third dielectric layer 180 are alternately stacked from bottom to top in sequence along the direction vertical to the plane of the substrate;
the channel layer 110, the tunneling layer 120, the gate layer 130, the storage layer 140 and the second dielectric layer 160 penetrate through the gate stack structure along the stacking direction of the third dielectric layer 180 and the gate control layer 170;
the tunneling layer 120, the gate layer 130, and the storage layer 140 are sequentially stacked around the outside of the channel layer 110 and disposed between the channel layer 110 and the second dielectric layer 160.
Fig. 2 shows a schematic diagram of a three-dimensional floating gate type memory. Fig. 5a to 5e are schematic diagrams showing energy band structures of the three-dimensional floating gate type memory shown in fig. 2. The three-dimensional Floating Gate type memory may include a three-dimensional Floating Gate type Flash memory (Floating Gate Flash).
It is noted that the tunneling layer 120 and the gate layer 130 in the off state form a barrier between the channel layer 110 and the storage layer 140 to block the movement of charged particles, and the second dielectric layer 160 blocks the transfer of charged particles between the storage layer 140 and the gate control layer 170.
Fig. 5a shows a band diagram of the flat band state of a three-dimensional floating gate type memory. Referring to fig. 5a, the channel layer 110 has negatively charged electrons, and the memory layer 140 does not store electrons, that is, data is not stored in the memory 100. Note that the gating layer 130 is in the off state in fig. 5 a.
Referring to fig. 5b, a positive voltage greater than the preset threshold voltage of pass layer 130 is applied to gate control layer 170. The applied positive voltage generates a first electric field with electric field lines in a first direction between channel layer 110 and gate control layer 170. Here, the first direction is a direction pointing to the channel layer 110 along the gate control layer 170. Under the action of the first electric field, the energy band of the tunneling layer 120 is bent, the gate layer 130 is switched from the off state to the on state, and the negatively charged electrons in the channel layer 110 obtain energy to sequentially pass through the tunneling layer 120 and the gate layer 130 and be transmitted to the storage layer 140, so that the programming operation of the memory 100 is realized.
Since the gate layer 130 in the off state is electrically insulated and the gate layer 130 in the on state is electrically conductive, as shown in fig. 5a and 5b, after the gate layer 130 is switched from the off state to the on state, the width of the potential barrier between the channel layer 110 and the storage layer 140 caused by the gate layer 130 in the off state is reduced or the potential barrier disappears, thereby improving the probability of electron transfer from the channel layer 110 to the storage layer 140. Moreover, since the gate layer 130 is switched from the off state to the on state, the electric field intensity of the first electric field acting on the tunneling layer 120 is improved, and the probability of the charged particles passing through the tunneling layer 120 is further improved. Namely, the three-dimensional floating gate type memory provided by the present disclosure can reduce a programming voltage.
It should be noted that different filling marks are used in the drawings of the embodiments of the present disclosure to distinguish the gate layer 130 in the on state from the gate layer 130 in the off state.
Fig. 5c shows the band structure of the three-dimensional floating gate type memory at the completion of the programming operation. Electrons from the channel layer 110, through the tunneling layer 120 and the gating layer 130, and into the storage layer 140 are used to indicate data stored in the memory.
Note that when the program operation is completed, the application of the positive voltage to gate control layer 170 is stopped, so that pass layer 130 is switched from the on state to the off state. Since the gate layer 130 in the off state has a high forbidden bandwidth, the tunneling layer 120 and the electrically insulating gate layer 130 can prevent charged particles from being transferred between the storage layer 140 and the channel layer 110, thereby reducing a leakage current of the three-dimensional floating gate memory.
Referring to fig. 5d, a negative voltage is applied to gate control layer 170. The applied negative voltage generates a second electric field with electric field lines in a second direction between channel layer 110 and gate control layer 170. Here, the second direction is opposite to the first direction. Under the action of the second electric field, the energy band of the tunneling layer 120 is bent, the gate layer 130 is switched from the off state to the on state, and the negatively charged electrons in the storage layer 140 acquire energy to pass through the gate layer 130 and the tunneling layer 120 and be transmitted to the channel, so that the erasing operation of the memory 100 is realized.
Similar to the programming operation, the embodiment of the disclosure is advantageous to increase the probability of the electrons being transmitted from the storage layer 140 to the channel layer 110 and increase the electric field intensity of the second electric field acting on the tunneling layer 120 by providing the pass layer 130, thereby increasing the probability of the charged particles passing through the tunneling layer 120. Namely, the three-dimensional floating gate type memory provided by the present disclosure can reduce the erase voltage.
Fig. 5e shows a schematic diagram of the band structure of the three-dimensional floating gate type memory when the erase operation is completed. It should be noted that, when the erase operation is completed, the application of the negative voltage to the gate control layer 170 is stopped, so that the gate layer 130 is switched from the on state to the off state, and the gate layer 130 in the off state has a higher forbidden bandwidth, so that the tunneling layer 120 and the electrically insulated gate layer 130 can prevent the charged particles from being transmitted between the storage layer 140 and the channel layer 110, thereby reducing the leakage current of the three-dimensional floating gate memory.
The three-dimensional Charge Trap memory includes a three-dimensional Charge Trap Flash memory (Charge Trap Flash), including but not limited to a three-dimensional NAND Flash memory. Taking a three-dimensional NAND memory as an example, the three-dimensional NAND memory may include a plurality of memory strings penetrating a gate stack structure, and each memory string may have a cylindrical shape.
Referring to FIG. 6, the storage string may include: the channel layer 110, the tunneling layer 120, the gate layer 130, the storage layer 140, and the second dielectric layer 160 are sequentially arranged from the center of the cylinder toward the outer surface of the cylinder along the radial direction of the cylinder.
Fig. 7a to 7e are schematic diagrams illustrating band structures of the three-dimensional charge trap memory shown in fig. 6. It is noted that the tunneling layer 120 and the gate layer 130 in the off state form a barrier between the channel layer 110 and the storage layer 140 to block the movement of charged particles, and the second dielectric layer 160 blocks the transfer of charged particles between the storage layer 140 and the gate control layer 170.
Fig. 7a shows a band diagram of the flat band state of a three-dimensional charge trapping memory. Referring to fig. 7a, the channel layer 110 has negatively charged electrons, and the memory layer 140 does not store electrons, that is, data is not stored in the memory 100. Note that the gating layer 130 is in the off state in fig. 7 a.
Referring to fig. 7b, a positive voltage greater than the preset threshold voltage of pass layer 130 is applied to gate control layer 170. The applied positive voltage generates a first electric field with electric field lines in a first direction between channel layer 110 and gate control layer 170. Here, the first direction is a direction pointing to the channel layer 110 along the gate control layer 170. Under the action of the first electric field, the energy band of the tunneling layer 120 is bent, the gate layer 130 is switched from the off state to the on state, and the negatively charged electrons in the channel layer 110 obtain energy to sequentially pass through the tunneling layer 120 and the gate layer 130 and be transmitted to the storage layer 140, so that the programming operation of the memory 100 is realized.
Since the gate layer 130 in the off state is electrically insulated and the gate layer 130 in the on state is electrically conductive, as shown in fig. 7a and 7b, after the gate layer 130 is switched from the off state to the on state, the width of the potential barrier between the channel layer 110 and the storage layer 140 caused by the gate layer 130 in the off state is reduced or the potential barrier disappears, thereby improving the probability of electron transfer from the channel layer 110 to the storage layer 140. Moreover, since the gate layer 130 is switched from the off state to the on state, the electric field intensity of the first electric field acting on the tunneling layer 120 is improved, and the probability of the charged particles passing through the tunneling layer 120 is further improved. Namely, the three-dimensional charge trap type memory provided by the present disclosure can reduce the programming voltage.
It should be noted that the embodiments of the present disclosure employ different filling marks to distinguish the gating layer 130 in the on state and the off state.
Fig. 7c shows the band structure of the three-dimensional charge trapping memory at the completion of the programming operation. Electrons from the channel layer 110, through the tunneling layer 120 and the gating layer 130, and into the storage layer 140 are used to indicate data stored in the memory 100.
Note that when the program operation is completed, the application of the positive voltage to gate control layer 170 is stopped, so that pass layer 130 is switched from the on state to the off state. Since the gate layer 130 in the off state has a high forbidden bandwidth, the tunneling layer 120 and the electrically insulating gate layer 130 can prevent charged particles from being transferred between the memory layer 140 and the channel layer 110, thereby reducing a leakage current of the three-dimensional charge trapping memory.
Referring to fig. 7d, a negative voltage is applied to gate control layer 170. The applied negative voltage generates a second electric field with electric field lines in a second direction between channel layer 110 and gate control layer 170. Here, the second direction is opposite to the first direction, and "h" is used to indicate a hole. Under the second electric field, the energy band of the tunneling layer 120 is bent, the gate layer 130 is switched from the off state to the on state, and the positively charged holes in the channel layer 110 obtain energy to pass through the gate layer 130 and the tunneling layer 120 and to be transmitted into the channel.
It is noted that the holes transferred into the memory layer 140 during the erase operation are recombined with the electrons transferred into the memory layer 140 during the program operation, thereby implementing the erase operation of the memory 100.
Similar to the programming operation, the embodiment of the disclosure is advantageous to increase the probability of hole transmission from the channel layer 110 to the storage layer 140 and increase the electric field intensity of the second electric field acting on the tunneling layer 120 by providing the pass layer 130, thereby increasing the probability of the charged particles passing through the tunneling layer 120. Namely, the three-dimensional charge trap type memory provided by the present disclosure can reduce the erase voltage.
Fig. 7e shows a schematic diagram of the band structure of the three-dimensional charge trapping memory when the erase operation is completed. It should be noted that, when the erase operation is completed, the application of the negative voltage to the gate control layer 170 is stopped, so that the gate layer 130 is switched from the on state to the off state, and the gate layer 130 in the off state has a higher forbidden bandwidth, so that the tunneling layer 120 and the electrically insulated gate layer 130 can prevent the charged particles from being transferred between the storage layer 140 and the channel layer 110, thereby reducing the leakage current of the three-dimensional charge trapping memory.
Fig. 8 is a schematic diagram illustrating a band structure of another floating gate memory according to an example embodiment. Fig. 9 is a schematic diagram illustrating a band structure of another charge trapping memory device according to an example embodiment.
When the memory device 100 includes the first dielectric layer 150, the first dielectric layer 150 may form a barrier between the gate layer 130 and the memory layer 140. When the voltage applied to the gate control layer 170 is sufficiently large, the barrier width of the tunneling layer 120 and the barrier width of the first dielectric layer 150 are reduced, and the gate layer 130 is switched from the off state to the on state, such that the tunneling layer 120, the gate layer 130, and the first dielectric layer 150 may allow charged particles to be transferred between the channel layer 110 and the storage layer 140.
Illustratively, the tunneling layer 120, the gate layer 130, and the first dielectric layer 150 may allow charged particles to be transferred between the channel layer 110 and the storage layer 140 when a voltage applied to the gate control layer 170 is greater than a sum of a threshold voltage of the tunneling layer 120, a preset threshold voltage of the gate layer 130, and a threshold voltage of the first dielectric layer 150.
The embodiment of the present disclosure provides a method for manufacturing a memory, which can be used to manufacture the memory 100 provided by the embodiment of the present disclosure, and the method includes the following steps:
forming a channel layer, a tunneling layer, a gate layer and a storage layer which are sequentially arranged in parallel;
the gating layer has an opening state and a closing state; the gating layer in the on state is conductive, and the gating layer in the off state is electrically insulated; when the gating layer is in an open state and a voltage applied to the tunneling layer is greater than a threshold voltage, the tunneling layer and the gating layer allow charged particles to be transferred between the channel layer and the storage layer; the tunneling layer and the gating layer block charged particles from being transported between the channel layer and the memory layer when the gating layer is in an off state.
Compared with a memory with a thicker tunneling layer formed between a storage layer and a channel layer, the embodiment of the disclosure replaces the thicker tunneling layer in the related art by the thinner tunneling layer and the gating layer with an open state and a closed state, and when a voltage value applied to the thicker tunneling layer is the same as the voltage value applied to the thinner tunneling layer and the gating layer provided by the disclosure, the gating layer in the open state is conductive, so that the memory provided by the disclosure can increase the electric field intensity applied to the tunneling layer, the probability that charged particles pass through the tunneling layer is increased, and the probability that the charged particles are transmitted between the channel layer and the storage layer is increased.
Therefore, the memory manufactured by the method provided by the embodiment of the disclosure can reduce the programming voltage and the erasing voltage, further reduce the memory structure degradation phenomenon caused by larger required programming voltage and erasing voltage, and is beneficial to improving the reliability of the memory.
In addition, when the gating layer is in a closed state, the barrier height between the channel layer and the storage layer can be ensured by the thin tunneling layer and the electrically insulated gating layer, which is similar to the barrier height generated by the thick tunneling layer in the related technology, so that the data retention capability of the memory is better ensured, and the leakage current of the memory is smaller.
In some embodiments, the method further comprises:
forming a first dielectric layer covering the gate layer; the first dielectric layer is located between the gate layer and the storage layer and used for reducing contact resistance between the gate layer and the storage layer.
Illustratively, the composition material of the first dielectric layer comprises silicon oxide and/or silicon oxynitride.
According to the embodiment of the disclosure, the first dielectric layer is formed between the gate layer and the storage layer, compared with the direct contact between the gate layer and the storage layer, the contact resistance between the gate layer and the storage layer can be reduced, the interface contact between the gate layer and the storage layer is optimized, the movement of charged particles between the gate layer and the storage layer in an open state is promoted, and the programming voltage and the erasing voltage of the memory are reduced.
In some embodiments, the method further comprises:
forming a conductive gate control layer; the gate control layer is used for controlling the gating layer to be switched between an opening state and a closing state;
forming a second dielectric layer electrically isolating the storage layer and the grid control layer; and the second dielectric layer is positioned between the storage layer and the grid control layer.
In some embodiments, the memory comprises a two-dimensional floating gate type memory, and the method of fabricating comprises:
forming a channel layer on the surface of the substrate; wherein, the channel layer is parallel to the plane of the substrate;
sequentially forming a tunneling layer, a gate layer and a storage layer which are arranged in parallel in a stacked mode from bottom to top on the surface of the channel layer along the direction perpendicular to the plane of the substrate;
the second dielectric layer for forming the electrical isolation storage layer and the grid control layer comprises: forming a second dielectric layer covering the storage layer;
the forming of the conductive gate control layer includes: and forming a grid control layer covering the second dielectric layer.
Illustratively, the channel layer may be formed on the surface of the substrate by means of ion implantation.
In some embodiments, the memory comprises a two-dimensional floating gate type memory, the method further comprising: source and drain regions are formed in the substrate by means of ion implantation and/or thermal diffusion.
In some embodiments, the memory comprises a three-dimensional floating gate type memory, the method comprising:
the forming of the conductive gate control layer includes:
forming a first stacked structure on the surface of a substrate; the first stacked structure comprises a grid control layer and a third dielectric layer which are parallel to the substrate and are sequentially and alternately stacked from bottom to top;
the second dielectric layer for forming the electrical isolation storage layer and the grid control layer, and the manufacturing method comprises the following steps:
forming a first via hole penetrating the first stacked structure; the first through hole is vertical to the plane of the substrate;
etching the end part of the grid control layer exposed through the first through hole along the direction parallel to the substrate so as to form a groove at the end part of the grid control layer close to the first through hole;
forming a second dielectric layer covering the end part of the grid control layer in the groove;
after the second dielectric layer is formed, filling the groove to form a storage layer;
after the storage layer is formed, sequentially forming a gating layer, a tunneling layer and a channel layer in the first through hole;
the second medium layer, the storage layer, the gating layer, the tunneling layer and the channel layer are perpendicular to the plane of the substrate; the tunneling layer, the gate layer, the storage layer and the second dielectric layer are sequentially stacked and surround the outer side of the channel layer.
The third dielectric layer may be composed of: silicon oxide, silicon oxynitride, or the like. It is noted that the third dielectric layer is electrically insulating and serves to electrically isolate adjacent gate control layers.
In some embodiments, the memory comprises a three-dimensional charge trapping memory, the forming a conductive gate control layer comprising:
forming a second stacked structure on the surface of the substrate; the second stacking structure comprises a sacrificial layer and a third dielectric layer which are parallel to the substrate and are sequentially and alternately stacked from bottom to top;
removing the sacrificial layer to form a gap between the adjacent third dielectric layers in the second stacked structure;
filling gaps to form a grid control layer;
the second dielectric layer for forming the electrical isolation storage layer and the grid control layer, and the manufacturing method comprises the following steps:
forming a second via hole penetrating the second stack structure;
forming a second dielectric layer covering the side wall of the second through hole in the second through hole;
forming a storage layer, a gating layer, a tunneling layer and a channel layer which cover the second medium layer in sequence in the second through hole on which the second medium layer is formed;
the second medium layer, the storage layer, the gating layer, the tunneling layer and the channel layer are perpendicular to the plane of the substrate; the tunneling layer, the gate layer, the storage layer and the second dielectric layer are sequentially stacked and surround the outer side of the channel layer.
Illustratively, the constituent materials of the sacrificial layer may include: silicon nitride or polysilicon.
The removing the sacrificial layer to form a gap between adjacent third dielectric layers in the second stacked structure includes: etching the second stacked structure to form a groove; and injecting an etchant into the groove, and enabling the etchant to be in contact with the sacrificial layer so as to remove the sacrificial layer.
When the constituent material of the sacrificial layer comprises silicon nitride, the etchant may comprise a hot phosphoric acid solution. When the constituent material of the sacrificial layer includes polysilicon, the etchant may include a tetramethylammonium hydroxide (TMAH) solution or a tetramethylammonium hydroxide gas.
In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (14)
1. A memory, comprising: the channel layer, the tunneling layer, the gate layer and the storage layer are arranged in parallel in sequence;
the gating layer has an open state and a closed state; wherein the gate layer in the on state is electrically conductive and the gate layer in the off state is electrically insulating;
the tunneling layer and the gating layer allow charged particles to be transported between the channel layer and the storage layer when the gating layer is in the on state and a voltage applied across the tunneling layer is greater than a threshold voltage;
when the gating layer is in the closed state, the tunneling layer and the gating layer block charged particles from being transmitted between the channel layer and the storage layer.
2. The memory of claim 1, further comprising:
and the first dielectric layer is positioned between the gate layer and the storage layer and used for reducing the contact resistance between the gate layer and the storage layer.
3. The memory of claim 2, wherein the first dielectric layer comprises a material comprising silicon oxide and/or silicon oxynitride.
4. The memory of claim 1, further comprising:
a second dielectric layer and a gate control layer;
the second dielectric layer is positioned between the storage layer and the grid control layer and used for electrically isolating the storage layer from the grid control layer;
the gate control layer is used for controlling the gating layer to be switched between the on state and the off state.
5. The memory of claim 4, wherein the memory comprises a two-dimensional floating gate type memory; the channel layer, the tunneling layer, the gating layer, the storage layer, the second dielectric layer and the gate control layer are sequentially stacked from bottom to top.
6. The memory of claim 4, wherein the memory comprises a three-dimensional floating gate type memory or a three-dimensional charge trapping type memory, the three-dimensional floating gate type memory or the three-dimensional charge trapping type memory comprising:
a gate stack structure comprising: the third dielectric layers and the grid control layers are sequentially and alternately stacked from bottom to top;
the channel layer, the tunneling layer, the gate layer, the storage layer and the second dielectric layer penetrate through the gate stack structure along the stacking direction of the third dielectric layer and the gate control layer;
the tunneling layer, the gate layer and the storage layer are sequentially stacked and wound on the outer side of the channel layer and are arranged between the channel layer and the second medium layer.
7. The memory of claim 1,
the thickness range of the tunneling layer is as follows: 5 to 30 angstroms;
the thickness range of the gating layer is as follows: 30 angstroms to 200 angstroms.
8. A method for manufacturing a memory, comprising:
forming a channel layer, a tunneling layer, a gate layer and a storage layer which are sequentially arranged in parallel; wherein the gating layer has an on state and an off state; the gate layer in the on state is conductive and the gate layer in the off state is electrically insulating;
the tunneling layer and the gating layer allow charged particles to be transported between the channel layer and the storage layer when the gating layer is in the on state and a voltage applied across the tunneling layer is greater than a threshold voltage;
when the gating layer is in the closed state, the tunneling layer and the gating layer block charged particles from being transmitted between the channel layer and the storage layer.
9. The method of claim 8, further comprising:
forming a first dielectric layer covering the gate layer; the first dielectric layer is located between the gate layer and the storage layer and used for reducing contact resistance between the gate layer and the storage layer.
10. The method of claim 9, wherein the first dielectric layer comprises a material comprising silicon oxide and/or silicon oxynitride.
11. The method of claim 8, further comprising:
forming a conductive gate control layer; the gate control layer is used for controlling the gating layer to switch between the on state and the off state;
forming a second dielectric layer electrically isolating the storage layer and the gate control layer; and the second dielectric layer is positioned between the storage layer and the grid control layer.
12. The method of claim 11, wherein the memory comprises a two-dimensional floating gate memory, and wherein forming the channel layer, the tunneling layer, the gate layer, and the memory layer in parallel in that order comprises:
forming a channel layer on the surface of the substrate; wherein the channel layer is parallel to the plane of the substrate;
the tunneling layer, the gate layer and the storage layer are sequentially formed on the surface of the channel layer from bottom to top in a parallel and stacked mode along the direction perpendicular to the plane of the substrate;
the forming a second dielectric layer electrically isolating the memory layer and the gate control layer includes: forming a second dielectric layer covering the storage layer;
the forming of the conductive gate control layer includes: and forming the grid control layer covering the second dielectric layer.
13. The method of claim 11, wherein the memory comprises a three-dimensional floating gate type memory, the method comprising:
the forming of the conductive gate control layer includes:
forming a first stacked structure on the surface of a substrate; the first stacked structure comprises a grid control layer and a third dielectric layer which are parallel to the substrate and are sequentially and alternately stacked from bottom to top;
the second dielectric layer electrically isolating the storage layer and the grid control layer is formed, and the channel layer, the tunneling layer, the gate layer and the storage layer are sequentially arranged in parallel, and the method comprises the following steps:
forming a first via through the first stacked structure; wherein the first through hole is vertical to the plane of the substrate;
etching the end part of the grid control layer exposed through the first through hole along the direction parallel to the substrate so as to form a groove at the end part of the grid control layer close to the first through hole;
forming a second dielectric layer covering the end part of the grid control layer in the groove;
after the second dielectric layer is formed, filling the groove to form the storage layer;
after the storage layer is formed, sequentially forming the gate layer, the tunneling layer and the channel layer in the first through hole;
the second dielectric layer, the storage layer, the gate layer, the tunneling layer and the channel layer are perpendicular to the plane of the substrate; the tunneling layer, the gate layer, the storage layer and the second dielectric layer are sequentially stacked and surround the outer side of the channel layer.
14. The method of claim 11, wherein the memory comprises a three-dimensional charge-trapping memory,
the forming of the conductive gate control layer includes:
forming a second stacked structure on the surface of the substrate; the second stacking structure comprises a sacrificial layer and a third dielectric layer which are parallel to the substrate and are sequentially and alternately stacked from bottom to top;
removing the sacrificial layer to form a gap between the adjacent third dielectric layers in the second stacked structure;
filling the gap to form the grid control layer;
the second dielectric layer electrically isolating the storage layer and the grid control layer is formed, and the channel layer, the tunneling layer, the gate layer and the storage layer are sequentially arranged in parallel, and the method comprises the following steps:
forming a second via through the second stack structure;
forming a second dielectric layer covering the side wall of the second through hole in the second through hole;
forming the storage layer, the gate layer, the tunneling layer and the channel layer in sequence in the second through hole formed with the second dielectric layer, wherein the storage layer, the gate layer, the tunneling layer and the channel layer cover the second dielectric layer;
the second dielectric layer, the storage layer, the gate layer, the tunneling layer and the channel layer are perpendicular to the plane of the substrate; the tunneling layer, the gate layer, the storage layer and the second dielectric layer are sequentially stacked and surround the outer side of the channel layer.
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