CN112103287A - Electrostatic discharge protection circuit and application thereof - Google Patents
Electrostatic discharge protection circuit and application thereof Download PDFInfo
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- CN112103287A CN112103287A CN202011249787.7A CN202011249787A CN112103287A CN 112103287 A CN112103287 A CN 112103287A CN 202011249787 A CN202011249787 A CN 202011249787A CN 112103287 A CN112103287 A CN 112103287A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Abstract
The invention discloses an electrostatic discharge protection circuit, which comprises a first type well and a second type well which are arranged side by side on a substrate, a protection ring arranged on the first type well, a body end arranged on the second type well, a first electrode arranged on the second type well, a second electrode arranged on the second type well, a grid electrode arranged between the first electrode and the second electrode, wherein the first electrode is positioned on the other side of the body end relative to the protection ring; wherein a distance between the body terminal and the second electrode is greater than a distance between the body terminal and the gate electrode, the guard ring and the first electrode are connected to a first potential point, and the body terminal, the gate electrode and the second electrode are connected to a second potential point. The electrostatic discharge protection circuit provided by the invention can enhance the latch-up resistance.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an electrostatic discharge protection circuit and application thereof.
Background
In recent years, in a semiconductor integrated circuit, an electrostatic discharge (ESD) protection circuit is provided between a signal input terminal and an internal chip in order to prevent electrostatic breakdown due to Static electricity from the outside or the like.
However, in the design of general esd protection circuits, parasitic effects generated in the circuits are generally ignored. Once the breakdown voltage of the circuit device is insufficient, the internal part of the circuit device can be burnt.
Disclosure of Invention
The invention aims to provide an electrostatic discharge protection circuit and application thereof, and the electrostatic discharge protection circuit provided by the invention can enhance the capability of resisting latch-up effect, thereby protecting the devices of the electrostatic discharge protection circuit.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides an electrostatic discharge protection circuit, which comprises:
a substrate provided with a first type well and a second type well side by side;
the protection ring is arranged on the first type trap and is a first type doping area;
a body terminal disposed on the second-type well, the body terminal being a second-type doped region;
a first electrode disposed on the well of the second type and on the other side of the body end with respect to the guard ring, the first electrode being the doped region of the first type;
a second electrode disposed on the well of the second type and on the other side of the first electrode with respect to the body end, the second electrode being the doped region of the first type;
a gate electrode disposed between the first electrode and the second electrode;
wherein a distance between the body terminal and the second electrode is greater than a distance between the body terminal and the gate electrode, the guard ring and the first electrode are connected to a first potential point, and the body terminal, the gate electrode and the second electrode are connected to a second potential point.
In an embodiment of the invention, the esd protection circuit further includes a silicide blocking region, the silicide blocking region is located on the second type well and disposed between the first electrode and the gate, and a depth of the silicide blocking region is smaller than a depth of the first electrode.
In an embodiment of the invention, the esd protection circuit further includes a first trench isolation structure disposed on the first type well and the substrate and located on another side of the first type well relative to the second type well.
In an embodiment of the invention, a depth of the first trench isolation structure is greater than a depth of the first electrode.
In an embodiment of the invention, the esd protection circuit further includes a second trench isolation structure, and the second trench isolation structure is located on the first type well and the second type well, and located between the guard ring and the body terminal.
In an embodiment of the invention, the esd protection circuit further includes a third trench isolation structure located on the second type well and between the body terminal and the first electrode.
In an embodiment of the invention, the esd protection circuit further includes a fourth trench isolation structure, where the fourth trench isolation structure is located on the second-type well and the substrate, and is located on another side of the second-type well opposite to the first-type well.
In an embodiment of the invention, the first electrode is a drain.
In an embodiment of the invention, the second electrode is a source.
In an embodiment of the present invention, a parasitic bipolar junction transistor is formed in the esd protection circuit, the second electrode is an emitter of the parasitic bipolar junction transistor, the body terminal is a base of the parasitic bipolar junction transistor, and the guard ring is a collector of the parasitic bipolar junction transistor.
The present invention also provides an electrostatic discharge protection circuit of an internal circuit, the electrostatic discharge protection circuit of the internal circuit including:
an internal circuit on which a plurality of input/output interfaces are provided;
a plurality of the electrostatic discharge protection circuits, one end of each of the electrostatic discharge protection circuits being connected to each of the input/output interfaces; the electrostatic discharge protection circuit includes:
a substrate provided with a first type well and a second type well side by side;
the protection ring is arranged on the first type trap and is a first type doping area;
a body terminal disposed on the second-type well, the body terminal being a second-type doped region;
a first electrode disposed on the well of the second type and on the other side of the body end relative to the guard ring, the first electrode being a first type doped region;
a second electrode disposed on the well of the second type and on the other side of the first electrode relative to the body end, the second electrode being a doped region of the first type;
a gate electrode disposed between the first electrode and the second electrode;
wherein the distance between the body terminal and the second electrode is greater than the distance between the body terminal and the gate, the guard ring is connected to the first electrode at a first potential point, and the body terminal, the gate and the second electrode are connected to a second potential point;
a plurality of external terminals, each external terminal being connected to the other end of each of the electrostatic discharge protection circuits.
According to the electrostatic discharge protection circuit provided by the invention, the protection ring is arranged on the first-type trap and is connected with the first potential point, so that the influence of an external signal on the electrostatic discharge protection circuit can be effectively eliminated, and the anti-interference capability of the electrostatic discharge protection circuit is improved; providing a potential to said ESD protection circuit by placing said body terminal on said second type well; the electrostatic discharge protection circuit is opened more uniformly by arranging the silicide blocking region between the first electrode and the grid electrode; the distance from the second electrode to the body end is set to be larger than the distance from the gate to the body end, and the base region of a parasitic bipolar junction transistor in the electrostatic discharge protection circuit is lengthened, so that the amplification capacity of the parasitic bipolar junction transistor is reduced, and the latch-up resisting capacity of the electrostatic discharge protection circuit is enhanced.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of an ESD protection circuit for a PMOS transistor.
FIG. 2 is a schematic diagram of an ESD protection circuit for an NMOS transistor.
FIG. 3 is an ESD protection circuit for an internal circuit.
Description of reference numerals:
100 a substrate; 101 a first type well; 102 a second type well; 201 a first trench isolation structure; 202 a second trench isolation structure; 203 a third trench isolation structure; 204 a fourth trench isolation structure; 301 a guard ring; 302 body end; 303 a first electrode; 304 a second electrode; 305 a grid electrode; 306 a silicide blocking region; 400 parasitic bipolar junction transistors.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Electrostatic discharge is one of the major factors responsible for the degradation of the majority of chips by the physical electrical stress. Electrostatic discharge includes two categories, on-chip electrostatic discharge and system-level electrostatic discharge. The chip-level electrostatic discharge comprises a human body discharge mode, a machine discharge mode, an element charging mode and an electric field induction mode, and the system-level electrostatic discharge comprises a contact mode and an air mode. The application provides a pair of electrostatic discharge protection circuit can alleviate latch-up effect in the electrostatic discharge protection device, electrostatic discharge protection circuit includes the connection of electrostatic discharge protection device and circuit, the electrostatic discharge protection device is Metal Oxide Semiconductor field effect (MOS) transistor for example.
Referring to fig. 1, in an embodiment of the invention, the esd protection circuit includes a substrate 100, a recess is disposed on the substrate 100, and a first type well 101 and a second type well 102 are disposed in parallel on the recess, wherein the first type well 101 is a P-type well and the second type well 102 is an N-type well. First-type well 101 and second-type well 102 are disposed within a recess of substrate 100, and a width of an area of first-type well 101 is smaller than a width of second-type well 102. A second trench isolation structure 202 is further disposed between the first-type well 101 and the second-type well 102, and a boundary between the first-type well 101 and the second-type well 102 divides the second trench isolation structure 202 into two symmetrical parts, wherein one part is located on the first-type well 101, the other part is located on the second-type well 102, and a depth of the second trench isolation structure 202 is greater than half of a depth of the recess. A fourth trench isolation structure 204 is disposed on the other side of second-type well 102 opposite to first-type well 101, and fourth trench isolation structure 204 is partially located on second-type well 102 and partially located on substrate 100, and the depth of fourth trench isolation structure 204 is the same as the depth of second trench isolation structure 202.
Referring to fig. 1, in an embodiment of the invention, a protection ring 301 is disposed on the well 101 of the first type, the protection ring 301 is disposed adjacent to the second trench isolation structure 202, and the protection ring 301 is disposed on the other side of the second trench isolation structure 202 relative to the fourth trench isolation structure 204. The guard ring 301 is a pocket-like structure extending deep into the well 101 of the first type, and the depth of the guard ring 301 is smaller than that of the second trench isolation structure 202. The guard ring 301 is a first type doped region, which in this embodiment is a P-type doped region. A first trench isolation structure 201 is further disposed on the other side of the first-type well 101 opposite to the second-type well 102, the first trench isolation structure 201 is partially located on the first-type well 101 and partially located on the substrate 100, and a depth of the first trench isolation structure 201 is the same as a depth of the second trench isolation structure 202. A protection ring 301 is arranged in the electrostatic discharge protection device, and the protection ring 301 is connected with a first potential point in an external circuit, so that the influence of an external signal on an internal circuit of the electrostatic discharge protection device can be effectively eliminated, and the anti-interference capability of the electrostatic discharge protection device is improved. In this embodiment, the first potential point is a ground GND.
Referring to fig. 1, in an embodiment of the invention, a body terminal 302 is disposed on the well 102 of the second type, the body terminal 302 is disposed near one side of the second trench isolation structure 202, and the body terminal 302 is disposed on the other side of the second shallow trench isolation structure 202 opposite to the guard ring 301. The body end 302 is a pocket-like structure deep into the well 102 of the second type, and the depth of the body end 302 is less than the depth of the second trench isolation structure 202. The body terminal 302 is a second type doped region, which in this embodiment is an N-type doped region. In circuit connection, the body terminal 302 is connected to a second potential point to provide a potential for the esd protection device. In the embodiment, the second potential point is a fixed voltage point VDD, for example, 3V to 5V.
Referring to fig. 1, in an embodiment of the invention, a third trench isolation structure 203, a first electrode 303, a gate 305 and a second electrode 304 are further disposed on the well 102 of the second type. The third trench isolation structure 203 is located on the other side of the body end 302 relative to the second trench isolation structure 202, and the third trench isolation structure 203 is located adjacent to the body end 302, the depth of the third trench isolation structure 203 being the same as the depth of the first trench isolation structure 201. A first electrode 303 is located on the other side of the third trench isolation structure 203 from the body end 302 and is disposed adjacent to the third trench isolation structure 203, a second electrode 304 is located on the other side of the first electrode 303 from the third trench isolation structure 203, and a gate 305 is located between the first electrode 303 and the second electrode 304 and is disposed adjacent to the second electrode 304. The first electrode 303 and the second electrode 304 are the first type doped region, i.e., the P-type doped region, the first electrode 303 and the second electrode 304 are pocket structures extending into the second type well 102, the depth of the first electrode 303 and the second electrode 304 is smaller than the depth of the first trench isolation structure 201, and the gate 305 is a polysilicon layer disposed on the second type well 102. In this embodiment, the first electrode 303 is a drain, the second electrode 304 is a source, the first electrode 303 and the guard ring 301 are connected to the first potential point, i.e. to the ground GND; the second electrode 304, the gate 305, is connected to the second potential point, i.e. to the fixed voltage point VDD.
Referring to fig. 1, in an embodiment of the invention, a silicide blocking region 306 is further disposed between the first electrode 303, i.e., the drain and the gate 305, the silicide blocking region 306 is directly defined by a mask, and the silicide blocking region 306 is remained during photolithography. A silicide block region 306 is disposed between the gate 305 and the first electrode 303, and the depth of the silicide block region 306 is less than the depth of the first electrode 303. The silicide blocking region 306 can prevent the metal cobalt or nickel from reacting with silicon to form a low-resistance silicide region, and the silicide blocking region 306 forms a high-resistance structure, so that the electrostatic discharge protection device is more uniformly opened when electrostatic discharge occurs, and the quality of the electrostatic discharge protection circuit is improved.
Referring to fig. 2, in another embodiment of the present invention, the esd protection circuit includes a substrate 100, a recess is disposed on the substrate 100, and a first type well 101 and a second type well 102 are disposed in parallel on the recess, wherein the first type well 101 is an N-type well and the second type well 102 is a P-type well. First-type well 101 and second-type well 102 are disposed within a recess of substrate 100, and a width of an area of first-type well 101 is smaller than a width of second-type well 102. A second trench isolation structure 202 is further disposed between the first-type well 101 and the second-type well 102, and a boundary between the first-type well 101 and the second-type well 102 divides the second trench isolation structure 202 into two symmetrical parts, wherein one part is located on the first-type well 101, the other part is located on the second-type well 102, and a depth of the second trench isolation structure 202 is greater than half of a depth of the recess. A fourth trench isolation structure 204 is disposed on the other side of second-type well 102 opposite to first-type well 101, and fourth trench isolation structure 204 is partially located on second-type well 102 and partially located on substrate 100, and the depth of fourth trench isolation structure 204 is the same as the depth of second trench isolation structure 202.
Referring to fig. 2, in another embodiment of the present invention, a protection ring 301 is disposed on the well 101 of the first type, the protection ring 301 is disposed adjacent to the second trench isolation structure 202, and the protection ring 301 is disposed on the other side of the second trench isolation structure 202 opposite to the fourth trench isolation structure 204. The guard ring 301 is a pocket-like structure extending deep into the well 101 of the first type, and the depth of the guard ring 301 is smaller than that of the second trench isolation structure 202. The guard ring 301 is a first type doped region, which in this embodiment is an N-type doped region. A first trench isolation structure 201 is further disposed on the other side of the first-type well 101 opposite to the second-type well 102, the first trench isolation structure 201 is partially located on the first-type well 101 and partially located on the substrate 100, and a depth of the first trench isolation structure 201 is the same as a depth of the second trench isolation structure 202. A protection ring 301 is arranged in the electrostatic discharge protection device, and the protection ring 301 is connected with a first potential point in an external circuit, so that the influence of an external signal on an internal circuit of the electrostatic discharge protection device can be effectively eliminated, and the anti-interference capability of the electrostatic discharge protection device is improved. In the embodiment, the first potential point is a fixed voltage point VDD, for example, 3V to 5V.
Referring to fig. 2, in another embodiment of the present invention, a body terminal 302 is disposed on the well 102 of the second type, the body terminal 302 is disposed near one side of the second trench isolation structure 202, and the body terminal 302 is disposed on the other side of the second shallow trench isolation structure 202 opposite to the guard ring 301. The body end 302 is a pocket-like structure deep into the well 102 of the second type, and the depth of the body end 302 is less than the depth of the second trench isolation structure 202. The body terminal 302 is a second type doped region, which in this embodiment is a P-type doped region. In circuit connection, the body terminal 302 is connected to a second potential point to provide a potential for the esd protection device. In this embodiment, the second potential point is a ground GND.
Referring to fig. 2, in another embodiment of the present invention, a third trench isolation structure 203, a first electrode 303, a gate 305 and a second electrode 304 are further disposed on the well 102 of the second type. The third trench isolation structure 203 is located on the other side of the body end 302 relative to the second trench isolation structure 202, and the third trench isolation structure 203 is located adjacent to the body end 302, the depth of the third trench isolation structure 203 being the same as the depth of the first trench isolation structure 201. A first electrode 303 is located on the other side of the third trench isolation structure 203 from the body end 302 and is disposed adjacent to the third trench isolation structure 203, a second electrode 304 is located on the other side of the first electrode 303 from the third trench isolation structure 203, and a gate 305 is located between the first electrode 303 and the second electrode 304 and is disposed adjacent to the second electrode 304. The first electrode 303 and the second electrode 304 are the first type doped region, i.e., the N-type doped region, the first electrode 303 and the second electrode 304 are pocket structures extending into the second type well 102, the depth of the first electrode 303 and the second electrode 304 is smaller than the depth of the first trench isolation structure 201, and the gate 305 is a polysilicon layer disposed on the second type well 102. In this embodiment, the first electrode 303 is a drain, the second electrode 304 is a source, the first electrode 303 and the guard ring 301 are connected to the first potential point, i.e., the fixed voltage point VDD; the second electrode 304 and the gate 305 are connected to the second potential point, i.e. to the ground GND.
Referring to fig. 2, in another embodiment of the present invention, a silicide blocking region 306 is further disposed between the first electrode 303, i.e., the drain and the gate 305, the silicide blocking region 306 is directly defined by a mask, and the silicide blocking region 306 is remained during photolithography. A silicide block region 306 is disposed between the gate 305 and the first electrode 303, and the depth of the silicide block region 306 is less than the depth of the first electrode 303. The silicide blocking region 306 can prevent the metal cobalt or nickel from reacting with silicon to form a low-resistance silicide region, and the silicide blocking region 306 forms a high-resistance structure, so that the electrostatic discharge protection device is more uniformly opened when electrostatic discharge occurs, and the quality of the electrostatic discharge protection circuit is improved.
Referring to fig. 1 to 2, in the esd protection circuit according to the present invention, the second electrode 304, the body terminal 302, and the gate 305 are connected to the second potential point, and the guard ring 301 and the first electrode 303 are connected to the first potential point. A parasitic bipolar junction transistor 400 is formed inside the esd protection device, the parasitic bipolar junction transistor 400 in fig. 1 is a PNP bipolar junction transistor, and the parasitic bipolar junction transistor 400 in fig. 2 is an NPN bipolar junction transistor. Second electrode 304 is the emitter of parasitic bipolar junction transistor 400, body terminal 302 is the base of parasitic bipolar junction transistor 400, and guard ring 301 is the collector of parasitic bipolar junction transistor 400. By increasing the collector (second electrode 304) to base (body terminal 302) distance of the parasitic bjt 400 to be greater than the gate 305 to body terminal 302 distance, the base region of the parasitic bjt 400 is lengthened, thereby reducing the amplification of the parasitic bjt 400 and enhancing the latch-up resistance of the esd protection circuit.
Referring to fig. 3, an esd protection circuit for an internal circuit 30 according to the present invention is used for esd protection of the internal circuit 30. The internal circuit 30 includes a plurality of Input/Output (I/O) interfaces that are susceptible to electrostatic interference, and the electrostatic discharge protection circuit is provided between the plurality of external terminals 40 and the plurality of Input/Output interfaces of the internal circuit 30 to protect the internal circuit 30, and includes two different electrostatic discharge protection devices including the N-type mosfet 20 and the P-type mosfet 10. The gate 305, source and bulk 302 of the P-type mosfet 10 are connected to the voltage point VDD, and the drain and guard ring 301 (not shown in fig. 3) of the P-type mosfet 10 are connected to the input/output interface of the internal circuit 30; the gate 305, source and bulk 302 of the nmos fet 20 are connected to the ground GND, and the drain of the nmos fet 20 and the guard ring 301 (not shown in fig. 3) are connected to the input/output interface of the internal circuit 30.
The invention provides an electrostatic discharge protection circuit, which comprises the electrostatic discharge protection device and the connection of the electrostatic discharge protection device and the circuit thereof, wherein a guard ring 301 and a first electrode 303 are connected to a first potential point, a body terminal 302, a grid 305 and a second electrode 304 are connected to a second potential point, a parasitic bipolar junction transistor 400 is formed between a first type trap 101 and a second type trap 102, the second electrode 304 is arranged on the other side of the grid 305 relative to the body terminal 302, the distance from the second electrode 304 to the body terminal 302 is larger than the distance from the grid 305 to the body terminal 302, the base region of the parasitic bipolar junction transistor 400 is lengthened, the amplification capacity of the parasitic bipolar junction transistor 400 is reduced, and the latch-up resisting capacity of the electrostatic discharge protection circuit is enhanced.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (11)
1. An electrostatic discharge protection circuit, comprising:
a substrate provided with a first type well and a second type well side by side;
the protection ring is arranged on the first type trap and is a first type doping area;
a body terminal disposed on the second-type well, the body terminal being a second-type doped region;
a first electrode disposed on the well of the second type and on the other side of the body end with respect to the guard ring, the first electrode being the doped region of the first type;
a second electrode disposed on the well of the second type and on the other side of the first electrode with respect to the body end, the second electrode being the doped region of the first type;
a gate electrode disposed between the first electrode and the second electrode;
wherein a distance between the body terminal and the second electrode is greater than a distance between the body terminal and the gate electrode, the guard ring and the first electrode are connected to a first potential point, and the body terminal, the gate electrode and the second electrode are connected to a second potential point.
2. The ESD protection circuit of claim 1 further comprising a silicide blocking region on the well of the second type and disposed between the first electrode and the gate, wherein the silicide blocking region has a depth less than the depth of the first electrode.
3. The ESD protection circuit of claim 1 further comprising a first trench isolation structure disposed over the well of the first type and the substrate and on the other side of the well of the first type relative to the well of the second type.
4. The ESD protection circuit of claim 3, wherein the first trench isolation structure has a depth greater than a depth of the first electrode.
5. The ESD protection circuit of claim 1 further comprising a second trench isolation structure on the first and second type wells between the guard ring and the body terminal.
6. The ESD protection circuit of claim 1 further comprising a third trench isolation structure on the well of the second type between the body terminal and the first electrode.
7. The ESD protection circuit of claim 1 further comprising a fourth trench isolation structure on the second type well and the substrate and on the other side of the second type well relative to the first type well.
8. The esd protection circuit of claim 1, wherein the first electrode is a drain electrode.
9. The esd protection circuit of claim 1, wherein the second electrode is a source.
10. The esd protection circuit of claim 1, wherein a parasitic bjt is formed inside the esd protection circuit, the second electrode is an emitter of the parasitic bjt, the body terminal is a base of the parasitic bjt, and the guard ring is a collector of the parasitic bjt.
11. An electrostatic discharge protection circuit of an internal circuit, the electrostatic discharge protection circuit of the internal circuit comprising:
an internal circuit on which a plurality of input/output interfaces are provided;
a plurality of the electrostatic discharge protection circuits, one end of each of the electrostatic discharge protection circuits being connected to each of the input/output interfaces; the electrostatic discharge protection circuit includes:
a substrate provided with a first type well and a second type well side by side;
the protection ring is arranged on the first type trap and is a first type doping area;
a body terminal disposed on the second-type well, the body terminal being a second-type doped region;
a first electrode disposed on the well of the second type and on the other side of the body end relative to the guard ring, the first electrode being a first type doped region;
a second electrode disposed on the well of the second type and on the other side of the first electrode relative to the body end, the second electrode being a doped region of the first type;
a gate electrode disposed between the first electrode and the second electrode;
wherein the distance between the body terminal and the second electrode is greater than the distance between the body terminal and the gate, the guard ring is connected to the first electrode at a first potential point, and the body terminal, the gate and the second electrode are connected to a second potential point;
a plurality of external terminals, each of which is connected to the other end of each of the electrostatic discharge protection circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011249787.7A CN112103287A (en) | 2020-11-11 | 2020-11-11 | Electrostatic discharge protection circuit and application thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011249787.7A CN112103287A (en) | 2020-11-11 | 2020-11-11 | Electrostatic discharge protection circuit and application thereof |
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| CN112103287A true CN112103287A (en) | 2020-12-18 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050045952A1 (en) * | 2003-08-27 | 2005-03-03 | International Business Machines Corporation | Pfet-based esd protection strategy for improved external latch-up robustness |
| CN109712971A (en) * | 2017-10-26 | 2019-05-03 | 南亚科技股份有限公司 | Semiconductor electrostatic discharge prevention element |
| CN111370405A (en) * | 2020-04-21 | 2020-07-03 | 伟芯科技(绍兴)有限公司 | Full-voltage ESD structure and implementation method |
-
2020
- 2020-11-11 CN CN202011249787.7A patent/CN112103287A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050045952A1 (en) * | 2003-08-27 | 2005-03-03 | International Business Machines Corporation | Pfet-based esd protection strategy for improved external latch-up robustness |
| CN109712971A (en) * | 2017-10-26 | 2019-05-03 | 南亚科技股份有限公司 | Semiconductor electrostatic discharge prevention element |
| CN111370405A (en) * | 2020-04-21 | 2020-07-03 | 伟芯科技(绍兴)有限公司 | Full-voltage ESD structure and implementation method |
Non-Patent Citations (1)
| Title |
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| 刘睿强 等: "《集成电路版图设计》", 31 March 2011 * |
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Application publication date: 20201218 |