CN112101218B

CN112101218B - Artificial intelligence system of going over examination papers

Info

Publication number: CN112101218B
Application number: CN202010970499.4A
Authority: CN
Inventors: 何彩鹏
Original assignee: Cmac Information Technology Co ltd
Current assignee: Cmac Information Technology Co ltd
Priority date: 2020-10-16
Filing date: 2020-10-16
Publication date: 2021-05-18
Anticipated expiration: 2040-10-16
Also published as: CN112101218A

Abstract

The invention discloses an artificial intelligence scoring system, which comprises a controller circuit, a peripheral circuit, a communication circuit, a main chip, a BOOT circuit, a power filter circuit and a TYPE-C interface, wherein the BOOT circuit controls the main chip to enter a BOOT0 mode, a BOOT1 mode, a BOOT2 mode and a BOOT3 mode, the controller circuit, the peripheral circuit and the communication circuit are divergently connected by taking the main chip as a center, the controller circuit provides a control signal for the peripheral circuit, the peripheral circuit is controlled to realize the functions of storage, scanning, printing, dimming, display and prompting, the communication circuit carries out information interaction with a PC through a Wi-Fi module circuit or a network interface module circuit, a TCP-IP protocol is adopted for information transmission, and the 802.11b/g/n standard is supported; the invention can scan the test paper in batches, warn the test paper which does not meet the requirements and exceeds the range, prompt the reader to pick out the abnormal test paper and manually check, can improve the scanning quality of the test paper and has good market prospect.

Description

Artificial intelligence system of going over examination papers

The technical field is as follows:

the invention relates to the field of intelligent marking, in particular to an artificial intelligent marking system.

Background art:

with the popularization of computers and artificial intelligence, artificial intelligence is applied in a plurality of fields of work and life. For education, education and examination are closely related, a teacher needs to turn over examination paper one by one and correct the examination paper one by one during paper marking to count objective scores, wrong judgment is often caused by excessive answers for some subjects with more objective questions, a large amount of time is occupied by the teacher in the traditional paper marking work, and the time which is not enough is more short. Therefore, manual paper marking systems come up, but the existing paper marking systems only can scan one test paper at a time, and the test paper needs to be scanned manually in real time, so that the problems of missed scanning, multiple scanning, scanning area deviation and the like of the test paper are easily caused, the paper marking quality is influenced, and the labor intensity of paper marking personnel is increased, and the energy of teachers is excessively consumed.

The invention content is as follows:

in view of this, the invention provides an artificial intelligence marking system, which can realize functions of continuous scanning, uploading, analysis and the like, and especially can perform early warning in time when scanning is abnormal, so as to improve the accuracy of scanning.

The invention provides an artificial intelligence marking system, which comprises a controller circuit, a peripheral circuit, a communication circuit, a main chip, a BOOT circuit, a power supply filter circuit and a TYPE-C interface, wherein the BOOT circuit controls the main chip to enter a BOOT0 mode, a BOOT1 mode, a BOOT2 mode and a BOOT3 mode, the power supply filter circuit provides stable +3.3V voltage and +1.8V voltage for the whole circuit, the TYPE-C interface can carry out data transmission with external equipment, the controller circuit, the peripheral circuit and the communication circuit carry out data interaction through the main chip, the controller circuit provides control signals for the peripheral circuit, the controller circuit comprises a clock circuit, an LED indicator lamp circuit, a USB serial port conversion module circuit, a battery charging circuit, a bleeder circuit, an SRAM circuit, a JTAG circuit and a reset circuit, the peripheral circuit comprises a stepping motor circuit, a display circuit, a memory circuit, a camera circuit and an alarm circuit, The communication circuit comprises a Wi-Fi module circuit, a network port module circuit and a wireless module circuit, sub-circuits contained in the controller circuit, the peripheral circuit and the communication circuit are integrated by taking a main chip as a center, the controller circuit provides control signals for the peripheral circuit and controls the peripheral circuit to realize the functions of storage, scanning, printing, dimming, display and prompt, the communication circuit performs information interaction with a PC through the Wi-Fi module circuit or the network port module circuit, a TCP-IP protocol is adopted for information transmission, and the 802.11b/g/n standard is supported.

Furthermore, the clock circuit comprises two clock circuits, the first clock circuit is composed of an 8M crystal oscillator and two 24P ceramic chip capacitors, the second clock circuit comprises a 30M crystal oscillator chip, two pins of the 8M crystal oscillator are connected with an X1 pin and an X2 pin of the main chip, a CLK pin of the 30M crystal oscillator chip is connected with an X1 pin of the main chip, VCC is connected with 3.3V voltage, an LED indicator lamp circuit is composed of a 330 ohm current-limiting resistor and an LED lamp, the anode of the LED lamp 1 is connected with 3.3V voltage, the cathode is connected with PWM7, PWM8 and PWM9 pins of the main chip, the anode of the LED lamp 2 is connected with 3.3V voltage, the cathode is connected with CAP5, C6TIP and IRTDD pins of the main chip, the USB to serial port circuit comprises a serial port chip U18, a USB interface and a third crystal oscillator circuit, the 1, 3 and 5 pins of the serial port U18 are respectively connected with PWM10, TCB and PWM11 pins of the main chip, the USB interface is connected with a serial port U2, a serial port 53927 pin of the USB chip and a serial port 53927 pin of the serial port U2, the battery charging circuit comprises a charging chip U7, a battery CN1 and operation indicator lamps D2 and D3, wherein a1 pin of the charging chip U7 is connected with an anode of an operation indicator lamp D2 and a cathode of an operation indicator lamp D3, an anode of an operation indicator lamp D3 is connected with a 5V voltage, a3 pin of the charging chip U7 is connected with an anode of a battery CN1, a4 pin is connected with a 5V voltage, a voltage division circuit comprises a power supply chip U9 and an operation indicator lamp D16, 5 and 6 pins of the power supply chip U9 are connected with a 5V voltage and an anode of an operation indicator lamp D16, 17 and 18 pins are connected with a 3.3V voltage and a VDD3VFL pin of a main chip, 23 and 24 are connected with a 1.8V voltage, and the SRAM circuit comprises an SRAM chip U8, and 1, 2, 3, 4, 5, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 42, 43, 44, 7, 8, 9, 10, 30, 31, 16, 31, 32, 31, 32, 31, 36. the

pins

37, 38, 6, 17, 41 are respectively connected with XA0, XA1, XA2, XA3, XA4, XA5, XA6, XA7, XA8, XA16, XA17, XA9, XA10, XA11, XA12, XA13, XA14, XA15, XD0, XD1, XD2, XD3, XD4, XD5, XZCS6AND 5, WEXXXXXX, XRD pins, 39, 40, 12, 34 pins of SRAM chip U5 are respectively connected with the

pins

11, 13 AND 3V voltage, the circuit adopts 14 pins, 1 pin, 7 pin, 13 pin, 14, 1 pin, 13 pin, 13, TCK pin, TCK 3, TCK 14, TCK 3, TCK 14, TCK 3.

Furthermore, the model of the main chip is TMS320F2812, the model of the serial port chip U18 is PL2303, the model of the charging chip U7 is MCP73831, the model of the power supply chip U9 is TPS767D318, and the model of the SRAM chip U8 is CY7C1041CV 33.

Further, the stepping motor circuit is characterized in that a four-way optical coupler circuit controls two-way stepping motors through a driving chip, a PWM1 pin of a main chip is connected with a cathode of an LED2 and a cathode of an optocoupler TLP1 light emitter in series, a PWM2 pin is connected with a cathode of an LED3 and a cathode of an optocoupler TLP2 light emitter in series, a PWM3 pin is connected with a cathode of an LED4 and a cathode of an optocoupler TLP3 light emitter in series, a PWM4 pin is connected with a cathode of an LED5 and a cathode of an optocoupler TLP4 light emitter in series, 4 optocouplers are connected with 5V voltage through exclusion R-1, cathodes of the light receivers of the optocouplers TLP1, TLP2, TLP3 and TLP4 are connected with 5, 7, 10 and 12 pins of the driving chip, a pin PWMA1 is connected with a PWM 84 pin of the main chip, a pin 2 pin is connected with a6 pin of the driving chip, a3 pin is connected with 5V voltage, a pin is connected with a1 pin of the driving chip, a pin of the PWMA 36MB 42, a pin is connected with a,

Pins

13 and 14 are respectively connected with

pins

1 and 2 of a stepping motor M2,

pins

9, 5V, 4, 12V and 1 and 15 of a driving chip are respectively connected with a pin 12V, a pin 15, a

19 and 9 of the driving chip are respectively connected with pins XA0, XA1, XA2, XA3 and XA4 of a main chip,

pins

9 and 6 of the OLED display are connected with a pin 3.3V and a filter capacitor, a memory circuit comprises a memory CARD CARD1,

pins

1, 5, 7, 8 and 9 of the memory CARD CARD1 are respectively connected with pins XD9, XD10, XD11, XD12, XD13, pins 3.3V, 6and 3, pins are respectively connected with a pin 3.3V, 9, a

14, 15A, 15V and 9 of the camera is connected with pins 3.3V, 2, 3, 6, 15, 17, 15, 17, 9, ADCINA1, ADCINA2, ADCINA3, ADCINA4, ADCINA5, ADCINA6, ADCINA7, ADCINB7, ADCINB6, ADCINB5, ADCINB4, ADCINB3, and ADCINB3 pins, an alarm circuit includes a transistor Q3 and a buzzer B3, the base of the transistor Q3 is connected with the XD3 pin of the main chip, the collector is connected with 3.3V voltage, the emitter is connected with the buzzer B3, a sensor circuit includes a sensor U3, the 2 and 3 pins of the sensor U3 are connected with the XD3 and XD3 pins of the main chip, the 1, 5 and 8 pins are connected with 3.3V voltage, the 6and7 pins are grounded, the 14, 13 and 12 pins are connected with 3.3V voltage and the XD3, XD XA, XA 72, XDXA 72, XD 72,

voice chip

72, 3, voice chip 3, voice chip header, 3,

voice chip

19, 3, 36, XD5 pin, voice chip U5 with 9 pin connected with capacitor C46 and first pin of microphone Mic, 10 pin connected with capacitor C47 and second pin of microphone Mic, 12 pin connected with first pin of microphone Mic, 19, 23, 7, 1 and 32 pin connected with 3.3V voltage, PWM light-adjusting circuit including transistors Q2, Q3 and LED light-adjusting bank lamp, transistor Q3 with base connected with XD7 pin of main chip, emitter grounded, collector connected with VCC voltage and base of transistor Q2, transistor Q2 with emitter connected with VCC power supply, collector connected with anode of light-adjusting bank lamp, printing module circuit including printing chip U11, U12, U13, U15, gate U14A, gate U14B and printing interface J2, printing chip 12 with 3, 4, 7, 8, 13, 14, 17 and 18 connected with host chip, CTT 1-585, CTP 5-PCEP 465, CTPI-P5-P5, CAP4 and CAP6, 1 and 2 pins of gate U14A are connected to the T3PWM-T3CMP, T4PWM-T4CMP pins of the host chip, 3 pins are connected to 11 pins of print chip U12, 2, 5, 6, 9, 12, 15, 16 and 19 pins of print chip U12 are connected to 2, 3, 4, 5, 6, 7, 8 and 9 pins of print chip U11, 19 pins of print chip U11 are connected to ground, 1 pin is connected to 5V voltage, 20 pins are connected to 5V voltage, 18, 17, 16, 15, 14, 13, 12 and 11 pins are connected to 1, 2, 3, 4, 5, 6, 7 and 8 of print interface J2, 3, 4, 7, 8, 13, 14, 17 and 18 pins of print chip U15 are connected to EVT 2PWM-T2CMP, CAP 2-BSQEP 2, TDIRA, TRIC 1, TRIC 3, TRIC 2-T3, TRIC 3-TIOC 4 pins of the host chip U635 pins, EVPDC 4 pins of host chip, EVP 4 and EVPDC 4 pins of host chip 5, CTC 14B pins of host chip U, EVPDOC 5 pins, and EVPDRIP 4 pins of host chip 4 and CTC 4 pins of host chip, the 6 pins are connected with the 11 pins of the printing chip U15, the 2, 5, 6, 9, 12, 15, 16 and 19 pins of the printing chip U15 are respectively connected with the 2, 3, 4, 5, 6, 7, 8 and 9 pins of the printing chip U13, the 19 pins of the printing chip U13 are grounded, the 1 pin is connected with 5V voltage, the 20 pins are connected with 5V voltage, the 18, 17 and 16 pins are connected with the 9, 10 and 11 pins of the printing interface J2, and the 14, 15, 16, 17 and 33 pins of the printing interface J2 are grounded.

Further, the model of the sensor U3 is BMI160, the model of the voice chip is LD3320, the model of the print chips U12 and U15 is 74273, the model of the print chips U11 and U13 is 74HC245, and the model of the print interface J2 is CENT 36.

Further, the Wi-Fi module circuit comprises a Wi-Fi chip U16,

pins

9 and 10 of the Wi-Fi chip U16 are connected with pins SCIRXDB and SCITXDB of a main chip, pin 11 is vacant, pin 16 is connected with 3.3V, pin 17 is grounded and pin 2 of P8, pin 19 is connected with pin 1 of P8, pin 23 is connected with 3.3V, the network port module circuit comprises a network port chip U2 and an interface J1, a resistor R75 and a resistor R76 are connected in series between

pins

36 and 32 of the network port chip U2, a resistor R75 and a resistor R76 are connected with 3.3V, a first pin of the resistor R75 is connected with a pin SCIRXDA of the main chip, a second pin of the resistor R76 is connected with a pin MFSRA of the main chip,

pins

35, 34, 33 and 37 of the network port chip U38 are respectively connected with pins SCIRXDA, MDRA, mclka, PWM12, pins 30 and 5831, pin 39, pin 583, pin 39, resistor R40, resistor R9638 and a resistor R40 are connected in series, r70 and R71 are connected in series to form a second group, R73 and R74 are connected in series to form a third group, the first group, the second group and the third group are connected in parallel to form a 3.3V voltage,

pins

45, 46 and 47 of a network port chip U2 are respectively connected between R63 and R64, between R70 and R71, between R73 and R74,

pins

15, 17 and 21 are connected with a 3.3V voltage, pin 22 is connected with a 1.2V voltage,

pins

27 and 25 are connected with

pins

10 and 11 of an interface J1, pin 1 is connected with a 3.3V voltage and a2 pin of an interface J1, pin 2 is connected with a 3.3V voltage and a1 pin of an interface J1, pin 5 is connected with a6 pin of an interface J1, pin 6 is connected with a3 pin of an interface J1,

12 and 9 of an interface J5 is connected with pins R66 and R72, pin R66 and R72 are connected with a 3.3V voltage, pin SpiMAX 28, wireless modem module, chip modules 28, SPIMXA, chip modules are connected with pins 1, SPOTA 3, SPITU 9, SPITU 3, SP, the pins Y1, 8 and 14 are grounded between the

pins

9 and 10, and the 13 pin is connected in series with an inductor L1, a capacitor C5 and an antenna E1.

Furthermore, the model of the Wi-Fi chip U16 is EMW3080B, the model of the network port chip U2 is W5500, and the model of the wireless chip U1 is NRF24L 01.

Compared with the prior art, the invention has the beneficial effects that:

the system can scan the test paper in batches, warn the test paper which does not meet the requirements and exceeds the range, prompt the reader to pick out the abnormal test paper and manually recheck the abnormal test paper; the functions of stopping, continuing, shutting down and the like of the marking system under the voice control can be realized; the system adopts an SRAM circuit, so that the scanning speed and the storage speed of the system are greatly improved; the system can carry out TCP/IP communication with the PC through the wired network port and the wireless network port, thereby reducing the dependence of the system on data lines; the system can monitor the scanning speed in real time, avoid the problems of unclear test paper scanning, test paper overlapping and the like caused by too fast scanning, and also avoid the problem of scanning efficiency caused by too slow scanning of the test paper.

Description of the drawings:

FIG. 1 is an enlarged view of a partial pin of a main chip 1

FIG. 2 is an enlarged view 2 of a partial pin of a main chip

FIG. 3 shows a WiFi module circuit and a stepper motor circuit

FIG. 4 shows a USB-to-serial circuit, a memory circuit, and a display circuit

FIG. 5 is a print module circuit

FIG. 6 shows a circuit of a network interface module

FIG. 7 shows a wireless module circuit

FIG. 8 shows a camera circuit, a sensor circuit, and an alarm circuit

FIG. 9 shows a reset circuit and a voice circuit

FIG. 10 shows a PWM dimming circuit, a clock circuit, and a JTAG circuit

FIG. 11 shows a voltage divider circuit, a battery charging circuit, and an SRAM circuit

FIG. 12 shows a power filter circuit, and an LED indicator circuit

FIG. 13 shows a BOOT circuit, TYPE-C interface

FIG. 14 is a schematic view of the whole structure

The specific implementation mode is as follows:

in order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. The preferred embodiments of the present invention are shown in the drawings, but the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for descriptive purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The present invention will be described in detail with reference to the accompanying drawings.

Embodiment 1:

as shown in fig. 1-14: the stepping chip in the stepping motor circuit is connected with two windings of the stepping motor, two paths of motors are controlled through a main chip to control the in-and-out scanning speed of a test paper, the test paper is scanned by a camera circuit, scanning information is stored in a memory circuit, the main chip is communicated with a PC (personal computer) through a USB (universal serial bus) to serial port module circuit in real time, when the scanned test paper is overlapped and exceeds the answering range, the main chip controls a buzzer to be conducted, the buzzer gives an alarm, human interference can be carried out as soon as possible when abnormal data occurs at the moment, a worker speaks a key word related to stop, a voice circuit inputs an instruction through a microphone, the voice chip intelligently identifies the instruction to realize voice identification, voice control and man-machine conversation functions, an identified key word list can be dynamically edited at will, and a display circuit can check the working condition of a paper reading system through an OLED, scanning information such as answer quantity, correct quantity, error quantity and the like so that a marking person can adjust the working state of the system in time, connecting an SCIRXBD port of a main chip with a TXD0 port of a Wi-Fi chip U16, connecting an SCIRXDB port of the main chip with an RXD0 port of a Wi-Fi chip U16, resetting the Wi-Fi chip U16 through a WIFI RESET port of the Wi-Fi chip U16, communicating with a Wi-Fi module circuit through sending a serial port instruction by the main chip, and transmitting information by adopting a TCP-IP protocol so as to support the 802.11b/g/n standard.

Embodiment 2:

as shown in fig. 1-14: a stepping chip in a stepping motor circuit is connected with two windings of the stepping motor, two paths of motors are controlled through a main chip to control the in-and-out scanning speed of a test paper, a camera circuit scans the test paper, scanning information is stored in a memory circuit, the main chip is communicated with a PC (personal computer) in real time through a USB (universal serial bus) to serial port module circuit, objective question scores are obtained through software comparison for the objective question PC, a scanning picture is provided for a subjective question system to be approved by a reader, when the scanned test paper is overlapped and exceeds the answering range, the main chip controls a buzzer to be conducted, the buzzer gives an alarm, human interference can be carried out as soon as possible when abnormal data appears, a worker speaks a key word related to stop, a voice circuit inputs an instruction through a microphone, and the voice chip intelligently identifies the instruction to realize voice identification, voice control and man-machine conversation functions, the identified key word list can be edited dynamically at will, the boot circuit can enable the system to enter an editable state, the display circuit can check the working condition of the marking system in real time through an OLED display screen, the information of the number of answers, the correct number, the error number and the like is scanned, so that the marking staff can adjust the working state of the system in time, when the external light is too bright or dim, the PWM dimming circuit can adjust the brightness of the display screen, the SCIRXBD port of the main chip is connected with the TXD0 port of the Wi-Fi chip U16, the SCIRXDB port of the main chip is connected with the RXD0 port of the Wi-Fi chip U16, the WIFI RESET port of the Wi-Fi chip U16 can reset the Wi-Fi chip U16, the main chip can communicate with the Wi-Fi module circuit by sending a serial port instruction, information transmission is carried out by adopting a TCP-IP protocol, and the 802.11b/g/n standard is supported.

Claims

1. The utility model provides an artificial intelligence system of going over examination papers, its characterized in that, including controller circuit, peripheral circuit, communication circuit, main chip, BOOT circuit, power filter circuit and TYPE-C interface, BOOT circuit control main chip gets into BOOT0, BOOT1, BOOT2 and BOOT3 mode, power filter circuit provides stable +3.3V and +1.8V voltage for whole circuit, the TYPE-C interface can carry out data transfer with external equipment, the controller circuit, peripheral circuit, communication circuit passes through main chip carries out data interaction, the controller circuit gives peripheral circuit provides control signal, the controller circuit includes clock circuit, LED pilot lamp circuit, USB changes serial module circuit, battery charging circuit, bleeder circuit, SRAM circuit, JTAG circuit, reset circuit, the peripheral circuit includes step motor circuit, a little, Display circuit, memory circuit, camera circuit, warning circuit, sensor circuit, voice circuit, PWM dimming circuit, print module circuit, communication circuit includes Wi-Fi module circuit, net gape module circuit, wireless module circuit, the controller circuit peripheral hardware circuit with branch circuit that contains in the communication circuit uses main chip is integrated as the center, the controller circuit gives the peripheral hardware circuit provides control signal, control peripheral hardware circuit realizes storage, scanning, printing, dimming, demonstration, prompt facility, communication circuit passes through Wi-Fi module circuit or net gape module circuit carry out information interaction with the PC, adopts the TCP-IP agreement to carry out information transmission, supports 802.11b/g/n standard.

2. The artificial intelligence examination paper marking system of claim 1, wherein the clock circuit comprises two clock circuits, the first clock circuit comprises an 8M crystal oscillator and two 24P ceramic capacitors, the second clock circuit comprises a 30M crystal oscillator chip, two pins of the 8M crystal oscillator are connected to X1 and X2 pins of the main chip, the CLK pin of the 30M crystal oscillator chip is connected to X1 pin of the main chip, VCC is connected to 3.3V, the LED indicator lamp circuit comprises a 330 ohm current-limiting resistor and an LED lamp, the positive electrode of the LED lamp 1 is connected to 3.3V, the negative electrode of the LED lamp 2 is connected to PWM7, PWM8 and PWM9 pins of the main chip, the positive electrode of the LED lamp 2 is connected to 3.3V, the negative electrode of the LED lamp is connected to CAP5, C6TIP and TDIRD pins of the main chip, the USB switching circuit comprises a serial port U18, a USB interface and a third oscillator circuit, and the main chip PWM10 pins of the serial port U18, the serial port 3 and the main chip 10 pins are respectively connected to the USB switching circuit, TCLINB and PWM11 pins, 2 and 3 pins of the USB interface are respectively connected with 16 and 15 pins of the serial port chip U18, a crystal oscillator Y3 of the third crystal oscillator circuit is connected with 28 and 27 pins of the serial port chip U18, the battery charging circuit comprises a charging chip U7, a battery CN1 and working indicator lamps D2 and D3, a1 pin of the charging chip U7 is connected with an anode of the working indicator lamp D2 and a cathode of the working indicator lamp D3, an anode of the working indicator lamp D3 is connected with 5V voltage, a3 pin of the charging chip U7 is connected with an anode of the battery CN1 and a4 pin is connected with 5V voltage, the voltage dividing circuit comprises a power supply chip U9 and a working indicator lamp D16, pins 5 and 6 of the power supply chip U9 are connected with 5V voltage and pins 5 and 6and pin 3.3V voltage, and pins 17 and 18 of the working indicator lamp D16 are connected with 3V voltage and pins VFL 23 and 24V pin 1.8 voltage of the main chip, the SRAM circuit comprises an SRAM chip U, pins 1, 2, 3, 4, 5, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 42, 43, 44, 7, 8, 9, 10, 13, 14, 15, 16, 29, 30, 31, 32, 35, 36, 37, 38, 6, 17, 41 of the SRAM chip U are respectively connected with XA, XD, JTAG, XD, XZ6 AND, XZX, XRD pins, 39, 40, 12, 34 of the SRAM chip U are grounded, 11, 13 pins are connected with 3.3V 3, 14, 3, 14, AND 14 of the SRAM chip U is respectively connected with pins of the host chip U, AND the host chip U is connected, TDI, TDO, TCK, EMU0, TRST and EMU1 pins, wherein pins 5, 13 and 14 of the JTAG interface are connected with 3.3V voltage, pins 4, 8, 10 and 12 are grounded, the reset circuit is composed of a resistor, a capacitor and a key, and a first pin of the key is respectively connected with 3.3V voltage and an XRS pin of the main chip.

3. The artificial intelligence scoring system of claim 2, wherein the model of the main chip is TMS320F2812, the model of the serial port chip U18 is PL2303, the model of the charging chip U7 is MCP73831, the model of the power supply chip U9 is TPS767D318, and the model of the SRAM chip U8 is CY7C1041CV 33.

4. The artificial intelligence scoring system as claimed in claim 3, wherein the stepping motor circuit is controlled by a four-way optical coupling circuit through a driving chip, the PWM1 pin of the main chip is connected in series with the cathode of the LED2 and the cathode of the optical coupling TLP1 illuminator, the PWM2 pin is connected in series with the cathode of the LED3 and the cathode of the optical coupling TLP2 illuminator, the PWM3 pin is connected in series with the cathode of the LED4 and the cathode of the optical coupling TLP3 illuminator, the PWM4 pin is connected in series with the cathode of the LED5 and the cathode of the optical coupling TLP4 illuminator, 4 optical couplings are connected with 5V voltage through exclusion R-1, the cathodes of the light receivers of the optical couplings TLP1, TLP2, TLP3 and TLP4 are connected with 5, 7, 10 and 12 pins of the driving chip, the 1 pin PWMA1 is connected with the PWM6 pin of the main chip, the 2 pin is connected with 6 pin, 3 pin is connected with 5V voltage, and the 1 pin of the PWMB1 is connected with the PWM5 pin of, The pin 2 is connected with the pin 11 and the pin 3 of the driving chip to be connected with 5V voltage, the pin 2 and the pin 3 of the driving chip are respectively connected with the pin 1 and the pin 2 of the stepping motor M1, the pin 13 and the pin 14 of the stepping motor M2 to be connected with the pin 1 and the pin 2 of the stepping motor M2, the pin 9 of the driving chip is connected with 5V voltage, the pin 4 of the driving chip is connected with 12V voltage, the pin 1 and the pin 15 of the stepping motor M2 to be grounded, the display circuit comprises an OLED display screen, the pins 13, 14, 15, 18 and 19 of the OLED display screen are respectively connected with the pins XA0, XA1, XA2, XA3 and XA4 of the main chip, the pins 9 and 6 of the OLED display screen are connected with 3.3V voltage and a filter capacitor, the memory circuit comprises a memory CARD D1, the pin 1, 5, 7, 8 and 9 of the memory CARD D1 are respectively connected with the pin XD9, the pin XD10, the pin XD11, the pin XD12, the pin 3. 13, the pin, the camera circuit comprises a camera, a1 pin of the camera is connected with 3.3V voltage, a2 pin of the camera is connected with ground, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 pins of the ADCINA0, ADCINA1, ADCINA2, ADCINA3, ADCINA4, ADCINA5, ADCINA6, ADCINA7, ADCINB7, ADCINB6, ADCINB5, ADCINB4, ADCINB3, ADCINB2, ADCINB1 and ADCINB0 pins of the main chip are connected with the ADCINB0, the base of the triode Q0 is connected with the XD0 pin of the main chip, the collector is connected with 3.3V voltage, the buzzer B72, the sensor circuit comprises a triode Q0 and a buzzer B0, the XD 72 pin of the triode Q0 is connected with the XD0 pin of the main chip, the XD 363, the XD 72 and the XD 72, the XD 3.3, the XD 72 and the voltage of the main chip 72, the XD3 pin of the XD 72, the XD3 pin of the 3614, the main chip 72 and the voltage, the main chip 72 are connected with the voltage, the voice circuit comprises a voice chip U5 and a microphone Mic2, pins 41, 40, 39, 38, 37, 36, 35, 34, 42, 43, 45, 46, 47, 48, 44 and 31 of the voice chip are respectively connected with pins XA5, XA6, XA7, XA8, XA9, XA10, XA11, XA12, XA13, XA14, XA15, XA16, XA17, XA18, XD14 and XD5 of the main chip, a capacitor C5 and a first pin of the microphone Mic are sequentially connected with a pin 9 of the voice chip U5, a capacitor C5 and a second pin of the microphone are sequentially connected with a pin 10, a pin 12 is connected with the first pin of the microphone Mic, a transistor 19, 23, 7, 1 and a transistor 32 are connected with a triode 3.3V voltage, the PWM dimming circuit comprises a transistor Q5, a VCC, a dimmer lamp, a base of the VCC lamp, a base of the power supply is connected with the transistor Q5, a base of the transistor 5 and a base of the transistor 5, the collector is connected with the anode of the dimming bank light, the print module circuit comprises print chips U11, U12, U13, U15, door U14A, door U14B and print interface J2, the print chips U12 are connected with the pins T1PWM-T1CMP, CAP1-QEP1, CAP3-QEPI1, TCLKINA, C2TRIP, T1CTRIP-PDPINTA, CAP4 and CAP6 of the master chip respectively, the pins 1 and 2 of the door U14A are connected with the pins T3PWM-T3CMP, T4PWM-T4CMP of the master chip, 3 pin is connected with the pin 11 of the print chip U12, the pins 2, 5, 6, 9, 12, 15, 16 and 19 of the print chip U12 are connected with the pins 2, 3, 6, 7, 11, 19, 20, 5, 6, 9, 19 and 19 pins of the print chip U11 are connected with the voltage tube 20, V17, V, 20, V17 and V18 and V17 are connected with the voltage of the pins of the print chip, 15. 14, 13, 12, 11 pins of the printing chip U15 are connected to 1, 2, 3, 4, 5, 6, 7, 8 of the printing interface J2, 3, 4, 7, 8, 13, 14, 17 and 18 of the printing chip U15 are connected to the T2PWM-T2CMP, CAP2-QEP2, TDIRA, C1TRIP, C3TRIP, T2 CTRRIP-EVASOC, T3 CTRRIP-PDPINTB, T4 CTRRIP-EVBSOC pins of the master chip, 4 and 5 pins of the gate U14B are connected to the C4TIP and C5TIP pins of the master chip, 6 pin 11 of the printing chip U15, 2, 5, 6, 9, 12, 15, 16 and 19 pins of the printing chip U15 are connected to the 2, 3, 4, 5, 6, 7, 8 and 9 pins of the printing chip U13, 19 pin 19, 19 pin 20, 5, 10 pin 20, 9 pin 11 pin voltage of the printing chip J13 is connected to the printing interface J2, 26, 10, 9, pins 14, 15, 16, 17 and 33 of the printing interface J2 are grounded.

5. The artificial intelligence scoring system of claim 4, wherein the model number of the sensor U3 is BMI160, the model number of the voice chip is LD3320, the model numbers of the print chips U12 and U15 are 74273, the model numbers of the print chips U11 and U13 are 74HC245, and the model number of the print interface J2 is CENT 36.

6. The artificial intelligence scoring system of claim 5, wherein the Wi-Fi module circuit comprises a Wi-Fi chip U16, pins 9 and 10 of the Wi-Fi chip U16 are connected to SCIRXDB and SCITXDB pins of the main chip, pin 11 is vacant, pin 16 is connected to 3.3V, pin 17 is connected to ground and pin 2 of P8, pin 19 is connected to pin 1 of P8, and pin 23 is connected to 3.3V, the network interface module circuit comprises a network interface chip U2 and an interface J1, a resistor R75 and a resistor R76 are connected in series between pins 36 and 32 of the network interface chip U2, a 3.3V is connected between resistors R75 and R76, a first pin of the resistor R75 is connected to the SCIRXDA pin of the main chip, a second pin of the resistor R76 is connected to the MFSRA pin of the main chip, and pins 35, 34, 33, 37, 35, 34, 37, and 37 of the network interface chip 2 are connected to the txmdda pin of the main chip, The pins MCLKRA, PWM12, 30 and 31 are connected with a crystal oscillator Y2, 37 pin 3.3V voltage, 42, 41, 40, 39 and 38 pin connecting resistors, R63 and R64 are connected in series to form a first group, R70 and R71 are connected in series to form a second group, R73 and R74 are connected in series to form a third group, the first group, the second group and the third group are connected with 3.3V voltage in parallel, pins 45, 44 and 43 of the network port chip U2 are respectively connected with a node between the R63 and the R64, a node between the R70 and the R71, a node between the R73 and the R74, pins 15, 17 and 21 are connected with 3.3V voltage, a pin 22 is connected with 1.2V voltage, pins 27 and 25 are respectively connected with pins 10 and 11 of the interface 46J 48, a pin 1 pin is connected with 3.3V voltage and an interface pin 2, a pin 3.3V voltage of the interface J5, a pin 1, a pin 585, a pin 596 pin of the interface pin 599 and an interface pin 599, the voltage of 3.3V is connected between the R66 and the R72, the wireless module circuit comprises a wireless chip U1 and an antenna, pins 1, 2, 3, 4, 5 and 6 of the wireless chip U1 are respectively connected with pins CANRXA, CANTXA, SPICLKA, SPISETA, SPIMIMOA and SPIMOMIA of the main chip, pins 7 and 15 are connected with the voltage of 3.3V, pins 9 and 10 are connected with pins Y1, pins 8 and 14 are connected with the ground, and pin 13 is connected with an inductor L1, a capacitor C5 and an antenna E1 in series.

7. The artificial intelligence scoring system of claim 6, wherein the model of the Wi-Fi chip U16 is EMW3080B, the model of the portal chip U2 is W5500, and the model of the wireless chip U1 is NRF24L 01.