CN112100692A - Encryption method and encryption device for hardware module - Google Patents

Abstract

The present disclosure relates to an encryption method and an encryption device for a hardware module. The encryption method for a hardware module includes a secure memory acquiring a random number generated by the hardware module, and setting an encryption algorithm according to the random number, a key and a security code to obtain a first authentication code. The hardware module sets the encryption algorithm to obtain the second authentication code according to the random number, the key and the security code; the hardware module obtains the first authentication code, compares the first authentication code and the second authentication code, and judges whether to enter the device according to the comparison result. User program. Through the technical solution of the present disclosure, the random number is used to greatly reduce the possibility of the hardware module being cracked, increase the difficulty of the hardware module being cracked, and effectively prevent the hardware module from being imitated by a third party.

Description

A hardware module encryption method and encryption device

technical field

The present disclosure relates to the field of encryption technology, and in particular, to an encryption method and an encryption device for a hardware module.

Background technique

In the development process of hardware equipment or boards, in order to reduce development costs, a large number of general-purpose processor hardware modules are used, resulting in the appearance, device selection and layout of hardware modules that are sold in the market. At present, most of the hardware modules do not have any protection mechanism due to cost considerations, or they only have simple protection that is easy to be cracked. For experienced plagiarists, they can obtain the hardware by adding a little external detection equipment. The configuration and program data inside the module make the design of the hardware module very easy to be pirated.

In order to solve the above problem, currently, the calibration data of the corresponding hardware module can be stored in the external memory, and whether the corresponding hardware module is a genuine module or a non-original genuine module can be judged through the calibration of the data. However, because the data to be calibrated is stored in the external memory, in the configuration stage, the data is all exposed to the outside, which is easily detected by a third party through the instrument to obtain an illegal copy, and the processor cannot distinguish whether the bit stream is real data or a copy Data, illegal data can obtain the permission of the program to run further, therefore, the cost of cracking this mode is not high, and the security is limited.

SUMMARY OF THE INVENTION

In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides an encryption method and an encryption device for a hardware module, which greatly reduces the possibility of the hardware module being cracked by using random numbers, and increases the probability of the hardware module being cracked. It is difficult to effectively prevent hardware modules from being copied by third parties.

In a first aspect, the present disclosure provides an encryption method for a hardware module, including:

The secure memory acquires the random number generated by the hardware module and sets an encryption algorithm according to the random number, the key and the security code to acquire the first authentication code;

The hardware module performs the set encryption algorithm according to the random number, the key and the security code to obtain the second authentication code;

The hardware module obtains the first authentication code, compares the first authentication code and the second authentication code, and judges whether to enter the setting user program according to the comparison result.

Optionally, the hardware module compares the first authentication code and the second authentication code and judges whether to enter a user setting program according to the comparison result, including:

If the first authentication code is consistent with the second authentication code, the hardware module enters a user program.

Optionally, the hardware module compares the first authentication code and the second authentication code and judges whether to enter a user setting program according to the comparison result, including:

If the first authentication code is inconsistent with the second authentication code, the hardware module exits the program.

Optionally, before the hardware module performs the set encryption algorithm according to the random number, the key and the security code to obtain the second authentication code, the method further includes:

The hardware module acquires the key and the security code stored inside the secure memory.

Optionally, the set encryption algorithm includes a message digest algorithm or a secure hash algorithm.

In a second aspect, the present disclosure provides a hardware module encryption device, including:

a secure memory, the secure memory is connected to the hardware module through a bus;

The secure memory is used to obtain the random number generated by the hardware module through the bus and set an encryption algorithm according to the random number, the key and the security code to obtain the first authentication code;

The hardware module is configured to perform the set encryption algorithm according to the random number, the key and the security code to obtain the second authentication code, and to obtain the first authentication code through the bus, Compare the first authentication code and the second authentication code and judge whether to enter the setting user program according to the comparison result.

Optionally, the bus is a single bus.

Optionally, a signal transmission node on the bus is connected to a set power signal through an impedance element.

Optionally, the hardware module includes a field programmable logic gate array or a power supply hardware module.

Optionally, the secure memory includes a DS28E01 type chip.

Compared with the prior art, the technical solutions provided by the embodiments of the present disclosure have the following advantages:

In the encryption method and encryption device for a hardware module provided by the embodiments of the present disclosure, a secure memory is set to obtain a random number generated by the hardware module, and an encryption algorithm is set according to the random number, key and security code to obtain the first authentication code, and the hardware module is based on the random number, key and security code. The random number, the key and the security code are used to set the encryption algorithm to obtain the second authentication code. The hardware module obtains the first authentication code, compares the first authentication code and the second authentication code, and judges whether to enter the set user program key according to the comparison result. on random numbers. In this way, the embodiment of the present disclosure dynamically transmits random numbers between the secure memory and the hardware module, and the use of random numbers greatly reduces the possibility of the hardware module being cracked, and can effectively ensure that the imitated hardware can be simulated without the authorization of the manufacturer. If the module cannot work normally, the hardware module can work normally only after the authorization of the manufacturer and the authentication of the software algorithm between the hardware module and the carrier board, which increases the difficulty of cracking the hardware module and effectively prevents the hardware module from being copied by third parties.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the accompanying drawings that are required to be used in the description of the embodiments or the prior art will be briefly introduced below. In other words, on the premise of no creative labor, other drawings can also be obtained from these drawings.

1 is a schematic flowchart of a method for encrypting a hardware module according to an embodiment of the present disclosure;

2 is a schematic diagram of data transmission between a secure memory and a hardware module according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a hardware module encryption device according to an embodiment of the present disclosure.

Detailed ways

In order to more clearly understand the above objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments may be combined with each other under the condition of no conflict.

Many specific details are set forth in the following description to facilitate a full understanding of the present disclosure, but the present disclosure can also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, and Not all examples.

FIG. 1 is a schematic flowchart of a method for encrypting a hardware module according to an embodiment of the present disclosure. The encryption method for a hardware module can be applied to an application scenario where the hardware module needs to be encrypted, and can be executed by the encryption device for a hardware module provided by the embodiment of the present disclosure. As shown in Figure 1, the encryption method of the hardware module includes:

S110, the secure memory acquires the random number generated by the hardware module and sets an encryption algorithm according to the random number, the key and the security code to acquire the first authentication code.

FIG. 2 is a schematic diagram of data transmission between a secure memory and a hardware module according to an embodiment of the present disclosure. As shown in Figure 2, the hardware module 1 generates random numbers. The hardware module 1 may contain a random number generator for generating random numbers. The hardware module 1 and the secure memory 2 are electrically connected. The random number is transferred to secure memory 2.

Security code refers to the ROM (Read Only Memory) ID of the security memory, also known as the identification code. The security code of the security memory is set when it leaves the factory. The length of the ROMID of each security memory is 64 bits and is unique. . The key refers to the parameters input in the algorithm of converting plaintext to ciphertext or converting ciphertext to plaintext, that is, the secret information used to complete cryptographic applications such as encryption, decryption or integrity verification. A unique security code is stored in the secure memory 2, and the key can be obtained by using the master key and the unique security code stored in the secure memory 2, that is, using a certain non-specific algorithm, or combining the ROM ID of the secure memory to generate 8 Byte key.

After acquiring the random number generated by the hardware module 1, the secure memory 2 sets the encryption algorithm according to the random number, the key and the security code to obtain the first authentication code C1. Exemplarily, the set encryption algorithm may be a message digest algorithm, namely the MD5 (Message Digest Algorithm 5) algorithm, the message digest algorithm is one of the hash algorithms widely used by computers, and it is a hash algorithm to operate the data into another fixed-length value. The basic principle is often used for file verification. No matter how large the file is, a unique message digest value can be generated after the message digest algorithm. The message digest algorithm is to allow a large amount of information to be compressed into a confidential format before signing the private key with digital signature software, that is, to convert a string of bytes of arbitrary length into a string of hexadecimal digits of a certain length. The information digest algorithm has the characteristics of fixed length of the message digest value, easy calculation and strong resistance to modification.

Exemplarily, the set encryption algorithm may also be a secure hash algorithm, namely the SHA (Secure HashAlgorithm) algorithm, also known as a secure hash algorithm, which is mainly applicable to the digital signature algorithm ( DSA, Digital Signature Algorithm). The secure hash algorithm is to receive a piece of plaintext, and then convert it into a piece of ciphertext in an irreversible way. The fixed output sequence is the hash value, the process of message digest or message authentication code.

The secure memory 2 can obtain the unique first authentication code C1 by performing the information digest algorithm according to the random number, the key and the security code, and the secure memory 2 can also obtain the unique first authentication code C1 by performing the secure hash algorithm according to the random number, the key and the security code. For the authentication code C1, the process of obtaining the first authentication code C1 from a random number, a key and a security code through an information digest algorithm or a secure hash algorithm is well known to those skilled in the art, and will not be discussed here.

S120, the hardware module sets the encryption algorithm according to the random number, the key and the security code to obtain the second authentication code.

Optionally, as shown in FIG. 2, before the hardware module 1 sets the encryption algorithm according to the random number, the key and the security code to obtain the second authentication code C2, the hardware module 1 can be set to obtain the password stored in the secure memory 2. key and security code.

Specifically, the secure memory 2 internally stores a key and a security code, and the secure memory 2 has an electrical connection with the hardware module 1. The secure memory 2 sends the internally stored key and security code to the hardware module 1, and the hardware module 1 After acquiring the key and the security code stored in the secure memory 2, use the random number generated by itself to set the encryption algorithm according to the random number, the key and the security code to obtain the second authentication code C2.

Exemplarily, the set encryption algorithm can also be an information digest algorithm or a secure hash algorithm. Similarly, the hardware module 1 can obtain a unique second authentication code C2 by performing the message digest algorithm according to the random number, the key and the security code. Module 1 can also obtain a unique second authentication code C2 by performing a secure hash algorithm according to the random number, key and security code, and obtains the second authentication code from the random number, key and security code through the message digest algorithm or the secure hash algorithm The process of C2 is well known to those skilled in the art and will not be discussed here.

It should be noted that the set encryption algorithm used by the secure memory 2 is the same as the set encryption algorithm used by the hardware module 1, and both may use an information digest algorithm, or both may use a secure hash algorithm.

S130, the hardware module obtains the first authentication code, compares the first authentication code and the second authentication code, and judges whether to enter the setting user program according to the comparison result.

Specifically, as shown in FIG. 2 , there is an electrical connection between the hardware module 1 and the secure memory 2 , and the hardware module 1 can obtain the first authentication code C1 generated by the secure memory 2 and use the first authentication code generated by the secure memory 2 C1 is compared with the second authentication code C2 generated by the hardware module 1 itself, and according to the comparison result, it is judged whether to enter the setting user program.

Optionally, the hardware module 1 compares the first authentication code C1 and the second authentication code C2 and judges whether to enter the setting user program according to the comparison result. It can be set that if the first authentication code C1 and the second authentication code C2 are consistent, the hardware module 1 Enter the user program. If the first authentication code C1 is inconsistent with the second authentication code C2, the hardware module 1 exits the program.

Specifically, since the hardware module 1 can transmit the generated random number to the secure memory 2, if the hardware module 1 is in a normal state, since the first authentication code C1 obtained by the secure memory 2 is a random number, a key and a security code that have been set The second authentication code C2 obtained by the hardware module 1 is obtained by the same random number, the same key and the same security code through the same set encryption algorithm, so the first authentication code C1 and the The two authentication codes C2 are the same. Therefore, if the first authentication code C1 is consistent with the second authentication code C2, it means that the hardware module 1 is in a normal state. At this time, the hardware module 1 enters the user program, that is, the hardware module 1 passes the authentication.

If there is a third-party malicious detection hardware module 1, and the third party cannot obtain the random number generated by the hardware module 1, the authentication code obtained by the third party based on different random numbers is likely to be inconsistent with the first authentication code C1. Therefore, if If the first authentication code C1 is inconsistent with the second authentication code C2, it means that there is a third-party malicious detection hardware module 1. At this time, the hardware module 1 exits the user program, and the hardware module 1 can also perform other operations instead of normal work. Module 1 certification failed.

At present, the hardware module either has no protection mechanism, or is simply verified by calculating and comparing the preset value. Generally, there is a unique serial number inside the hardware module, that is, the device ID. The device ID is built-in when the hardware module leaves the factory. inside the hardware module. According to the unique ID serial number, combined with the relevant encryption algorithm and the external memory chip, the encryption protection of the hardware module can be realized. After the hardware module is powered on, first enter the encryption program through the boot program, the encryption program reads the unique ID preset in the hardware module by the manufacturer, calculates a comparison value through a specific algorithm, and then reads the external memory, such as external FLASH ( The preset comparison value stored in a specific location in the flash memory), whether the comparison between the two is consistent. If they are consistent, it means that the hardware module is a genuine module from the manufacturer; if they are inconsistent, it means that the hardware module is damaged or not produced by the original factory, and the module will power off the system.

However, because the data to be calibrated is stored in the external memory, in the configuration stage, the data is exposed to the outside, and it is easy for a third party to obtain an illegal copy through the instrument detection, and the processor cannot distinguish whether the bit stream is real data or copied data, so illegal The data can obtain the permission of the program to run further, so the cost of cracking this mode is not high, and the security is limited. That is to say, an obvious shortcoming of the prior art is that once the ID of the hardware module is read externally, the external device can disguise as the processor and communicate with the FLASH to obtain the trust of the system.

In the embodiment of the present disclosure, after the hardware module 1 is powered on, the hardware module 1 starts from the default external configuration and enters the authentication procedure. The authentication procedure of the hardware module 1 generates a random number and sends it to the secure memory 2, and the secure memory 2 according to the random number , the built-in key and the unique security code are set to the encryption algorithm to obtain the first authentication code C1, the hardware module 1 authentication program obtains the second authentication code C2 through the same input and the same set encryption algorithm, the hardware module 1 authentication program The first authentication code C1 and the second authentication code C2 are compared.

If the first authentication code C1 is consistent with the second authentication code C2, it means that the hardware module 1 is in a normal state, and the hardware module 1 enters the user program at this time, that is, the hardware module 1 passes the authentication. If there is a third-party malicious detection hardware module 1, and the third party cannot obtain the random number generated by the hardware module 1, the authentication code obtained by the third-party random number is likely to be inconsistent with the first authentication code C1. Therefore, if If the first authentication code C1 is inconsistent with the second authentication code C2, it means that there is a third-party malicious detection hardware module 1. At this time, the hardware module 1 exits the user program, and the hardware module 1 can also perform other operations instead of normal work. Module 1 certification failed. In this way, the embodiment of the present disclosure dynamically transmits random numbers between the secure memory 2 and the hardware module 1, and the use of random numbers greatly reduces the possibility of the hardware module 1 being cracked, and can effectively ensure that imitation without the authorization of the manufacturer can be achieved. The output hardware module 1 cannot work normally. Only after the authorization of the manufacturer and the authentication of the software algorithm between the hardware module 1 and the carrier board, the hardware module 1 can work normally, which increases the difficulty of cracking the hardware module 1 and effectively prevents the hardware Module 1 is copied by a third party.

An embodiment of the present disclosure further provides an encryption device of a hardware module. FIG. 3 is a schematic structural diagram of an encryption device of a hardware module provided by an embodiment of the present disclosure. With reference to FIG. 2 and FIG. 3 , the encryption device of the hardware module includes a secure memory 2 , and the secure memory 2 is connected to the hardware module 1 through a bus 3 . Exemplarily, the bus 3 can be a single bus. The single bus is a peripheral serial expansion bus technology. A single signal line is used to transmit both the clock and the data, and the data is transmitted in both directions. The single bus is used to realize the secure memory 2 and the hardware module 1. On the basis of realizing the data transmission between the security memory 2 and the hardware module 1, the connection between the hardware modules 1 and the security memory 2 is effectively simplified.

The secure memory 2 is used to obtain the random number generated by the hardware module 1 through the bus 3 and set an encryption algorithm according to the random number, the key and the security code to obtain the first authentication code C1, and the hardware module 1 is used to obtain the first authentication code C1 according to the random number, the key and the security code. Set the encryption algorithm with the security code to obtain the second authentication code C2, and use the bus 3 to obtain the first authentication code C1, compare the first authentication code C1 and the second authentication code C2, and judge whether to enter the setting according to the comparison result. user program.

Specifically, after the hardware module 1 is powered on, the hardware module 1 starts from the default external configuration and enters the authentication procedure. The authentication procedure of the hardware module 1 generates a random number and sends the random number to the secure memory 2 through the bus. The secure memory 2 according to the The random number, the built-in key and the unique security code are set with an encryption algorithm to obtain the first authentication code C1, and the hardware module 1 also obtains the key and security code stored in the secure memory 2 through the bus and the first authentication code generated by the secure memory 2. An authentication code C1, the hardware module 1 authentication program obtains the second authentication code C2 through the same input and the same set encryption algorithm, and the hardware module 1 authentication program compares the first authentication code C1 and the second authentication code C2.

If the first authentication code C1 is consistent with the second authentication code C2, it means that the hardware module 1 is in a normal state, and the hardware module 1 enters the user program at this time, that is, the hardware module 1 passes the authentication. If there is a third-party malicious detection hardware module 1, and the third party cannot obtain the random number generated by the hardware module 1, the authentication code obtained by the third-party random number is likely to be inconsistent with the first authentication code C1. , if the first authentication code C1 is inconsistent with the second authentication code C2, it means that there is a third-party malicious detection hardware module 1. At this time, the hardware module 1 exits the user program, and the hardware module 1 can also perform other operations instead of normal work. At this time, the hardware module 1 certification failed.

In this way, the embodiment of the present disclosure utilizes a single bus with a relatively simple connection relationship to dynamically transmit random numbers between the secure memory 2 and the hardware module 1, and the use of random numbers greatly reduces the possibility of the hardware module 1 being cracked, and can effectively ensure that in the future With the authorization of the manufacturer, the imitated hardware module 1 cannot work normally. Only after the authorization of the manufacturer and the authentication of the software algorithm between the hardware module 1 and the carrier board, the hardware module 1 can work normally, thus adding the hardware module 1. The difficulty of being cracked can effectively prevent the hardware module 1 from being copied by a third party.

Optionally, as shown in FIG. 3 , the signal transmission node N on the bus 3 can access the set power signal through the impedance element R1 . Specifically, the signal transmission node N on the bus 3 is a node at any position on the bus 3 connecting the secure memory 2 and the hardware module 1. The set power supply signal can be, for example, the positive power supply signal VDD, and the signal transmission node N on the bus 3 The impedance element R1 is connected to the set power supply signal VDD to form an open-drain configuration, and the impedance element R1 forms a pull-up element, so that the working voltages of the safety memory 2 and the hardware module 1 are consistent, and the working voltages of the safety memory 2 and the hardware module 1 are balanced. , to ensure normal communication between the secure memory 2 and the hardware module 1.

Exemplarily, the hardware module 1 may include a field programmable logic gate array, that is, the hardware module 1 may include an FPGA (Field Programmable Gate Array), such as an FPGA that can be produced by Xilinx. Exemplarily, the hardware module 1 may also include a power supply hardware module, which uses random numbers to encrypt the power supply hardware module, reduces the possibility of the power supply hardware module being cracked, and effectively prevents the power supply hardware module from being imitated by a third party.

Illustratively, the secure memory 2 may comprise a DS28E01 type chip. The DS28E01 type chip is a 128-byte user memory, which can be used for keys that are operated inside the chip but cannot be read from the outside, and a unique and unchangeable security code. Using the DS28E01 type chip as a security memory 2 can be used for encryption at lower hardware modules 1 On the basis of the cost, the possibility of the hardware module 1 being cracked is further reduced, and the hardware module 1 is effectively prevented from being copied by a third party.

In the embodiment of the present disclosure, a single bus with a relatively simple connection relationship is used to dynamically transmit random numbers between the secure memory 2 and the hardware module 1, and the use of random numbers greatly reduces the possibility of the hardware module 1 being cracked, and can effectively ensure that the In the case of authorization, the imitated hardware module 1 cannot work normally. Only after the authorization of the manufacturer and the authentication of the software algorithm between the hardware module 1 and the carrier board, the hardware module 1 can work normally, thus increasing the hardware module 1 is cracked. It can effectively prevent the hardware module 1 from being copied by a third party.

It should be noted that, in this document, relational terms such as "first" and "second" etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these Any such actual relationship or sequence exists between entities or operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, article, or device that includes the element.

The above are only specific embodiments of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not to be limited to the embodiments herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method for encrypting a hardware module, comprising:

the secure memory acquires a random number generated by the hardware module and sets an encryption algorithm according to the random number, the secret key and the secure code to acquire a first authentication code;

the hardware module carries out the set encryption algorithm according to the random number, the secret key and the security code to obtain a second authentication code;

and the hardware module acquires the first authentication code, compares the first authentication code with the second authentication code and judges whether to enter a set user program according to a comparison result.

2. The method for encrypting the hardware module according to claim 1, wherein the hardware module compares the first authentication code with the second authentication code and determines whether to enter a set user program according to the comparison result, comprising:

and if the first authentication code is consistent with the second authentication code, the hardware module enters a user program.

3. The method for encrypting the hardware module according to claim 1, wherein the hardware module compares the first authentication code with the second authentication code and determines whether to enter a set user program according to the comparison result, comprising:

and if the first authentication code is not consistent with the second authentication code, the hardware module exits the program.

4. The method for encrypting the hardware module according to claim 1, before the hardware module performs the encryption algorithm according to the random number, the secret key and the security code to obtain a second authentication code, further comprising:

the hardware module obtains the secret key and the security code stored in the security memory.

5. The hardware module encryption method of claim 1, wherein the configured encryption algorithm comprises a message digest algorithm or a secure hash algorithm.

6. An encryption apparatus for a hardware module, comprising:

the safety memory is connected with the hardware module through a bus;

the secure memory is used for acquiring a random number generated by the hardware module through the bus and setting an encryption algorithm according to the random number, the secret key and the secure code to acquire a first authentication code;

the hardware module is used for setting an encryption algorithm according to the random number, the secret key and the security code to obtain a second authentication code, obtaining the first authentication code through the bus, comparing the first authentication code with the second authentication code and judging whether to enter a set user program according to a comparison result.

7. The hardware module encryption device of claim 6, wherein the bus is a single bus.

8. The hardware module encryption device of claim 7, wherein the signal transmission node on the bus is connected to the set power signal through an impedance element.

9. The hardware module encryption apparatus of claim 6, wherein the hardware module comprises a field programmable gate array or a power supply hardware module.

10. The hardware module encryption apparatus of claim 6, wherein said secure memory comprises a DS28E01 model chip.

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