CN112099389B - Uplink and downlink front-end machine synchronous acquisition method and system based on 1PPS - Google Patents
Uplink and downlink front-end machine synchronous acquisition method and system based on 1PPS Download PDFInfo
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Abstract
The invention discloses a synchronous acquisition method and a synchronous acquisition system for an uplink front-end machine and a downlink front-end machine based on 1PPS (packet per second), aiming at enabling uplink data streams and downlink data streams to have the same time reference, namely starting at the same T0 moment. The time system equipment provides the system with 10MHz frequency scale and 1PPS second pulse signals, which are generated by an atomic clock and GPS co-vision receiver in a station, and the time delay difference between the signals is consistent and measurable during observation. Based on the method, firstly, the working clocks of the downlink data AD conversion module and the uplink data DA conversion module are ensured to be homologous, the 10MHz frequency scale is subjected to phase locking generation by the frequency synthesizer, and then 1PPS is used as a trigger signal of AD and DA starting time, so that synchronous starting can be realized. The method and the device do not depend on a high-performance special signal acquisition and processing board, the synchronous acquisition precision is superior to 0.06ns, and synchronous acquisition of the uplink and downlink front-end machines of the virtual measurement and control integrated baseband is realized.
Description
Technical Field
The invention relates to the technical field of aerospace measurement and control, in particular to a synchronous acquisition method and system for uplink and downlink front-end machines based on 1 PPS.
Background
With the rapid development of aerospace technologies represented by satellite engineering, manned aerospace, lunar exploration engineering and the like, aerospace tasks are increasingly complex, and aerospace measurement and control systems face more and more challenges. Different space missions put different demands on space measurement and control systems, the space measurement and control systems are more and more complex in function, and a method for forming a measurement and control integrated baseband processing platform by taking a software radio processing technology as a core is formed so as to adapt to different demands of various measurement and control missions. The method has satisfactorily completed important space flight measurement and control tasks such as manned space flight and the like at present, and makes a great contribution to the development of the space flight measurement and control business in China. But still has the problems of software customization along with hardware, close coupling of software and hardware, solidified function and performance after the system is developed. The system has the advantages that most measurement and control systems are 'one model, leave factory and have life-long', some new algorithms and new technologies are difficult to absorb and utilize quickly, the performance of the system is difficult to promote, the functions are difficult to expand, the types and the spectrum of various measurement and control systems are complex, the daily maintenance is difficult, and the deployment and the upgrade in wartime are slow.
Therefore, the flexibility, the generalization and the standard of the measurement and control signal comprehensive baseband processing platform are improved, and the development direction of a future measurement and control system is provided.
At present, the rapid development of computer technology and the great improvement of the performance of a general computer are realized, a radio technology realized based on the general high-performance computer is a development trend of software radio idealization, the technology is a new technology and a new method for realizing the software radio by fully utilizing general computer resources from the perspective of a computer system, and is called as a virtual radio technology, the technology can effectively solve the problems of high development cost, poor flexibility and universality and the like of the existing measurement and control comprehensive baseband equipment, and is more suitable for the development requirements of the future measurement and control system function synthesis, equipment generalization and interface standardization.
The important differences between the radio technology implemented on the basis of a general-purpose high-performance computer and the conventional software radio are: the technology does not utilize special digital hardware (FPGA and DSP chips) controlled by software, but utilizes general computer resources to realize the functions of equipment, the design and development of the system are more convenient and faster, and the system is easier to update and upgrade.
Compared with the software radio measurement and control integrated baseband based on a special digital hardware platform, the virtual radio measurement and control integrated baseband based on the general computer platform better realizes generalization and standardization on two layers of system hardware and software. The virtual radio measurement and control integrated baseband has greater advantages in the aspects of recombination, flexibility and universality, can more effectively utilize the goods shelf products of the general computer, and brings convenience for development, remote control, maintenance guarantee, upgrading and reconstruction of a measurement and control system. The virtual radio measurement and control integrated baseband is the development and supplement of the existing software radio integrated baseband, and the characteristics and advantages of the virtual radio measurement and control integrated baseband can meet the requirements of measurement and control technology development and future aerospace application.
(1) Application requirement for rapid upgrading and deployment of future aerospace measurement and control equipment
The space flight measurement and control system is used as a guarantee system of the space aircraft and is responsible for measurement and control tasks of various space aircraft. In the future, the aerospace measurement and control system must have the capabilities of rapid station building, rapid repair and rapid guarantee. The integrated baseband is used as a core component part in the aerospace measurement and control system and must have the capacity, which brings new requirements and challenges for the development of future integrated baseband equipment. Meanwhile, under the traction of the requirement of the aerospace engineering on the diversity and flexibility of the measurement and control system, the standard and the technology of the aerospace measurement and control system are continuously developed in recent years and have the characteristics of multiple types, new technology and fast change of the requirement, the development period of the aerospace measurement and control system is shortened, the frequency of system upgrading and modification is increased, and the reserve, the management and the supplement of spare parts for maintenance have a complicated trend, so that higher requirements are provided for the deployment guarantee, the upgrading and the maintenance of aerospace measurement and control equipment including a comprehensive baseband.
(2) Meet the requirements of the aerospace measurement and control system and the technical development
The virtual measurement and control integrated baseband device takes a general computer as a processing platform, and utilizes shelf type products and general software development resources to the maximum extent, so that the generalization and standardization of software and hardware of the measurement and control device are realized. The essence of the realization of the functional software of the virtual measurement and control integrated baseband equipment enables the aerospace measurement and control system to adopt a 'soft means' to improve the system performance, and to use complex algorithm software to exchange the processing precision, and to invest more high-performance general calculations to exchange the processing capacity. The cost for development, use, maintenance and upgrade of the measurement and control system can be effectively reduced, and more and better measurement and control services are provided. Due to the software of the equipment functions, the measurement and control system can expand the application of the measurement and control system and can realize related services by replacing corresponding functional software, and the utilization of the measurement and control system is greatly improved. The software integrated baseband platform based on the general computer adopts a 'cordwood' recombination mode of a software module, can flexibly realize the measurement and control functions of different systems and types, and ensures that the measurement and control system can quickly adapt to the requirement of the development of the space mission. By using the flexibility of software module design and development, the development and upgrading period of the measurement and control system can be shortened, and the development of new technology, application of new standards and international cooperation in the measurement and control field is facilitated. By utilizing the upgradability of the software module, the upgrading and the expansion of the system functions can be quickly realized on the basis of the original measurement and control system.
Therefore, in order to meet the development requirements of future measurement and control system function integration, equipment generalization and interface standardization, the virtual radio technology is urgently required to be fused with the development trend of the aerospace measurement and control system. A measurement and control comprehensive processing platform based on a general computer is constructed by utilizing a virtual radio technology, and a measurement and control system is formed by an antenna, a digital interface, the general computer and software. The measurement and control integrated baseband based on the virtual radio technology can realize a system irrelevant to a hardware platform, and the generalization and standardization level of the measurement and control integrated baseband is improved.
The system composition of the virtual measurement and control integrated baseband system is shown in fig. 1.
As shown in fig. 1, the virtual measurement and control integrated baseband is composed of a front-end machine, a processing node, a service node, a monitoring node, a user application node, a network time service server and a network switch, and realizes interaction of high-speed and low-speed data streams by taking the network switch as a center. The virtual measurement and control integrated baseband processes digitized measurement and control signals, and an interface between a digital processing system and the analog measurement and control signals needs to be designed. The virtual measurement and control integrated baseband respectively utilizes a downlink front-end machine and an uplink front-end machine to realize uplink and downlink interfaces of data, wherein the uplink front-end machine is inserted with a DA card and mainly responsible for receiving data flow of an uplink signal processing node through a high-speed network, transmitting the data flow through a PCI-e bus, sending the data flow to the DA card to complete digital-to-analog conversion, and sending the data flow to an uplink channel; the downlink front-end machine is inserted with an AD card and is mainly responsible for receiving intermediate frequency signals sent by a downlink channel, completing analog-to-digital conversion, and sending acquired data to a downlink signal processing node through a PCI-e bus and a high-speed network; the processing node completes the function of measuring and controlling signal processing; the monitoring node is responsible for sending control commands, monitoring the state of each node, processing results and the like; the user application node is responsible for the deployment, configuration and management of the functions of the whole system; the network time service server provides 10MHz frequency scale, 1PPS synchronous signal and GPS time service.
The front-end machine is an interface for analog and digital conversion of a measurement and control signal, which directly affects measurement and control performance and reliability, and one of key technologies to be overcome is how to realize synchronous acquisition of uplink and downlink signals, so that the downlink signal received by the measurement and control comprehensive baseband and the transmitted uplink signal keep strict time synchronization, and the measurement and control system is ensured to measure distance and speed and meet the precision requirement.
The traditional measurement and control integrated baseband adopts a specially developed signal acquisition and processing board to complete the acquisition and signal processing of uplink and downlink signals, and the schematic block diagram of the traditional measurement and control integrated baseband is shown in fig. 2. The signal acquisition and processing board mainly comprises an AD chip, a DA chip, a frequency synthesis chip and a high-performance FPGA chip, and interacts commands, parameters, state data and the like with upper computer application software through a computer bus (such as a PCI-e bus). The frequency synthesizer provides acquisition clocks for the AD chip and the DA chip, and the AD acquisition clock and the DA acquisition clock are guaranteed to be homologous. The FPGA chip generally adopts a model chip with strong performance in the industry, and can independently complete the uplink and downlink signal processing functions. Because the uplink and downlink signal processing modules in the FPGA are in one FPGA, the traditional measurement and control integrated baseband can easily realize the synchronous processing of the uplink and downlink signals.
Compared with the traditional measurement and control integrated baseband, the virtual measurement and control integrated baseband adopts the universal server and the universal signal acquisition card to complete the acquisition and signal processing of uplink and downlink signals. As the goods shelf type products are adopted, compared with the traditional measurement and control integrated base band, the system has the advantages of being rapid in deployment, good in upgrading and maintenance performance and the like. However, as can be seen from the structure of the virtual measurement and control integrated baseband system shown in fig. 1, the virtual measurement and control integrated baseband system respectively collects uplink signals and downlink signals by using an uplink front-end machine and a downlink front-end machine, and a general acquisition card on the front-end machine is not responsible for signal processing tasks, but interacts data with uplink and downlink signal processing nodes by using a PCI-e bus, and the signal processing functions are completed by the signal processing nodes. Therefore, the problem to be solved by the virtual measurement and control integrated baseband is how to realize the synchronous acquisition of the uplink and downlink front-end machines. Firstly, the influence of synchronous acquisition time delay of uplink and downlink signals on the ranging performance is analyzed.
By analyzing the influence of the uplink and downlink signal synchronous acquisition time delay on the ranging performance, the necessity of researching the uplink and downlink signal synchronous acquisition method can be further pointed out.
According to the ranging principle, the baseband terminal measures the link delay by comparing the uplink transmitting signal phase and the downlink receiving signal phase at the same time, and then calculates the distance. Fig. 3 shows a schematic diagram of the principle of sidetone ranging.
In the figure: tau isRangeFor spatial geometric time delay, τUplinkFor uplink analogue link delay, tauDownlinkAnd simulating the time delay of the link for the downlink. The purpose of the method for synchronously starting the uplink data stream and the downlink data stream is to enable the uplink data stream and the downlink data stream to have the same time reference. Suppose DA and AD should start at the same time T0, and DA actually starts at the time T0+ TDAThe actual starting time of AD is T0+ tauAD，τDAI.e. start-up delay, tau, for the upstream data streamADI.e. the start-up delay of the downstream. Setting the difference of synchronous time delay of up and down lines as tauSyncThen there is τSync＝τAD-τDA. Let DA send the first data phase as
The first data phase of AD reception is
The sidetone frequency is f. For simplicity of analysis, phase ambiguity is not considered here (in practice, phase ambiguity can be resolved by a round-robin articulation mechanismFuzzy), then there are
In the formula: tau isAllI.e. the measured link delay, which includes the space geometric delay tauRangeAnd device time delay τInsIs provided with
From the formula (2), in order to obtain τRangeMust eliminate tauIns. Tau after starting AD and DA under the condition of constant working environment and temperatureInsIs fixed and can be eliminated by a calibration method, such as calibration by a calibration tower. At tauInsIn, tauUplinkAnd τDownlinkCan be considered fixed and of small value, and τSyncThe following problems may exist:
1. if the synchronous starting mechanism of AD and DA is not designed reasonably, tauSyncThe value may be large. E.g. tauSync1ms, the resulting link distance is 300km, which cannot be corrected by current calibration towers, hence τSyncThe value must be as small as possible;
2. if after each activation of AD and DA, τSyncThe value is not fixed. Then in one task, τInsAfter calibration, if abnormal conditions are met, calibration needs to be carried out again after the AD and the DA are restarted, and precious observation time is occupied.
In summary, τ is a high-precision measurement systemSyncIt should be as small as possible and kept fixed every time acquisition is started to ensure that the device has a stable time delay zero value. In addition, τSyncThe value is kept fixed, so that the problem of abnormal time delay change can be quickly found, and the method is an effective means for checking the state of the equipment. Therefore, it is necessary to research a synchronous acquisition method to ensure the uplink and downlink synchronous delay difference τ after each startSyncIs a fixed value andthe value is small.
Disclosure of Invention
In view of this, the invention provides a method and a system for synchronously acquiring uplink and downlink front-end machines based on 1PPS, which can realize the synchronous acquisition of the uplink and downlink front-end machines of the virtual measurement and control integrated baseband, and the synchronous acquisition precision is higher and is better than 0.06 ns.
In order to achieve the purpose, the technical scheme of the invention is as follows: the synchronous acquisition method of the uplink and downlink front-end machines based on 1PPS comprises the synchronous acquisition process of downlink data streams by the downlink front-end machines and the synchronous acquisition process of uplink data streams by the uplink front-end machines.
The synchronous acquisition process of the downlink data stream comprises the following steps:
setting appointed synchronous acquisition starting time as T0Time of day, and setting a synchronization enable start time ratio T0Δ seconds ahead; and carrying out network time service on the downlink front-end machine.
Setting a first synchronous starting signal for controlling the write enable of the FIFO of the first FPGA chip; setting the first synchronous starting signal to be invalid initially, setting a register in the first FPGA chip to store the first synchronous starting signal, and setting the FIFO write enable of the first FPGA chip to be invalid when the first synchronous starting is invalid, and setting the first FPGA chip for processing the downlink data stream to be in a reset state.
At T0The first sync enable signal is asserted a second before the time.
The synchronization start signal becomes active at the rising edge of the 1 st 1PPS pulse signal after the first synchronization enable signal is active.
And when the synchronous starting signal is effective, the downlink data stream enters the first FPGA chip for subsequent processing of the downlink data stream through analog-to-digital conversion.
The synchronous acquisition process of the uplink data stream comprises the following steps:
carrying out network time service on the uplink front-end machine; and the uplink processing node generates uplink data and sends the uplink data stream to the FIFO of the second FPGA chip until a link from the uplink processing node to the second FPGA chip is in a blocking state, and then the link is set to be in a waiting state.
Setting a second synchronous starting signal for controlling FIFO read enabling of a second FPGA chip; and when the second synchronous starting signal is invalid, setting the FIFO read enable of the second FPGA chip to be invalid, and setting the second FPGA chip for storing the uplink data stream to be in a working state.
At T0The second sync enable signal is asserted a second before the time.
The second synchronization start signal becomes active at a rising edge of the 1 st 1PPS pulse signal after the second synchronization enable signal is active.
And when the second synchronous starting signal is effective, the uplink data flow in the second FPGA chip executes digital-to-analog conversion and subsequent uplink processing.
Therefore, a synchronous starting mechanism of the uplink data stream and the downlink data stream is realized.
Further, setting the sync enable start time ratio T0The advance is Δ seconds, specifically the set sync enable start time is advanced by 0.5 seconds.
Another embodiment of the present invention further provides a system for synchronously acquiring uplink and downlink front-end machines based on 1PPS, wherein the system includes: the system comprises an uplink front-end machine, a downlink front-end machine, an uplink signal processing node and a downlink signal processing node.
The downlink front-end machine is connected with the downlink signal processing node through a network; the downlink front-end computer is provided with downlink application software, a downlink data AD conversion module and a first FPGA chip.
The uplink front-end machine is connected with the uplink signal processing node through a network; the uplink front-end computer is provided with uplink application software, an uplink data DA conversion module and a second FPGA chip.
The 1PPS pulse signal is sent to a first FPGA chip for triggering a first synchronous starting signal, and the 1PPS pulse signal is sent to a second FPGA chip for triggering a second synchronous starting signal; the initial states of the first synchronous starting signal and the second synchronous starting signal are both invalid.
The downlink data AD conversion module is provided with a downlink data input interface and a downlink AD conversion data output interface, downlink data flow enters the downlink data AD conversion module through the downlink data input interface, downlink AD conversion data are obtained after AD conversion, and the downlink AD conversion data are output through the downlink AD conversion data output interface.
The downlink AD conversion data output interface is connected to the first FPGA chip.
The first FPGA chip sets a first synchronous starting signal in the form of a register flag bit, and the first synchronous starting signal is invalid initially; when the first synchronous starting signal is invalid, the first FPGA chip is in a reset state, and FIFO write enable of the first FPGA chip is set to be invalid.
Before the synchronous acquisition starts, the downlink front-end machine utilizes the NTP network time service server to carry out network time service.
The downlink application software is used for carrying out network time service on the downlink front-end machine; downstream application software, also for use at T0Setting a first synchronous enabling signal in the first FPGA chip to be effective delta seconds before the moment, wherein the first synchronous enabling signal exists in the first FPGA chip in a register mode.
The first FPGA chip is used for setting the first synchronous starting signal to be effective at the rising edge of the 1 st 1PPS pulse signal after the effective signal in the first synchronization; when the first synchronous starting signal is effective, the FIFO write enable of the first FPGA chip is effective, the first FPGA chip receives downlink AD conversion data, and the downlink AD conversion data enter the first FPGA chip to execute a subsequent downlink data processing process.
Before synchronous acquisition begins, an uplink front-end machine utilizes an NTP network time service server to carry out network time service;
the uplink application software is used for carrying out network time service on the uplink front-end machine; uplink application software, also for use at T0And setting a second synchronous enabling signal in the second FPGA chip to be effective delta seconds before the moment, wherein the second synchronous enabling signal exists in the first FPGA chip in a register mode.
And the second FPGA chip establishes a link with the uplink processing node, the uplink processing node generates an uplink data stream and sends the uplink data stream to the FIFO of the second FPGA chip until the link from the uplink processing node to the second FPGA chip is in a blocking state, and then the link is set to be in a waiting state.
And the second FPGA chip sets a second synchronous starting signal in the form of a register flag bit, the second synchronous starting signal is invalid initially, and the FIFO read enable of the second FPGA chip is invalid when the second synchronous starting signal is invalid.
The second FPGA chip is used for setting the second synchronous starting signal to be effective when the rising edge of the 1 st 1PPS pulse signal after the effective signal in the second synchronization is carried out; and when the second synchronous starting signal is effective, the uplink data flow in the FIFO of the second FPGA chip is output through the uplink data output interface of the second FPGA chip.
And the uplink data enters an uplink data DA conversion module for DA conversion, and the obtained uplink DA conversion data is directly output.
Further, the downlink front-end machine is connected with the downlink signal processing node through a high-speed network; the uplink front-end machine is connected with the uplink signal processing node through a high-speed network.
Furthermore, a first frequency synthesis module is also arranged on the downlink front-end machine; and a second frequency synthesis module is also arranged on the uplink front-end machine.
The synchronous acquisition system adopts peripheral time system equipment to provide 10MHz frequency scale signals which are respectively sent to the first frequency synthesis module and the second frequency synthesis module.
The first frequency synthesis module performs phase locking on the 10MHz frequency scale signal to generate a working clock and sends the working clock to the downlink data AD conversion module.
The second frequency synthesis module performs phase locking on the 10MHz frequency scale signal to generate a working clock and sends the working clock to the uplink data DA conversion module.
Has the advantages that:
the invention provides a synchronous acquisition method and a synchronous acquisition system of an uplink front-end machine and a downlink front-end machine based on 1PPS, aiming at enabling uplink data streams and downlink data streams to have the same time reference, namely to be started at the same T0 moment. The time system equipment provides the system with 10MHz frequency scale and 1PPS second pulse input signals, which are generated by a co-vision receiver of an atomic clock and a GPS in a station, and the time delay difference between the signals is consistent and measurable during observation. Based on the method, firstly, the working clocks of the downlink data AD conversion module and the uplink data DA conversion module are ensured to be homologous, the 10MHz frequency scale is subjected to phase locking generation by the frequency synthesizer, and then 1PPS is used as a trigger signal of AD and DA starting time, so that synchronous starting can be realized. The method and the device do not depend on a high-performance special signal acquisition and processing board, the synchronous acquisition precision is superior to 0.06ns, and synchronous acquisition of the uplink and downlink front-end machines of the virtual measurement and control integrated baseband is realized.
Drawings
FIG. 1 is a block diagram of a system component of a virtual measurement and control integrated baseband system;
FIG. 2 is a schematic block diagram of a conventional measurement and control integrated baseband uplink and downlink signal acquisition method;
FIG. 3 is a schematic diagram of the lateral tone distance measurement principle;
fig. 4 is a system block diagram of a synchronous acquisition method based on 1PPS according to an embodiment of the present invention.
FIG. 5 is a schematic diagram illustrating a network time service synchronization error according to an embodiment of the present invention;
FIG. 6 is a timing diagram illustrating the generation of a synchronization enable signal according to an embodiment of the present invention;
FIG. 7 is a timing diagram illustrating the generation of a synchronization start signal according to an embodiment of the present invention;
fig. 8 is a block diagram of a system for testing the synchronous start performance of downlink data AD in the embodiment of the present invention;
fig. 9 shows a result of testing the synchronous start performance of the downlink data AD in the embodiment of the present invention; FIG. 9(a) is a comparison graph of the first 50 sampling points of the 1 st and 2 nd synchronous acquisition signals; FIG. 9(b) is a comparison graph of the first 50 sampling points of the 3 rd and 4 th synchronous acquisition signals; FIG. 9(c) is a graph comparing the phase delay difference between the 1 st and 2 nd acquisition signals and the phase delay difference between the 3 rd and 4 th acquisition signals;
fig. 10 is a block diagram of a system for testing synchronous start performance of uplink data DA in the embodiment of the present invention.
Detailed Description
The invention is described in detail below by way of example with reference to the accompanying drawings.
The invention provides a synchronous acquisition method and a system of an uplink front-end and a downlink front-end based on 1PPS (pulse per second), which can realize the synchronous acquisition of the uplink front-end and the downlink front-end of a virtual measurement and control integrated baseband, and have higher synchronous acquisition precision which is better than 0.06 ns. The principle of the invention is as follows: the purpose of the uplink and downlink signal synchronous acquisition method is to make uplink and downlink data streams have the same time reference, i.e. start at the same time T0. In the observation station, the time system equipment provides the system with 10MHz frequency scale and 1PPS second pulse external input signals, which are generated by an atomic clock and GPS common-view receiver in the station, so that the time delay difference between the 10MHz frequency scale and the 1PPS second pulse signals is consistent and measurable during observation. Based on the method, the working clocks of the AD and the DA are ensured to be homologous, phase locking is carried out on a 10MHz frequency scale by a frequency synthesizer, and then 1PPS is used as a trigger signal of the starting time of the AD and the DA, so that synchronous starting can be realized.
According to the principle of synchronous acquisition, in order to realize synchronous start of the AD and the DA at the time T0, firstly, it must be ensured that the time corresponding to the rising edge of the 1PPS serving as the trigger signal is the time T0, and secondly, it must be ensured that the rising edge of the start signal is synchronous with the rising edge of the 1PPS signal. To meet these two requirements, the starting strategy adopted is: firstly, the front-end machine utilizes the time management equipment to carry out network time service, and the time of the front-end machine and the time of the time management equipment are ensured to be basically kept synchronous; then, the front-end transmits a synchronization enable signal (the level is changed from low to high) 0.5 seconds before the time T0; thereafter, the synchronization start signal becomes active (level goes from low to high) at the 1 st rising edge of 1PPS after the synchronization enable signal is active.
As shown in fig. 4, the mechanism for synchronous start of the downstream and upstream data streams is described below.
The synchronous acquisition method of the uplink and downlink front-end machines based on 1PPS comprises the synchronous acquisition process of downlink data streams by the downlink front-end machines and the synchronous acquisition process of uplink data streams by the uplink front-end machines.
The principle of the synchronous acquisition mechanism of the downlink data stream is as follows: the method is realized by controlling a synchronous starting signal of the AD acquisition data stream. The synchronous starting signal is triggered by a 1PPS signal, when the signal is in an invalid state (low level), the AD acquisition data stream is marked as invalid, each function module of the FPGA is in a reset state, and when the synchronous starting signal is changed into the valid state (high level) after the 1PPS corresponding to the moment comes, the AD acquisition data stream is marked as valid and starts to enter a subsequent data processing link of the FPGA. The synchronous starting method is to use 1PPS as a trigger signal of a starting signal to ensure that the rising edge time of the starting signal is synchronous with the rising edge time of the 1PPS signal.
The principle of the uplink data flow synchronous acquisition mechanism is as follows: this can be achieved by controlling the synchronization start signal to the DA stream, which is the same as the downstream start mechanism. The difference is that before starting, the FPGA is in a working state, and the FIFO buffer must be filled with the uplink data, and the uplink data is sent to the DA after starting.
Therefore, the synchronous acquisition process of the downlink data stream comprises the following steps:
setting appointed synchronous acquisition starting time as T0Time of day, and setting a synchronization enable start time ratio T0Δ seconds ahead; and carrying out network time service on the downlink front-end machine.
Setting the first synchronous starting signal to be invalid initially, setting FIFO write enable of the first FPGA chip to be invalid when the first synchronous starting signal of the first FPGA chip is invalid, and setting the first FPGA chip for processing downlink data stream to be in a reset state.
At T0The first sync enable signal is asserted a second before the time.
The synchronization start signal becomes active at the rising edge of the 1 st 1PPS pulse signal after the first synchronization enable signal is active.
And when the synchronous starting signal is effective, the downlink data stream enters the first FPGA chip for subsequent processing of the downlink data stream through analog-to-digital conversion.
The synchronous acquisition process of the uplink data stream comprises the following steps:
carrying out network time service on the uplink front-end machine; and the uplink processing node generates uplink data and sends the uplink data stream to the FIFO of the second FPGA chip until a link from the uplink processing node to the second FPGA chip is in a blocking state, and then the link is set to be in a waiting state.
Setting a second synchronous starting signal for controlling FIFO read enabling of a second FPGA chip; and when the second synchronous starting signal is invalid, setting the FIFO read enable of the second FPGA chip to be invalid, and setting the second FPGA chip for storing the uplink data stream to be in a working state.
At T0The second sync enable signal is asserted a second before the time.
The second synchronization start signal becomes active at a rising edge of the 1 st 1PPS pulse signal after the second synchronization enable signal is active.
And when the second synchronous starting signal is effective, the uplink data flow in the second FPGA chip executes digital-to-analog conversion and subsequent uplink processing.
Therefore, a synchronous starting mechanism of the uplink data stream and the downlink data stream is realized.
In the embodiment of the present invention, the synchronization enabling error is set to Δ seconds, specifically, the synchronization enabling error is set to 0.5 seconds. The sync enable signal needs to be set high by the front-end 0.5 seconds before time T0, and first the front-end time and the time of the time system should remain substantially synchronized. FIG. 5 shows a schematic diagram of a timing synchronization error in a network timing method. Through testing, the time service synchronization error delta T is less than or equal to +/-10 ms. Because the front-end clock and the timing clock are different in source, the time synchronization error is increased after the front-end clock and the timing clock operate for a period of time. The front-end must be automatically re-timed every 1 hour.
Fig. 6 shows a timing diagram for generating the sync enable signal. The front-end computer configures an FPGA register through a PCIe bus, sets a synchronization enabling signal to be high 0.5 second before T0 time, and sets the synchronization enabling signal to be low after 1 second. Through testing, the synchronous enabling error is within 100ms, and the use requirement is met.
The generation strategy of the synchronous starting signal is realized by using a state machine of the FPGA, and a timing chart of the generation of the synchronous starting signal is given in FIG. 7. In fig. 7, the FPGA operating clock is phase locked by a 10MHz frequency scale and is therefore synchronized to the 1PPS signal. In order to realize the synchronization of the synchronization start signal and the first 1PPS signal after the arrival of the synchronization enable signal, firstly, the state machine enters a state of waiting for the synchronization enable to be valid after reset initialization, and whether the synchronization enable signal is valid is detected. When the synchronous enabling signal changes to an active level, the state machine enters a state of waiting for 1PPS, and whether the 1PPS signal is active or not is detected. When the 1PPS arrives, the state machine sets the synchronous starting signal to be high level immediately, and enters a state of waiting for invalid synchronous enabling, and whether the synchronous enabling signal is invalid is detected. When the synchronization enable signal becomes inactive (low level), the state machine sets the synchronization start signal to low level and enters the state of waiting for the synchronization enable to be active again. The AD and DA can be synchronously started for a plurality of times by the circulating operation.
In order to verify the performance of the synchronous acquisition method, the following tests and verifications are respectively performed on the downlink data AD synchronous start performance and the uplink data DA synchronous start performance.
Firstly, a measurement method based on phase delay is adopted to test the synchronous start delay performance of the downlink data AD. The principle of the measurement method based on the phase delay is as follows: and starting and collecting homologous single-point frequency signals for multiple times, recording, and analyzing the consistency of the phase of each recorded signal. If the synchronization is well designed, the phase of the recorded signal should be the same for each acquisition. From the definition of the phase delay:
in the formula:
is the initial phase of the signal as it is input to the system,
the phase of the signal after passing through the system, and f is the signal frequency. The phase of the signal actually found in the test is
Is unknown, but at each acquisition of a recordAre all fixed. The invention is based on the phase delay difference delta tau between multiple measurementspThe synchronous start-up performance of the device is described. From formula (3):
in the formula:
for the first time the phase of the signal is recorded,
the phase of the signal is recorded for the second time. As can be seen from equation (4), by recording the phase of the dot frequency signal, the synchronous start performance of the apparatus can be evaluated.
A block diagram of a system for testing the AD synchronous starting performance of downlink data is shown in FIG. 8, and a network time service server with the model number of HJ210-0CX0-B2 is used as a 10MHz frequency standard and a 1PPS signal source. The signal source and the baseband both adopt 10MHz as reference frequency, and the baseband collects and records 70MHz signals of the signal source. The data processing computer extracts the phases of the recorded signals of different times and calculates the performance index of synchronous starting.
And (3) respectively performing four times of synchronous acquisition records, wherein the first 50 sampling points of the 1 st and 2 nd acquired signals are shown in fig. 9(a), the first 50 sampling points of the 3 rd and 4 th acquired signals are shown in fig. 9(b), the phase delay difference between the 1 st and 2 nd acquired signals and the phase delay difference between the 3 rd and 4 th acquired signals are respectively obtained based on the phase delay measuring method, and the result is shown in fig. 9 (c). According to the test result, the synchronous acquisition precision of the downlink data AD is better than 0.06 ns.
Next, the synchronous start performance of the uplink data DA is observed by using the synchronous trigger function of the oscilloscope, and a block diagram of the test system is shown in fig. 10. And a network time service server with the model number of HJ210-0CX0-B2 is used as a 10MHz frequency standard and a 1PPS signal source. The baseband adopts 10MHz as a reference frequency standard, and generates a 70MHz analog signal under the triggering of 1PPS according to the uplink data synchronous starting method of the invention. The oscilloscope takes 1PPS as a trigger signal, and observes the relative time delay change between the 70MHz analog signal and the 1PPS through multiple synchronous starting.
Through a large number of experimental tests, the relative time delay between the uplink 70MHz analog signal output by the DA and 1PPS is kept unchanged, and the synchronous acquisition performance is good.
Based on the above principle, the present invention further provides a 1 PPS-based uplink and downlink front-end synchronous acquisition system, as shown in fig. 4, the system includes: the system comprises an uplink front-end machine, a downlink front-end machine, an uplink signal processing node and a downlink signal processing node; the uplink front-end machine is connected with the uplink signal processing node through a high-speed network.
The downlink front-end machine is connected with the downlink signal processing node through a network; the downlink front-end computer is provided with downlink application software, a downlink data AD conversion module and a first FPGA chip.
The uplink front-end machine is connected with the uplink signal processing node through a network; the uplink front-end computer is provided with uplink application software, an uplink data DA conversion module and a second FPGA chip.
The 1PPS pulse signal is sent to a first FPGA chip for triggering a first synchronous starting signal, and the 1PPS pulse signal is sent to a second FPGA chip for triggering a second synchronous starting signal; the initial states of the first synchronous starting signal and the second synchronous starting signal are both invalid.
The downlink data AD conversion module is provided with a downlink data input interface and a downlink AD conversion data output interface, downlink data flow enters the downlink data AD conversion module through the downlink data input interface, downlink AD conversion data are obtained after AD conversion, and the downlink AD conversion data are output through the downlink AD conversion data output interface.
The downlink AD conversion data output interface is connected to the first FPGA chip.
The first FPGA chip sets a first synchronous starting signal in the form of a register flag bit, and the first synchronous starting signal is invalid initially; when the first synchronous starting signal is invalid, the first FPGA chip is in a reset state, and FIFO write enable of the first FPGA chip is set to be invalid; (ii) a
Before the synchronous acquisition starts, the downlink front-end machine utilizes the NTP network time service server to carry out network time service.
The downlink application software is used for carrying out network time service on the downlink front-end machine; downstream application software, also for use at T0Setting a first synchronous enabling signal in the first FPGA chip to be effective delta seconds before the moment, wherein the first synchronous enabling signal exists in the first FPGA chip in a register mode.
The first FPGA chip is used for setting the first synchronous starting signal to be effective at the rising edge of the 1 st 1PPS pulse signal after the effective signal in the first synchronization; when the first synchronous starting signal is effective, the FIFO write enable of the first FPGA chip is effective, the first FPGA chip receives downlink AD conversion data, and the downlink AD conversion data enter the first FPGA chip to execute a subsequent downlink data processing process.
Before the synchronous acquisition is started, the uplink front-end machine utilizes the NTP network time service server to carry out network time service.
The uplink application software is used for carrying out network time service on the uplink front-end machine; uplink application software, also for use at T0And setting a second synchronous enabling signal in the second FPGA chip to be effective delta seconds before the moment, wherein the second synchronous enabling signal exists in the first FPGA chip in a register mode.
And the second FPGA chip establishes a link with the uplink processing node, the uplink processing node generates an uplink data stream and sends the uplink data stream to the FIFO of the second FPGA chip until the link from the uplink processing node to the second FPGA chip is in a blocking state, and then the link is set to be in a waiting state.
And the second FPGA chip sets a second synchronous starting signal in the form of a register flag bit, the second synchronous starting signal is invalid initially, and when the second synchronous starting signal is invalid, the FIFO read enable of the second FPGA chip is invalid, namely, the uplink data stream in the FIFO of the second FPGA chip cannot be read.
The second FPGA chip is used for setting the second synchronous starting signal to be effective when the rising edge of the 1 st 1PPS pulse signal after the effective signal in the second synchronization is carried out; and when the second synchronous starting signal is effective, the uplink data flow in the FIFO of the second FPGA chip is output through the uplink data output interface of the second FPGA chip.
And the uplink data enters an uplink data DA conversion module for DA conversion, and the obtained uplink DA conversion data is directly output.
In the embodiment of the invention, a first frequency synthesis module is also arranged on the downlink front-end machine; and a second frequency synthesis module is also arranged on the uplink front-end machine.
The synchronous acquisition system adopts peripheral time system equipment to provide 10MHz frequency scale signals which are respectively sent to the first frequency synthesis module and the second frequency synthesis module.
The first frequency synthesis module performs phase locking on the 10MHz frequency scale signal to generate a working clock and sends the working clock to the downlink data AD conversion module.
The second frequency synthesis module performs phase locking on the 10MHz frequency scale signal to generate a working clock and sends the working clock to the uplink data DA conversion module.
The working clocks of the downlink data AD conversion module and the uplink data DA conversion module are set to be the same source working clock.
In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. The synchronous acquisition method of the uplink and downlink front-end machines based on 1PPS is characterized by comprising the synchronous acquisition process of downlink data streams carried out by the downlink front-end machines and the synchronous acquisition process of uplink data streams carried out by the uplink front-end machines;
the synchronous acquisition process of the downlink data stream comprises the following steps:
setting appointed synchronous acquisition starting time as T0Time of day, and setting sync enable phase ratio T0Δ seconds ahead; network time service is carried out on the downlink front-end machine;
setting a first synchronous starting signal for controlling the write enable of the FIFO of the first FPGA chip; setting a first synchronous starting signal to be invalid initially, setting a register in a first FPGA chip to store the first synchronous starting signal, and setting a FIFO (first in first out) write enable of the first FPGA chip to be invalid and setting the first FPGA chip for processing downlink data stream to be in a reset state when the first synchronous starting signal is invalid;
a register is arranged in a first FPGA chip for storing a first synchronous enabling signal at T0Setting the first synchronization enabling signal to be effective delta seconds before the moment;
setting the synchronous starting signal to be effective by the first FPGA chip at the rising edge of the 1 st 1PPS pulse signal after the first synchronous enabling signal is effective;
when the first synchronous starting signal is effective, the FIFO write enable of the first FPGA chip is set to be effective, the downlink data stream is written into the FIFO of the first FPGA chip through analog-to-digital conversion, and the subsequent processing of the downlink data stream is executed;
the synchronous acquisition process of the uplink data stream comprises the following steps:
carrying out network time service on the uplink front-end machine;
the uplink processing node generates uplink data and sends uplink data flow to an FIFO (first in first out) of the second FPGA chip until a link from the uplink processing node to the second FPGA chip is in a blocking state, and then the link is set to be in a waiting state;
setting a second synchronous starting signal for controlling FIFO read enabling of a second FPGA chip; the second synchronous starting signal is invalid initially, when the second synchronous starting signal is invalid, the FIFO read enable of the second FPGA chip is invalid, and the second FPGA chip for storing the uplink data stream is set to be in a working state;
at T0Setting the second synchronization enabling signal to be effective delta seconds before the moment;
the second synchronization start signal becomes active at a rising edge of a 1 st 1PPS pulse signal after the second synchronization enable signal is active;
when the synchronous starting signal is effective, FIFO read enabling in the second FPGA chip is effective, wherein the uplink data flow executes digital-to-analog conversion and subsequent uplink processing;
therefore, a synchronous starting mechanism of the uplink data stream and the downlink data stream is realized.
2. The method of claim 1, wherein the setting of synchronization enable start time is compared to T0The advance is Δ seconds, specifically the set sync enable start time is advanced by 0.5 seconds.
3. Uplink and downlink front-end synchronous acquisition system based on 1PPS, its characterized in that, the system includes: the system comprises an uplink front-end machine, a downlink front-end machine, an uplink signal processing node and a downlink signal processing node;
the downlink front-end machine is connected with the downlink signal processing node through a network; the downlink front-end computer is provided with downlink application software, a downlink data AD conversion module and a first FPGA chip;
the uplink front-end machine is connected with the uplink signal processing node through a network; the uplink front-end computer is provided with uplink application software, an uplink data DA conversion module and a second FPGA chip;
1PPS pulse signals are sent to the first FPGA chip and used for triggering a first synchronous starting signal, and 1PPS pulse signals are sent to the second FPGA chip and used for triggering a second synchronous starting signal; the initial states of the first synchronous starting signal and the second synchronous starting signal are both invalid;
the downlink data AD conversion module is provided with a downlink data input interface and a downlink AD conversion data output interface, downlink data flow enters the downlink data AD conversion module through the downlink data input interface, downlink AD conversion data are obtained after AD conversion, and the downlink AD conversion data are output through the downlink AD conversion data output interface;
the downlink AD conversion data output interface is connected to the first FPGA chip;
the first FPGA chip sets a first synchronous starting signal in the form of a register flag bit, and the first synchronous starting signal is invalid initially; when the first synchronous starting signal is invalid, the first FPGA chip is in a reset state, and FIFO write enable of the first FPGA chip is set to be invalid;
before synchronous acquisition begins, a downlink front-end machine utilizes an NTP network time service server to carry out network time service;
the downlink application software is used for the application software at T0Setting a first synchronous enabling signal in a first FPGA chip as valid within delta seconds before the moment, wherein the first synchronous enabling signal exists in the first FPGA chip in a register form;
the first FPGA chip sets the first synchronous starting signal to be effective at the rising edge of the 1 st 1PPS pulse signal after the first synchronous enabling signal is effective; when the first synchronous starting signal is effective, the FIFO write enable of the first FPGA chip is effective, the first FPGA chip receives downlink AD conversion data, and the downlink AD conversion data enter the first FPGA chip to execute a subsequent downlink data processing process;
before synchronous acquisition begins, an uplink front-end machine utilizes an NTP network time service server to carry out network time service;
the uplink application software is used for the application software at T0Setting a second synchronous enabling signal in a second FPGA chip to be effective delta seconds before the moment, wherein the second synchronous enabling signal exists in the first FPGA chip in a register mode;
the second FPGA chip establishes a link with the uplink processing node, the uplink processing node generates an uplink data stream and sends the uplink data stream to the FIFO of the second FPGA chip until the link from the uplink processing node to the second FPGA chip is in a blocking state, and then the link is set to be in a waiting state;
the FPGA chip sets a second synchronous starting signal in the form of a register flag bit, the second synchronous starting signal is invalid initially, and when the second synchronous starting signal is invalid, the FIFO read enable of the second FPGA chip is invalid;
the second FPGA chip sets the second synchronous starting signal to be effective at the rising edge of the 1 st 1PPS pulse signal after the second synchronous enabling signal is effective; when the second synchronous starting signal is effective, the uplink data flow in the FIFO of the second FPGA chip is output through the uplink data output interface of the second FPGA chip;
and the downlink data enters the uplink data DA conversion module for DA conversion, and the obtained downlink DA conversion data is directly output.
4. The system of claim 3, wherein said downstream front-end machine and said downstream signal processing node are connected by a high-speed network;
and the uplink front-end machine is connected with the uplink signal processing node through a high-speed network.
5. The system of claim 3, wherein the downstream front end machine further comprises a first frequency synthesizer module; the uplink front-end machine is also provided with a second frequency synthesis module;
the synchronous acquisition system adopts peripheral time system equipment to provide 10MHz frequency scale signals which are respectively sent to the first frequency synthesis module and the second frequency synthesis module;
the first frequency synthesis module performs phase locking on the 10MHz frequency scale signal to generate a working clock and sends the working clock to the downlink data AD conversion module;
and the second frequency synthesis module performs phase locking on the 10MHz frequency scale signal to generate a working clock and sends the working clock to the uplink data DA conversion module.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5886992A (en) * | 1995-04-14 | 1999-03-23 | Valtion Teknillinen Tutkimuskeskus | Frame synchronized ring system and method |
| CN101990314A (en) * | 2009-08-03 | 2011-03-23 | 中兴通讯股份有限公司 | Packet control unit frame processing method, transmission method and system |
| CN102981116A (en) * | 2012-11-02 | 2013-03-20 | 北京创毅讯联科技股份有限公司 | Dedicated integrated circuit checking device and method |
| CN104281048A (en) * | 2014-08-26 | 2015-01-14 | 重庆九洲星熠导航设备有限公司 | Vehicle-mounted Beidou dual-mode satellite communication and positioning timing system and method |
| CN109284247A (en) * | 2018-06-29 | 2019-01-29 | 电子科技大学 | A kind of multichannel collecting system storage synchronous method of more FPGA |
| CN109451531A (en) * | 2018-11-08 | 2019-03-08 | 武汉虹信通信技术有限责任公司 | A kind of field strength measurement system and method in LTE cell range |
| CN110324166A (en) * | 2018-03-31 | 2019-10-11 | 华为技术有限公司 | A kind of method, apparatus and system of target information synchronous in multiple nodes |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4565751B2 (en) * | 2001-01-16 | 2010-10-20 | 富士通株式会社 | Transmission equipment |
-
2020
- 2020-06-16 CN CN202010550147.3A patent/CN112099389B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5886992A (en) * | 1995-04-14 | 1999-03-23 | Valtion Teknillinen Tutkimuskeskus | Frame synchronized ring system and method |
| CN101990314A (en) * | 2009-08-03 | 2011-03-23 | 中兴通讯股份有限公司 | Packet control unit frame processing method, transmission method and system |
| CN102981116A (en) * | 2012-11-02 | 2013-03-20 | 北京创毅讯联科技股份有限公司 | Dedicated integrated circuit checking device and method |
| CN104281048A (en) * | 2014-08-26 | 2015-01-14 | 重庆九洲星熠导航设备有限公司 | Vehicle-mounted Beidou dual-mode satellite communication and positioning timing system and method |
| CN110324166A (en) * | 2018-03-31 | 2019-10-11 | 华为技术有限公司 | A kind of method, apparatus and system of target information synchronous in multiple nodes |
| CN109284247A (en) * | 2018-06-29 | 2019-01-29 | 电子科技大学 | A kind of multichannel collecting system storage synchronous method of more FPGA |
| CN109451531A (en) * | 2018-11-08 | 2019-03-08 | 武汉虹信通信技术有限责任公司 | A kind of field strength measurement system and method in LTE cell range |
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