CN112086554A - Magnetic storage unit of magnetic random access memory - Google Patents

Magnetic storage unit of magnetic random access memory Download PDF

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CN112086554A
CN112086554A CN201910518030.4A CN201910518030A CN112086554A CN 112086554 A CN112086554 A CN 112086554A CN 201910518030 A CN201910518030 A CN 201910518030A CN 112086554 A CN112086554 A CN 112086554A
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bottom electrode
layer
magnetic
thickness
random access
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CN112086554B (en
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张云森
郭一民
陈峻
肖荣福
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Shanghai Ciyu Information Technologies Co Ltd
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Abstract

The invention relates to a magnetic memory unit of a magnetic random access memory, which comprises a substrate with a surface polished with a CMOS through hole, a bottom electrode, a magnetic tunnel junction and a top electrode, wherein the top of the substrate is distributed with the bottom electrode; the magnetic tunnel junction comprises a buffer layer, a crystalline seed layer, a synthetic antiferromagnetic layer-reference layer ferromagnetic coupling layer, a reference layer, a barrier layer, a free layer and a covering layer which are sequentially stacked upwards and have a multilayer structure; the bottom electrode comprises a first bottom electrode, a second bottom electrode and a second bottom electrode oxidation layer inside, the second bottom electrode is distributed on the top of the first bottom electrode, the second bottom electrode oxidation layer is distributed on the top of the second bottom electrode, and bottom electrode amorphous partition layers can be selectively distributed inside the first bottom electrode and the second bottom electrode.

Description

Magnetic storage unit of magnetic random access memory
Technical Field
The invention relates to the technical field of a Magnetic Random Access Memory (MRAM) with Perpendicular Anisotropy (PMA), in particular to a Magnetic Memory unit of the MRAM.
Background
In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered as a future solid-state nonvolatile memory, which has features of high speed read and write, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures in which there is a Free magnetic Layer (FL) that can change the direction of magnetization to record different data; an insulating tunnel Barrier Layer (BL) in the middle; and a magnetic Reference Layer (RL) on the other side of the tunnel barrier Layer and having a constant magnetization direction. Specifically, the structure may be a Bottom Pinned (Bottom Pinned) structure in which a reference layer, a barrier layer, and a free layer are sequentially stacked upward, or a Top Pinned (Top Pinned) structure in which a free layer, a barrier layer, and a reference layer are sequentially stacked upward. Currently, bottom pinned structures are popular.
In the current MRAM technology, the Bottom Electrode (BE), the Top Electrode (Top Electrode, TE) and the Bottom Electrode (MTJ) of the Magnetic Tunnel Junction (MTJ) are typically fabricated directly on the surface-polished CMOS VIA (VIA). Then, the fabrication process of the Bottom Electrode (BE) and how to implement the junction of the Bottom Electrode (BE) and the Magnetic Tunnel Junction (MTJ) become extremely important.
Disclosure of Invention
The present invention is directed to a magnetic random access memory magnetic memory cell, so as to solve the problems of the prior art, which is generally to directly fabricate a Bottom Electrode (BE) of a Magnetic Tunnel Junction (MTJ), and a Top Electrode (Top Electrode, TE) of a magnetic tunnel junction (Top) in a CMOS VIA (VIA) with a polished surface.
In order to achieve the purpose, the invention provides the following technical scheme: a magnetic random access memory magnetic storage unit comprises a substrate with a surface polished CMOS through hole, a bottom electrode, a magnetic tunnel junction and a top electrode, wherein the bottom electrode is distributed on the top of the substrate, the magnetic tunnel junction is distributed on the top of the bottom electrode, and the top electrode is distributed on the top of the magnetic tunnel junction;
the magnetic tunnel junction comprises a buffer layer, a crystalline seed layer, a synthetic antiferromagnetic layer-reference layer ferromagnetic coupling layer, a reference layer, a barrier layer, a free layer and a covering layer which are sequentially stacked upwards and have a multilayer structure;
the bottom electrode comprises a first bottom electrode, a second bottom electrode and a second bottom electrode oxidation layer inside, the second bottom electrode is distributed on the top of the first bottom electrode, the second bottom electrode oxidation layer is distributed on the top of the second bottom electrode, and bottom electrode amorphous partition layers can be selectively distributed inside the first bottom electrode and the second bottom electrode.
Compared with the prior art, the invention has the following beneficial effects:
according to the Bottom Electrode (BE) and the manufacturing process thereof, the Buffer Layer (BL) and the Crystalline Seed Layer (CSL) enable the substrate to have good surface roughness (smoothness), surface state and nucleation points before the MTJ magnetic structure unit is deposited, and due to the introduction of the Buffer Layer (BL), the Bottom Electrode (BE) and the MTJ unit can not influence the normal growth of the lattice structure of the MTJ unit because of different lattice constants. The method is very beneficial to the improvement of magnetism, electricity and yield of the whole MTJ unit and the miniaturization of devices.
Drawings
FIG. 1 is a schematic diagram of a magnetic random access memory cell with a double Bottom Electrode (BE), a Magnetic Tunnel Junction (MTJ) and a Top Electrode (TE) according to the present invention;
FIG. 2 is a diagram illustrating a Buffer Layer (BL) structure of a magnetic memory cell of a magnetic random access memory according to the present invention;
FIG. 3 is a schematic diagram of a MRAM magnetic memory cell of the present invention after sequentially depositing a Bottom Electrode (BE), a Magnetic Tunnel Junction (MTJ) multilayer film, and a Top Electrode (TE) on a surface-polished substrate with CMOS Via (Via);
FIG. 4 is a diagram illustrating the structure of the first bottom electrode (BE1) of a magnetic memory cell of the MRAM in accordance with the present invention;
FIG. 5 is a schematic diagram of the structures of the amorphous partition layers of the first bottom electrode (BE1) and the Bottom Electrode (BE) of the magnetic memory cell of the magnetic random access memory according to the present invention;
FIG. 6 is a diagram illustrating the structure of the second bottom electrode (BE2) of a magnetic memory cell of a magnetic random access memory in accordance with the present invention;
FIG. 7 is a diagram illustrating the second bottom electrode (BE2) and the amorphous partition layer structure of the Bottom Electrode (BE) in the magnetic memory cell of the MRAM in accordance with the present invention;
FIG. 8 is a diagram illustrating a second bottom electrode (BE2) before being oxidized in a magnetic memory cell of a magnetic random access memory in accordance with the present invention;
FIG. 9 is a diagram illustrating the structure of a MRAM magnetic memory cell according to the present invention after the second bottom electrode (BE2) has been oxidized.
In the figure: 1. surface polishing a substrate with CMOS through vias (Via); 101. a CMOS VIA (VIA) interlayer dielectric; 102. a CMOS VIA (VIA) metal diffusion barrier layer; 103. CMOS VIA (VIA) metal; 2. a bottom electrode; 201. a first bottom electrode (BE 1); 202. a second bottom electrode (BE 2); 203. a second bottom electrode (BE2) oxide layer; 204. a Bottom Electrode (BE) amorphous partition layer; 3. a Magnetic Tunnel Junction (MTJ); 301. a Buffer Layer (BL); 302. a Crystalline Seed Layer (CSL); 303. a synthetic antiferromagnetic layer (SyAF); 304. synthetic antiferromagnetic layer (SyAF) -reference layer ferromagnetic coupling layer; 305. a reference layer; 306. a barrier layer; 307. a free layer; 308. a cover layer; 4. a top electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-9, the present invention provides a technical solution: a magnetic random access memory magnetic memory cell includes a surface-polished substrate 1 with CMOS VIA (VIA), a CMOS VIA (VIA) interlayer dielectric (101), a CMOS VIA (VIA) metal diffusion barrier layer (102), a CMOS VIA (VIA) metal (103), a bottom electrode 2, a first bottom electrode (BE1)201, a second bottom electrode (BE2)202, a second bottom electrode (BE2) oxide layer 203, a Bottom Electrode (BE) amorphous partition layer 204, a Magnetic Tunnel Junction (MTJ)3, a Buffer Layer (BL)301, a Crystalline Seed Layer (CSL)302, a synthetic antiferromagnetic layer (SyAF)303, a synthetic antiferromagnetic layer (SyAF) -reference layer ferromagnetic coupling layer 304, a reference layer 305, a barrier layer 306, a free layer 307, a capping layer 308, a top electrode 4, a bottom electrode 2 distributed on top of an upper end of the surface-polished substrate 1 with CMOS VIA (VIA), and a Magnetic Tunnel Junction (MTJ)3 distributed on top of the bottom electrode 2, a top electrode 4 is distributed on top of the Magnetic Tunnel Junction (MTJ) 3.
The bottom electrode 2 includes a first bottom electrode (BE1)201, a second bottom electrode (BE2)202, a second bottom electrode (BE2) oxide layer 203 and a Bottom Electrode (BE) amorphous partition layer 204 inside, a second bottom electrode (BE2)202 is distributed on the top of the first bottom electrode (BE1)201, a second bottom electrode (BE2) oxide layer 203 is distributed on the top of the second bottom electrode (BE2)202, and the Bottom Electrode (BE) amorphous partition layer 204 can BE selectively distributed inside the first bottom electrode (BE1)201 and the second bottom electrode (BE2)202, and the forming steps include:
step 1: providing a surface-polished substrate 1 with CMOS through-holes (Via);
step 2: depositing a bottom electrode 2;
and step 3: depositing a Magnetic Tunnel Junction (MTJ)3 and a top electrode 4;
and 4, step 4: annealing the Magnetic Tunnel Junction (MTJ) structure unit after deposition at 350-450 ℃ is selected so that the reference layer 305 and the free layer 307 are transformed from an amorphous structure to a BCC (001) crystal structure by the template of the NaCl type structure FCC (001) barrier layer 306.
The bottom electrode 2 can BE divided into a first bottom electrode (BE1)201 and a second bottom electrode (BE2)202, wherein the total thickness of the first bottom electrode (BE1)201 is 10nm to 150nm, and the thickness of the second bottom electrode (BE2)202 is 0nm to 50nm (i.e., the second bottom electrode (BE2)202 can BE selectively made or not made after the first bottom electrode (BE1) 201). The total thickness and material of the Bottom Electrode (BE)2 is adjusted to obtain the best resistance after processing of the Magnetic Tunnel Junction (MTJ) cell array.
The material of the first bottom electrode (BE1)201 is Ti, TiN, Ta, TaN, W, WN, Ru or a combination thereof.
Further, TiN may be selectedx(x is less than or equal to 1) as the material of the first bottom electrode (BE1)201, and optionally TiNxA layer of Ti is deposited thereon.
In order to prevent the growth of the crystal grains of the first bottom electrode (BE1)201 during the PVD deposition process, one or more Bottom Electrode (BE) amorphous partition layers 204 may BE optionally inserted during the deposition process of the first bottom electrode (BE1), and the single-layer Bottom Electrode (BE) amorphous partition layer 204 has a thickness of 0.1nm to 3nm and is made of Ta, TaN, CoX, CoFeX, CoXY, FeX, CoFeXY, or a combination thereof, wherein X may BE B, C, Si, P, As, Sb, Ge, or Sn, etc., and Y may BE Ta, W, Ti, Mg, Al, Ca, Sc, V, Cr, Mn, Sr, Y, Zr, Nb, Mo, Ru, or Hf, etc.
After the PVD deposition process of the first bottom electrode (BE1)201, a Chemical Mechanical Planarization (CMP) process is selected to planarize it in order to further increase its surface Roughness (RMS) to a level of 0.1nm or 0.2 nm.
Wherein, in the CMP process, the pH value of CMP is controlled to be 0-7, and H can be added2O2,KIO3,Fe(NO3)3Or K3Fe(CN)6And oxidizing agent is added into the aqueous slurry to increase its redox potential.
Further, SiO may be selected2、Al2O3、CeO2Or MnO2And the like are abrasives.
The structure of the second bottom electrode (BE2)202 is as follows:
when the thickness of the second bottom electrode (BE2)202 is not zero; the material of the second bottom electrode (BE2)202 is TiNx(x is less than or equal to 1) and can be selectively placed on TiNxA layer of Ti is deposited thereon.
In order to prevent the growth of the grains of the second bottom electrode (BE2)202 during the PVD deposition process, one or more Bottom Electrode (BE) amorphous partition layers 204 may BE optionally inserted during the deposition process of the second bottom electrode (BE2), and the single-layer bottom electrode (BE1) amorphous partition layer 204 has a thickness of 0.1nm to 3nm and is made of Ta, TaN, CoX, CoFeX, CoXY, FeX, NiX, NiFeX, NiCr, NiFeCr, NiCrY, NiFeCrY, CoFeX, NiFeX, or a combination thereof, wherein X may BE B, C, Si, P, As, Sb, Ge, or Sn, etc., and Y may BE Ta, W, Ti, Mg, Al, Ca, Sc, V, Cr, Mn, Sr, Y, Zr, Nb, Mo, Ru, or Hf, etc.
As shown in FIG. 7, to prevent the growth of the second bottom electrode (BE2)202, the second bottom electrode (BE2)202 may BE slightly oxidized to produce ultra-thin TiOxOr TiNOxEtc., the oxidizing group may be O, O2Or O3(the oxidation process may be O)3Or O2Oxidation process, O oxidation process produced in plasma).
Due to the small thickness of the oxide layer 203 of the second bottom electrode (BE2), no electrical separation of the bottom electrode 2 and the Magnetic Tunnel Junction (MTJ)3 is formed under this condition. Meanwhile, due to the existence of the second bottom electrode (BE2) oxide layer 203, the bottom electrode 2 and the crystal lattices of the Magnetic Tunnel Junction (MTJ)3 can BE effectively separated.
The top electrode 4 is disposed on top of the Magnetic Tunnel Junction (MTJ)3 and is typically formed of Ta, TaN, W, WN, Ti, TiN or any combination thereof.
The Magnetic Tunnel Junction (MTJ)3 includes a Buffer Layer (BL)301, a Crystalline Seed Layer (CSL)302, a synthetic antiferromagnetic layer (SyAF)303, a synthetic antiferromagnetic layer (SyAF) -reference layer ferromagnetic coupling layer 304, a reference layer 305, a barrier layer 306, a free layer 307, and a capping layer 308 inside, and the Crystalline Seed Layer (CSL)302 is distributed on top of the Buffer Layer (BL)301, the synthetic antiferromagnetic layer (SyAF)303 is connected on top of the Crystalline Seed Layer (CSL)302, and the synthetic antiferromagnetic layer (SyAF) -reference layer ferromagnetic coupling layer 304 is arranged on top of the synthetic antiferromagnetic layer (SyAF)303, the reference layer 305 is connected on top of the synthetic antiferromagnetic layer (SyAF) -reference layer ferromagnetic coupling layer 304, and the barrier layer 306 is arranged on top of the reference layer 305, the free layer 307 is distributed on top of the barrier layer, the capping layer 308 is distributed on top of the free layer 307, the Buffer Layer (BL)301, The Crystalline Seed Layer (CSL)302, the synthetic antiferromagnetic layer (SyAF)303, the synthetic antiferromagnetic layer (SyAF) -reference layer ferromagnetic coupling layer 304, the reference layer 305, the barrier layer 306, the free layer 307, and the capping layer 308 constitute a multilayer structure, and the Buffer Layer (BL)301, the Crystalline Seed Layer (CSL)302, the synthetic antiferromagnetic layer (SyAF)303, the synthetic antiferromagnetic layer (SyAF) -reference layer ferromagnetic coupling layer 304, the reference layer 305, the barrier layer 306, the free layer 307, and the capping layer 308 are stacked on one another in this order from the bottom up. The specific structure of the Magnetic Tunnel Junction (MTJ)3 is as follows:
1) the Buffer Layer (BL)301 is made of [ (Ta, TaN)/Ru]nOr [ Ru/(Ta, TaN)]nWherein n is more than or equal to 1, the thickness of Ru is 0 nm-10 nm, and the thickness of Ta or TaN is 0 nm-10 nm.
More specifically, when n is 1, the thickness of Ru is 0.1nm to 10nm, and the thickness of Ta or TaN is 0.2nm to 2.0 nm.
Furthermore, the thickness of Ru can be selected to be 0, and the thickness of Ta or TaN can be selected to be 0.5 nm-2.0 nm; the thickness of Ru is 0.5 nm-10 nm, and the thickness of Ta or TaN is 0.
When n is more than or equal to 2, the thickness of Ru is 0.1 nm-10 nm, and the thickness of Ta or TaN is 0.2 nm-2.0 nm; the thickness of each Ta or TaN layer can be the same or different, and the thickness of each Ru layer can be the same or different.
2) The Crystalline Seed Layer (CSL)302 has a specific structure of Pt or Pt/Ru/Pt.
Further, Pt is selected as the Crystalline Seed Layer (CSL)302, and the thickness of the Pt is 1nm to 10 nm.
Further, Pt/Ru/Pt is selected as a Crystalline Seed Layer (CSL) (302), wherein the first layer Pt is 1nm to 10nm thick, the second layer Ru is 2nm to 20nm thick, and the third layer Pt is 0.1nm to 1.0nm thick.
3) The synthetic antiferromagnetic layer (SyAF)303 has the structure [ Co/(Pt, Pd or Ni)]nCo/(Ru, Ir or Rh)/Co [ (Pt, Pd or Ni)/Co ]]m(where m.gtoreq.0, the thickness of the individual layers of Co, (Pt, Pd or Ni) and (Ru, Ir or Rh) is less than 1nm, and further, the individual layer thickness of Co and (Pt, Pd or Ni) may be below 0.5nm, such as 0.10nm, 0.15nm, 0.20nm, 0.25nm, 0.30nm, 0.35nm, 0.40nm, 0.45nm or 0.50nm, etc.).
The synthetic antiferromagnetic layer (SyAF) -reference layer ferromagnetic coupling layer 304 is typically composed of Ta, W, Mo, Hf, Fe, Co (Ta, W, Mo or Hf), Fe (Ta, W, Mo or Hf), FeCo (Ta, W, Mo or Hf), FeCoB (Ta, W, Mo or Hf), or the like. Its main role is to achieve lattice separation of the synthetic antiferromagnetic layer (SyAF)303 with FCC (111) and the reference layer 305 with BCC (001).
4) The reference layer 305 has a thickness of 0.5nm to 2.0nm, and is typically Co, Fe, Ni, CoFe, CoB, FeB, CoFeB, a combination thereof, or the like.
5) The barrier layer 306 is a nonmagnetic metal oxide, has a total thickness of 0.6nm to 1.5nm, and is preferably MgO, MgZnO, MgBO, or MgAlO. Further, MgO may be selected.
6) The free layer 307 has a variable magnetic polarization and a total thickness of 1.1nm to 3nm, and generally comprises CoB, FeB, CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB/(Ta, W, Mo, Hf)/CoFeB, Fe/CoFeB/(W, Mo, Hf)/CoFeB or CoFe/CoFeB/(W, Mo, Hf)/CoFeB, and further CoFeB/(W, Mo, Hf)/CoFeB, Fe/CoFeB/(W, Mo, Hf)/CoFeB or CoFe/CoFeB/(W, Mo, Hf)/CoFeB structure can be selected.
After the deposition of the free layer 307, a capping layer 308 is deposited again, typically a bilayer structure of (Mg, MgO, MgZnO, MgBO or MgAlO)/(W, Mo, Mg, Nb, Ru, Hf, V, Cr or Pt, or a combination thereof), preferably a structure of MgO/(W, Mo, Hf)/Ru or MgO/Pt/(W, Mo, Hf)/Ru, etc., may be selected. The superior effect of choosing MgO provides a source of additional interfacial anisotropy for the free layer 307, thereby increasing thermal stability.
The working principle of the embodiment is as follows: the magnetic random access memory magnetic storage unit is used firstly.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the invention can be made, and equivalents and modifications of some features of the invention can be made without departing from the spirit and scope of the invention.

Claims (10)

1. A magnetic random access memory magnetic storage cell, comprising: the surface-polished CMOS tunnel junction device comprises a substrate with a CMOS through hole, a bottom electrode, a magnetic tunnel junction and a top electrode, wherein the bottom electrode is distributed on the top of the substrate;
the magnetic tunnel junction comprises a buffer layer, a crystalline seed layer, a synthetic antiferromagnetic layer-reference layer ferromagnetic coupling layer, a reference layer, a barrier layer, a free layer and a covering layer which are sequentially stacked upwards and have a multilayer structure;
the bottom electrode comprises a first bottom electrode, a second bottom electrode and a second bottom electrode oxidation layer inside, the second bottom electrode is distributed on the top of the first bottom electrode, the second bottom electrode oxidation layer is distributed on the top of the second bottom electrode, and bottom electrode amorphous partition layers can be selectively distributed inside the first bottom electrode and the second bottom electrode.
2. The magnetic random access memory magnetic storage cell of claim 1, wherein: the total thickness of the first bottom electrode is 10 nm-150 nm, and the thickness of the second bottom electrode is 0 nm-50 nm.
3. The magnetic random access memory magnetic storage cell of claim 2, wherein: selection of TiNxAs the material of the first bottom electrode, and optionally TiNxDepositing a layer of Ti on the substrate, wherein x is less than or equal to 1;
selecting TiN when the thickness of the second bottom electrode is not zeroxAs the material of the second bottom electrode, and optionally TiNxA layer of Ti is deposited thereon.
4. The magnetic random access memory magnetic storage cell of claim 1, wherein: the material of the first bottom electrode is Ti, TiN, Ta, TaN, W, WN, Ru or the combination of the Ti, TiN, Ta, TaN, W, WN and Ru;
the material of the second bottom electrode is Ti, TiN, TiON, Ta, TaN, TaON, W, WN, WON, Ru or the combination thereof.
5. The magnetic random access memory magnetic storage cell of claim 1, wherein: one or more first bottom electrode amorphous partition layers are optionally inserted in the deposition process of the first bottom electrode, the total thickness of the first bottom electrode amorphous partition layers is 0.1 nm-3 nm, the material of the first bottom electrode amorphous partition layers is Ta, TaN, CoX, CoFeX, CoXY, FeX, CoFeXY or the combination of the Ta, TaN, CoX, CoFeX and CoFeXY, wherein X can be B, C, Si, P, As, Sb, Ge or Sn, Y can be Ta, W, Ti, Mg, Al, Ca, Sc, V, Cr, Mn, Sr, Y, Zr, Nb, Mo, Ru or Hf;
one or more second bottom electrode amorphous partition layers are optionally inserted in the deposition process of the second bottom electrode. The total thickness of the amorphous partition layer of the second bottom electrode is 0.1 nm-3 nm, and the amorphous partition layer is made of Ta, TaN, CoX, CoFeX, CoXY, FeX, NiX, NiFeX, NiCr, NiFeCr, NiCrY, NiFeCrY, CoFeXY, NiFeXY or a combination of the above materials, wherein X is B, C, Si, P, As, Sb, Ge or Sn, Y is Ta, W, Ti, Mg, Al, Ca, Sc, V, Cr, Mn, Sr, Y, Zr, Nb, Mo, Ru or Hf.
6. The magnetic random access memory magnetic storage cell of claim 1, wherein: after the first bottom electrode deposition process, the first bottom electrode deposition process is planarized by a chemical mechanical planarization process.
7. The magnetic random access memory magnetic storage cell of claim 1, wherein: slight oxidation of the second bottom electrode to produce ultra-thin TiOxOr TiNOxThe oxidizing group is O, O2Or O3
8. The magnetic random access memory magnetic storage cell of claim 1, wherein: the buffer layer is made of [ (Ta, TaN)/Ru]nOr [ Ru/(Ta, TaN)]nWherein n is more than or equal to 1, the thickness of Ru is 0 nm-10 nm, and the thickness of Ta or TaN is 0 nm-10 nm;
the crystalline seed layer has a structure of Pt or Pt/Ru/Pt;
the synthetic antiferromagnetic layer has the structure of [ Co/(Pt, Pd or Ni)]nCo/(Ru, Ir or Rh)/Co [ (Pt, Pd or Ni)/Co ]]mWherein m is more than or equal to 0, single layerThe thicknesses of Co, (Pt, Pd or Ni) and (Ru, Ir or Rh) are less than 1 nm;
the synthetic antiferromagnetic layer-reference layer ferromagnetic coupling layer is made of Ta, W, Mo, Hf, Fe, Co (Ta, W, Mo or Hf), Fe (Ta, W, Mo or Hf), FeCo (Ta, W, Mo or Hf) or FeCoB (Ta, W, Mo or Hf);
the reference layer has a thickness of 0.5nm to 2.0nm, and is typically Co, Fe, Ni, CoFe, CoB, FeB, CoFeB or a combination thereof;
the barrier layer is made of nonmagnetic metal oxide, and the total thickness of the barrier layer is 0.6 nm-1.5 nm;
the free layer has variable magnetic polarization, has the total thickness of 1.1 nm-3 nm, and consists of CoB, FeB, CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB/(Ta, W, Mo, Hf)/CoFeB, Fe/CoFeB/(W, Mo, Hf)/CoFeB or CoFe/CoFeB/(W, Mo, Hf)/CoFeB;
the covering layer is of a (Mg, MgO, MgZnO, MgBO or MgAlO)/(W, Mo, Mg, Nb, Ru, Hf, V, Cr or Pt combination) double-layer structure.
9. The magnetic random access memory magnetic storage cell of claim 8, wherein: selecting Pt as a crystalline seed layer, wherein the thickness of the crystalline seed layer is 1 nm-10 nm;
selecting Pt/Ru/Pt as crystalline seed layer, wherein the thickness of the first layer of Pt is 1 nm-10 nm, the thickness of the second layer of Ru is 2 nm-20 nm, and the thickness of the third layer of Pt is 0.1 nm-1.0 nm.
10. The magnetic random access memory magnetic storage cell of claim 1, wherein: and annealing the magnetic tunnel junction structure after deposition at 350-450 ℃ so that the reference layer and the free layer are converted from an amorphous structure into a BCC crystal structure under the template action of the NaCl type FCC barrier layer.
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