CN112086488B - Display panel and manufacturing method thereof - Google Patents
Display panel and manufacturing method thereof Download PDFInfo
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- CN112086488B CN112086488B CN202010928793.9A CN202010928793A CN112086488B CN 112086488 B CN112086488 B CN 112086488B CN 202010928793 A CN202010928793 A CN 202010928793A CN 112086488 B CN112086488 B CN 112086488B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/128—Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
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Abstract
The application provides a display panel and a manufacturing method thereof, wherein the display panel comprises: a substrate; the first thin film transistor layer is arranged on the substrate and comprises a first thin film transistor and a second thin film transistor which are arranged on the same layer; the first light-emitting layer is arranged on one side, far away from the substrate, of the first thin film transistor layer and is electrically connected with the first thin film transistor, and the first thin film transistor controls the light-emitting condition of the first light-emitting layer; the second light-emitting layer is arranged on one side of the substrate, which is far away from the first thin film transistor layer, and is electrically connected with the second thin film transistor, and the second thin film transistor controls the light-emitting condition of the second light-emitting layer; the scheme can improve the lightness, thinness and cost performance of the display while realizing double-sided display.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and a method for manufacturing the same.
Background
The display can be used as an electronic product to transmit a large amount of picture information to audiences, and particularly, the picture information in large-scale public places such as stations, halls, song stages and the like needs to cover more people, so that the display with a double-sided display function is produced.
However, a conventional display having a double-sided display function is basically configured such that two display panels for single-sided display are assembled back to back, and the same or different electric signals are input to the two display panels for single-sided display, so that the two display panels for single-sided display images, respectively. Therefore, the conventional display with the double-sided display function has a heavy structure, a complex process and high cost, and the light weight, the thinness and the cost performance of the display are reduced.
Therefore, it is necessary to provide a display panel and a method for fabricating the same, which can be used for dual-sided display and can improve the lightness, thinness and cost performance of the display.
Disclosure of Invention
The embodiment of the application provides a display panel and a manufacturing method thereof, wherein the display panel comprises a first light-emitting layer and a second light-emitting layer which are respectively arranged on the opposite sides of a substrate, and a first thin film transistor for controlling the light-emitting condition of the first light-emitting layer and a second thin film transistor for controlling the light-emitting condition of the second light-emitting layer are arranged in the same layer, so that the two display panels are prevented from being assembled to realize double-sided display after being respectively manufactured; the problems of heavy structure, complex process and high cost of the existing display with the double-sided display function are solved.
The embodiment of the present application provides a display panel, display panel includes:
a substrate;
the first thin film transistor layer is arranged on the substrate and comprises a first thin film transistor and a second thin film transistor which are arranged on the same layer;
the first thin film transistor layer is arranged on the substrate, and is electrically connected with the first thin film transistor layer;
the second light-emitting layer is arranged on one side, far away from the first thin film transistor layer, of the substrate and electrically connected with the second thin film transistor, and the second thin film transistor controls the light-emitting condition of the second light-emitting layer.
In one embodiment, the display panel further includes:
the first flat layer is arranged on one side, close to the first light-emitting layer, of the first thin film transistor layer and comprises a first through hole, the first through hole is opposite to the first thin film transistor, and the first light-emitting layer is electrically connected with the first thin film transistor through the first through hole;
the second through hole is formed in the substrate, the second through hole is opposite to the second thin film transistor, and the second light emitting layer is electrically connected with the second thin film transistor through the second through hole.
In an embodiment, the substrate includes a first region and a second region, the second region is disposed on at least one side of the first region, the first thin-film transistor layer is disposed in the first region, and the display panel further includes:
the second thin film transistor layer is arranged on the substrate and is positioned in the second area, the second thin film transistor layer and the first thin film transistor layer are arranged on the same layer, and the second thin film transistor layer comprises a third thin film transistor;
and the third light-emitting layer is arranged on one side of the second thin film transistor layer far away from the substrate, and is electrically connected with the third thin film transistor, and the third thin film transistor controls the light-emitting condition of the third light-emitting layer.
In one embodiment, the display panel further includes:
the second flat layer is arranged on one side, close to the third light-emitting layer, of the second thin film transistor layer and comprises a third through hole, the third through hole is opposite to the third thin film transistor, and the third light-emitting layer is electrically connected with the third thin film transistor through the third through hole.
In one embodiment, the second planar layer and the first planar layer are disposed in the same layer.
In an embodiment, the substrate further includes a third region between the first region and the second region, the third region being used to bend the display panel, the display panel further including:
and the bending layer is arranged on the substrate, the bending layer is positioned in the third area, and the bending layer and the second thin film transistor layer are arranged in the same layer.
In one embodiment, the display panel further includes:
the power module is arranged on one side, far away from the second thin film transistor layer, of the substrate, is located in the second area, and provides working voltage for the first thin film transistor layer and the second thin film transistor layer.
In one embodiment, the first light-emitting layer includes a plurality of first light-emitting portions, the second light-emitting layer includes a plurality of second light-emitting portions, the third light-emitting layer includes a plurality of third light-emitting portions, the arrangement density of the plurality of second light-emitting portions is the same as or different from the arrangement density of the plurality of first light-emitting portions, and the arrangement density of the plurality of third light-emitting portions is the same as the arrangement density of the plurality of first light-emitting portions.
The embodiment of the application provides a manufacturing method of a display panel, which is used for preparing the display panel, and the method comprises the following steps:
providing a substrate;
forming a first thin film transistor layer on the substrate, wherein the first thin film transistor layer comprises a first thin film transistor and a second thin film transistor which are arranged in the same layer;
and forming a first light-emitting layer on one side of the first thin film transistor layer far away from the substrate and a second light-emitting layer on one side of the substrate far away from the first thin film transistor layer, wherein the first light-emitting layer is electrically connected with the first thin film transistor, the first thin film transistor controls the light-emitting condition of the first light-emitting layer, the second light-emitting layer is electrically connected with the second thin film transistor, and the second thin film transistor controls the light-emitting condition of the second light-emitting layer.
In an embodiment, before the step of forming a first light emitting layer on a side of the first thin film transistor layer far from the substrate and forming a second light emitting layer on a side of the substrate far from the first thin film transistor layer, the first light emitting layer is electrically connected to the first thin film transistor, the first thin film transistor controls light emission of the first light emitting layer, the second light emitting layer is electrically connected to the second thin film transistor, and the second thin film transistor controls light emission of the second light emitting layer, the method includes:
forming a first flat layer on one side of the first thin film transistor layer close to the substrate, wherein the first flat layer comprises a first through hole, the first through hole is arranged opposite to the first thin film transistor, and the first light-emitting layer is electrically connected with the first thin film transistor through the first through hole;
and forming a second through hole on the substrate, wherein the second through hole is opposite to the second thin film transistor, and the second light-emitting layer is electrically connected with the second thin film transistor through the second through hole.
The application provides a display panel and a manufacturing method thereof, wherein the display panel comprises: a substrate; the first thin film transistor layer is arranged on the substrate and comprises a first thin film transistor and a second thin film transistor which are arranged on the same layer; the first light-emitting layer is arranged on one side, far away from the substrate, of the first thin film transistor layer and is electrically connected with the first thin film transistor, and the first thin film transistor controls the light-emitting condition of the first light-emitting layer; and the second light-emitting layer is arranged on one side of the substrate, which is far away from the first thin film transistor layer, and is electrically connected with the second thin film transistor, and the second thin film transistor controls the light-emitting condition of the second light-emitting layer. According to the display device, the first thin film transistor used for controlling the light emitting condition of the first light emitting layer and the second thin film transistor used for controlling the light emitting condition of the second light emitting layer are arranged on the same layer, so that the two display panels are prevented from being assembled to realize double-sided display after being manufactured respectively, and the light weight, the light weight and the cost performance of the display are improved while the double-sided display is realized.
Drawings
The present application is further illustrated by the following figures. It should be noted that the drawings in the following description are only for illustrating some embodiments of the present application, and that other drawings may be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic cross-sectional view of a first display panel provided in an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a second display panel provided in the embodiment of the present application;
fig. 3 is a schematic cross-sectional view of a third display panel provided in the embodiment of the present application;
fig. 4 is a schematic cross-sectional view of a fourth display panel provided in the embodiment of the present application;
fig. 5 is a schematic cross-sectional view of a fifth display panel according to an embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view of a sixth display panel provided in an embodiment of the present application;
fig. 7 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 8 is a flowchart of another method for manufacturing a display panel according to an embodiment of the present disclosure.
Detailed Description
The technical solution in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "away", "close", "lower", "upper", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the drawings, elements having similar structures are denoted by the same reference numerals. Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.
Embodiments of the present application provide a display panel including, but not limited to, the following embodiments and combinations of the following embodiments.
In one embodiment, as shown in fig. 1, the display panel 00 includes: a substrate 100; a first thin film transistor layer 200, where the first thin film transistor layer 200 is disposed on the substrate 100, the first thin film transistor layer 200 includes a first thin film transistor 201 and a second thin film transistor 202, and the first thin film transistor 201 and the second thin film transistor 202 are disposed on the same layer; a first light-emitting layer 300, where the first light-emitting layer 300 is disposed on a side of the first thin-film transistor layer 200 away from the substrate 100, the first light-emitting layer 300 is electrically connected to the first thin-film transistor 201, and the first thin-film transistor 201 controls a light-emitting condition of the first light-emitting layer 300; the second light emitting layer 400 is disposed on a side of the substrate 100 away from the first thin film transistor layer 200, the second light emitting layer 400 is electrically connected to the second thin film transistor 202, and the second thin film transistor 202 controls a light emitting condition of the second light emitting layer 400.
The substrate 100 may be a rigid substrate or a flexible substrate, the rigid substrate may be glass or a silicon wafer, and the flexible substrate may be a polymer material substrate, a metal foil substrate, an ultra-thin glass substrate, a polymer/inorganic substance substrate, or a polymer/organic substance/inorganic substance substrate, where the polymer material may include at least one of polyethylene, polypropylene, polystyrene, polyethylene terephthalate, polyethylene naphthalate, and polyimide.
The first thin film transistor layer 200 may include a plurality of first thin film transistors 201 and a plurality of second thin film transistors 202, the first thin film transistors 201 and the second thin film transistors 202 may be alternately disposed, and a gap may be formed between adjacent first thin film transistors 201 and adjacent second thin film transistors 202, so that the adjacent first thin film transistors 201 and adjacent second thin film transistors 202 are electrically insulated.
It is to be understood that, since the first thin film transistor 201 and the second thin film transistor 202 control the light emission of the first light emitting layer 300 and the second light emitting layer 400, respectively, the arrangement of the light emitting parts in the first light emitting layer 300 and the second light emitting layer 400 may be determined according to the arrangement of the first thin film transistor 201 and the second thin film transistor 202. As shown in fig. 1, the first light emitting layer 300 may include a plurality of first light emitting portions 301, and the second light emitting layer 400 may include a plurality of second light emitting portions 401, and since the first light emitting layer 300 and the second light emitting layer 400 both display a picture on a side away from the substrate 100, the plurality of first light emitting portions 301 and the plurality of second light emitting portions 401 are not arranged in a related manner, that is, the arrangement density of the plurality of second light emitting portions 401 is the same as or different from the arrangement density of the plurality of first light emitting portions 301.
Specifically, the projections of the plurality of first light-emitting portions 301 and the plurality of second light-emitting portions 401 on the same horizontal plane may overlap or may not overlap. For example, the plurality of first light emitting parts 301 and the plurality of second light emitting parts 401 may correspond to each other one by one, and the positions and/or sizes of the first light emitting parts 301 and the corresponding second light emitting parts 401 may be the same or different; further, when the first light emitting layer 301 and the corresponding second light emitting layer 401 have the same size, the resolution of the screen displayed by the first light emitting layer 300 is the same as the resolution of the screen displayed by the second light emitting layer 400.
Specifically, each adjacent two first thin film transistors 201 and each adjacent two second thin film transistors 202 may have a first light emitting portion 301 disposed on the upper side, and an edge of the first light emitting portion 301 may or may not exceed an edge of the corresponding adjacent two first thin film transistors 201 and the corresponding adjacent two second thin film transistors 202, and similarly, the plurality of second light emitting portions 401 may also refer to the manner of disposing the plurality of first light emitting portions 301.
In an embodiment, as shown in fig. 2, the display panel 00 further includes: a first planarization layer 500, where the first planarization layer 500 is disposed on a side of the first thin film transistor layer 200 close to the first light emitting layer 300, the first planarization layer 500 includes a first through hole 501, the first through hole 501 is opposite to the first thin film transistor 201, and the first light emitting layer 300 is electrically connected to the first thin film transistor 201 through the first through hole 501; a second via 104, where the second via 104 is disposed on the substrate 100, the second via 104 is disposed opposite to the second thin film transistor 202, and the second light emitting layer 400 is electrically connected to the second thin film transistor 202 through the second via 104.
Specifically, the first thin film transistor 201 and the second thin film transistor 202 may be thin film transistors with a top gate structure or thin film transistors with a bottom gate structure, and the thin film transistors with a top gate structure are taken as an example for description here. As shown in fig. 2, the first thin film transistor 201 includes a first active layer 2011, a first gate 2012 disposed on the first active layer 2011, a first source 2013 and a first drain 2014 disposed at two sides of the first gate 2012, the width of the first gate 2012 is less than that of the first active layer 2011, a gate insulating layer 203 is disposed between the first active layer 2011 and the first gate 2012, the gate insulating layer 203 covers the first active layer 2011 and the substrate 100, an interlayer insulating layer 204 is disposed between the first gate 2012 and the first source 2013, and between the first gate 2012 and the first drain 2014, the first source 2013 and the first drain 2014 sequentially penetrate through the inter-layer insulating layer 204 and a partial region of the gate insulating layer 203 to the upper surface of the first active layer 2011 so as to be electrically connected with the first active layer 2011. Similarly, the second thin film transistor 202 includes a second active layer 2021, a second gate 2022, a second source 2023, and a second drain 2024, the arrangement manner of the second thin film transistor 202 may refer to the arrangement manner of the first thin film transistor 201, and the relative position relationship among the plurality of film layers in the gate insulating layer 203, the inter-insulating layer 204, and the second thin film transistor 202 may refer to the relative position relationship among the plurality of film layers in the gate insulating layer 203, the inter-insulating layer 204, and the first thin film transistor 201; the second active layer 2021 and the first active layer 2011 are disposed in the same layer, the second gate 2022 and the first gate 2012 are disposed in the same layer, and the second source 2023, the second drain 2024, the first source 2013 and the first drain 2014 are disposed in the same layer.
The composition materials of the first active layer 2011 and the second active layer 2021 may include, but are not limited to, polysilicon and doped polysilicon; the composition material of the gate insulating layer 203 may include, but is not limited to, inorganic materials such as silicon nitride and silicon oxide; the constituent materials of the first gate 2012 and the second gate 2022 may include, but are not limited to, metals with low resistivity; the first source 2013, the first drain 2014, the second source 2023 and the second drain 2024 may be made of the same material as the first gate 2012; the constituent material of the interlayer insulating layer 204 is the same as that of the gate insulating layer 203.
Specifically, the first planarization layer 500 is disposed on the inter-insulating layer 204, the first source 2013, the first drain 2014, the second source 2023, and the second drain 2024, the first via 501 is disposed on the first source 2013 or the first drain 2014, the first light-emitting layer 300 is disposed in the first via 501 and on the first planarization layer 500, and the first light-emitting layer 300 is electrically connected to the first source 2013 or the first drain 2014 through the first via 501.
Specifically, the second via 104 is disposed below the second source 2023 or the second drain 2024 beyond the second active layer 2021, the second via 104 sequentially penetrates through the inter-insulating layer 204, the gate insulating layer 203, and the substrate 100 to the upper surface of the second light emitting layer 400, and the second light emitting layer 400 is further disposed in the second via 104 to be electrically connected to the second source 2023 or the second drain 2024.
In an embodiment, as shown in fig. 3, the substrate 100 includes a first region 101 and a second region 102, the second region 102 is disposed on at least one side of the first region 101, the first thin-film transistor layer 200 is disposed in the first region 101, and the display panel 00 further includes: a second thin-film transistor layer 600, where the second thin-film transistor layer 600 is disposed on the substrate 100, the second thin-film transistor layer 600 is located in the second region 102, the second thin-film transistor layer 600 and the first thin-film transistor layer 200 are disposed in the same layer, and the second thin-film transistor layer 600 includes a third thin-film transistor 601; a third light emitting layer 700, where the third light emitting layer 700 is disposed on a side of the second thin film transistor layer 600 far from the substrate 100, the third light emitting layer 700 is electrically connected to the third thin film transistor 601, and the third thin film transistor 601 controls a light emitting condition of the third light emitting layer 700.
The second thin film transistor layer 600 may include a plurality of third thin film transistors 601, the third light emitting layer 700 may include a plurality of third light emitting portions 701, and each of the third light emitting portions 701 is disposed opposite to a corresponding third thin film transistor 601. It can be understood that, since the third light-emitting layer 700 is also disposed on the side of the second thin-film transistor layer 600 far from the substrate 100, in order to achieve that the third light-emitting layer 700 and the first light-emitting layer 300 jointly display the same picture and improve the uniformity of the same picture, the third light-emitting layer 700 and the first light-emitting layer 300 may be disposed in the same layer; further, in order to make the resolution of the screen displayed by the first light emitting layer 300 the same as the resolution of the screen displayed by the third light emitting layer 700, the arrangement density of the plurality of third light emitting portions 701 and the arrangement density of the plurality of first light emitting portions 301 may be the same, and the sizes of the plurality of first light emitting portions 301 and the plurality of third light emitting portions 701 may be the same.
Specifically, the specific structure of the third thin film transistor 601 can refer to the related description of the first thin film transistor 201. Further, similar structures in the third thin film transistor 601, the first thin film transistor 301 and the second thin film transistor 401 can be manufactured at the same time, or even integrally formed.
In one embodiment, as shown in fig. 3, the display panel 00 further includes: the power module 402 is disposed on a side of the substrate 100 away from the second thin-film transistor layer 600, the power module 402 is located in the second region 102, and the power module 402 provides a working voltage to the first thin-film transistor layer 200 and the second thin-film transistor layer 600.
It is understood that the power module 402 may include a power source, a flexible circuit board, and the like, and the power module 402 may be electrically connected to voltage lines in the first thin-film transistor layer 200 and the second thin-film transistor layer 600, respectively, to maintain the normal operation of the thin-film transistors in the first thin-film transistor layer 200 and the second thin-film transistor layer 600.
In an embodiment, as shown in fig. 4, the display panel 00 further includes: the second planarization layer 800 is disposed on a side of the second thin film transistor layer 600 close to the third light-emitting layer 700, the second planarization layer 800 includes a third through hole 801, the third through hole 801 is opposite to the third thin film transistor 601, and the third light-emitting layer 700 is electrically connected to the third thin film transistor 601 through the third through hole 801.
In an embodiment, the second flat layer 800 and the first flat layer 500 are disposed in the same layer. It is understood that, since the second thin-film transistor layer 600 and the first thin-film transistor layer 200 are disposed at the same layer, after the second thin-film transistor layer 600 and the first thin-film transistor layer 200 are fabricated, the second planarization layer 800 and the first planarization layer 500 are fabricated on the second thin-film transistor layer 600 and the first thin-film transistor layer 200 at the same time, and further, the second planarization layer 800 and the first planarization layer 500 may be integrally formed.
In an embodiment, as shown in fig. 5, the substrate 100 further includes a third region 103, the third region 103 is located between the first region 101 and the second region 102, the third region 103 is used for bending the display panel 00, and the display panel 00 further includes: a bending layer 900, where the bending layer 900 is disposed on the substrate 100, the bending layer 900 is located in the third region 103, and the bending layer 900 and the second thin-film transistor layer 600 are disposed on the same layer.
Specifically, the bending layer 900, the first thin-film transistor layer 200, and the second thin-film transistor layer 600 are disposed on the same layer, and the thicknesses of the bending layer 900, the first thin-film transistor layer 200, and the second thin-film transistor layer 600 may be the same, and further, the upper surfaces and the lower surfaces of the bending layer 900, the first thin-film transistor layer 200, and the second thin-film transistor layer 600 may be on the same horizontal plane, so that the bending layer 900 may better protect the first thin-film transistor layer 200 and the second thin-film transistor layer 600.
In an embodiment, as shown in fig. 6, the display panel 00 further includes: a first buffer layer 901, where the first buffer layer 901 is disposed on one side of the substrate 100 close to the first thin-film transistor layer 200 and the second thin-film transistor layer 600, and the bending layer 900 may also be disposed on the first buffer layer 901; the first buffer layer 901 is arranged on one side of the substrate 100 close to the second light-emitting layer 400, and the second through hole 104 is further arranged on the first buffer layer 901 and the second buffer layer 902; a second pixel definition layer 903, the second pixel definition layer 903 being provided between two adjacent second light-emitting portions 401 to partition the two adjacent second light-emitting portions 401; a first pixel defining layer 904, the first pixel defining layer 904 being provided between two adjacent first light-emitting portions 301, between two adjacent third light-emitting portions 701, and between the adjacent first light-emitting portions 301 and the adjacent third light-emitting portions 701, for separating the adjacent two first light-emitting portions 301, the adjacent two third light-emitting portions 701, and the adjacent first light-emitting portions 301 and the adjacent third light-emitting portions 701; a first cover plate 905, wherein the first cover plate 905 is disposed on a side of the first light emitting layer 300 and the third light emitting layer 700 away from the substrate 100, and the first cover plate 905 is a flexible cover plate; a second cover plate 906, wherein the second cover plate 906 is arranged on the side of the second light-emitting layer 400 far away from the substrate 100, and the second cover plate 906 is a rigid cover plate.
The composition material of the first buffer layer 901 and the composition material of the second buffer layer 902 include, but are not limited to, inorganic materials such as silicon nitride and silicon oxide.
It is understood that, when the first light emitting layer 300 and the third light emitting layer 700 are respectively used for displaying a picture in different directions, the display panel 00 can be bent by the bending layer 900, and the first cover 905 is a flexible cover to facilitate bending of the display panel 00; moreover, the second cover 906 is a rigid cover, and can support the display panel 00 to prevent the display panel 00 from collapsing downward. It should be noted that the first cover 905 may be disposed in the first region 101 and the second region 102, and not disposed in the third region 103, so as to prevent the first cover 905 from falling off when the display panel 00 is bent.
Further, the second light emitting section 401 includes a second anode 4011 and a second organic layer 4012, wherein the second anode 4011 is disposed in the second via hole 104, and is disposed on a side of the second organic layer 4012 close to the second buffer layer 902; similarly, the first light emitting part 301 includes a first anode 3011 and a first organic layer 3012, the first anode 3011 is disposed in the first through hole 501 and is disposed on one side of the first organic layer 3012 close to the first passivation layer 500; similarly, the third light emitting part 701 includes a third anode 7011 and a third organic layer 7012, and the third anode 7011 is disposed in the third through hole 801 and on a side of the third organic layer 7012 close to the second passivation layer 800.
The embodiment of the present application provides a manufacturing method of a display panel, which includes, but is not limited to, the following embodiments and combinations of the following embodiments.
In one embodiment, as shown in FIG. 7, the method includes the following steps.
S10, providing a substrate.
The substrate may be a rigid substrate or a flexible substrate, the rigid substrate may be glass or a silicon wafer, and the flexible substrate may be a polymer material substrate, a metal foil substrate, an ultra-thin glass substrate, a polymer/inorganic substance substrate, or a polymer/organic substance/inorganic substance substrate, where the polymer material may include at least one of polyethylene, polypropylene, polystyrene, polyethylene terephthalate, polyethylene naphthalate, and polyimide.
And S20, forming a first thin film transistor layer on the substrate, wherein the first thin film transistor layer comprises a first thin film transistor and a second thin film transistor, and the first thin film transistor and the second thin film transistor are arranged in the same layer.
The first thin film transistor layer may include a plurality of first thin film transistors and a plurality of second thin film transistors, the first thin film transistors and the second thin film transistors may be alternately disposed, and a gap may be formed between adjacent first thin film transistors and adjacent second thin film transistors, so that the adjacent first thin film transistors and the adjacent second thin film transistors are electrically insulated.
Specifically, the first thin film transistor and the second thin film transistor may be thin film transistors of a top gate structure or thin film transistors of a bottom gate structure, and the specific structures of the first thin film transistor and the second thin film transistor may refer to the above description.
In an embodiment, before the step S20, the following steps may be included, but not limited to.
S101, forming a first buffer layer on the substrate, wherein the first buffer layer is arranged on one side of the substrate close to the first thin film transistor layer and the second thin film transistor layer.
Specifically, the first buffer layer may completely cover the region of the substrate opposite to the first thin-film transistor layer and the second thin-film transistor layer to achieve the buffer effect, and the composition material of the first buffer layer may refer to the above description.
In an embodiment, the substrate includes a first region and a second region, the second region is disposed on at least one side of the first region, and the first thin-film-transistor layer is located in the first region, which may include, but is not limited to, the following steps.
S201, forming a second thin film transistor layer on the substrate, wherein the second thin film transistor layer is located in the second area, the second thin film transistor layer and the first thin film transistor layer are arranged on the same layer, and the second thin film transistor layer comprises a third thin film transistor.
Specifically, the specific structure of the third thin film transistor can be referred to the above description. Further, the structures of the first thin film transistor, the second thin film transistor and the third thin film transistor may be the same, and the specific similar structures of the first thin film transistor, the second thin film transistor and the third thin film transistor may be prepared at the same time, or even integrally formed.
In an embodiment, the substrate further includes a third region, the third region is located between the first region and the second region, and the third region is used for bending the display panel, and the step S20 may further include, but is not limited to, the following steps.
S202, forming a bending layer on the substrate, wherein the bending layer is located in the third area, and the bending layer and the second thin film transistor layer are arranged on the same layer, even integrally formed.
In particular, the specific structure of the bending layer can be referred to the above description. Further, after the step S201, a via hole may be disposed in the gate insulating layer and the inter-insulating layer, and the bending layer may be formed in the via hole, and a constituent material of the bending layer may include, but is not limited to, an organic material, and it is understood that the organic material may have high elasticity to perform a bending function, so as to avoid the bending layer from being broken when bending.
S30, forming a first light emitting layer on a side of the first thin film transistor layer away from the substrate and a second light emitting layer on a side of the substrate away from the first thin film transistor layer, where the first light emitting layer is electrically connected to the first thin film transistor, the first thin film transistor controls a light emitting condition of the first light emitting layer, the second light emitting layer is electrically connected to the second thin film transistor, and the second thin film transistor controls a light emitting condition of the second light emitting layer.
It is to be understood that, since the first thin film transistor and the second thin film transistor control light emission of the first light emitting layer and the second light emitting layer, respectively, an arrangement of light emitting portions in the first light emitting layer and the second light emitting layer may be determined according to the arrangement of the first thin film transistor and the second thin film transistor.
As can be seen from the above, the first light-emitting layer may include a plurality of first light-emitting portions, the second light-emitting layer may include a plurality of second light-emitting portions, and the arrangement manner of the plurality of first light-emitting portions and the arrangement manner of the plurality of second light-emitting portions 401 may be referred to the above description.
In an embodiment, as shown in fig. 8, before the step S30, the following steps may be included, but are not limited to.
S203, forming a first flat layer on one side, close to the substrate, of the first thin film transistor layer, wherein the first flat layer comprises a first through hole, the first through hole is opposite to the first thin film transistor, and the first light-emitting layer is electrically connected with the first thin film transistor through the first through hole.
Specifically, the step S203 may include the following steps: forming a first flat layer on one side of the first thin film transistor layer close to the substrate, and forming a second flat layer on one side of the second thin film transistor layer close to the substrate, wherein the first flat layer comprises a first through hole, the first through hole is arranged opposite to the first thin film transistor, the first light-emitting layer is electrically connected with the first thin film transistor through the first through hole, the second flat layer comprises a third through hole, the third through hole is arranged opposite to the third thin film transistor, and the third light-emitting layer is electrically connected with the third thin film transistor through the third through hole.
In particular, the specific structure of the first and second flat layers may refer to the above description. It is understood that the first light-emitting portions are further disposed in the corresponding first through holes to electrically connect with the corresponding first thin film transistors, and the third light-emitting portions are further disposed in the corresponding third through holes to electrically connect with the corresponding third thin film transistors.
Further, the second flat layer and the first flat layer are disposed in the same layer and integrally formed, and the composition material of the first flat layer and the composition material of the second flat layer are the same, and may include, but not limited to, an organic material, for example.
And S204, forming a second through hole on the substrate, wherein the second through hole is opposite to the second thin film transistor, and the second light-emitting layer is electrically connected with the second thin film transistor through the second through hole.
Specifically, the specific position of the second through hole can be referred to the above related description. It can be understood that the second light emitting portions are further disposed in the corresponding second through holes to electrically connect with the corresponding second thin film transistors.
In an embodiment, the step S30 may include, but is not limited to, the following steps.
S301, forming a third light-emitting layer on one side of the first thin film transistor layer far away from the substrate, wherein the third light-emitting layer is electrically connected with the third thin film transistor, and the third thin film transistor controls the light-emitting condition of the third light-emitting layer.
As can be seen from the above, the third light emitting layer may include a plurality of third light emitting portions, and the plurality of third light emitting portions 301 may be arranged in the manner described above with reference to the related description.
In an embodiment, before the step S301, the following steps may be further included, but are not limited to.
And S300, forming a first pixel defining layer on one side of the first thin film transistor layer far away from the substrate, wherein the first pixel defining layer is used for separating two adjacent first light-emitting parts, two adjacent third light-emitting parts and the first light-emitting part and the third light-emitting part which are adjacent.
Wherein, the composition material of the first pixel definition layer includes but is not limited to organic material.
In an embodiment, the step S30 may further include, but is not limited to, the following steps.
And S302, forming a light resistance layer on the first light emitting layer, the third light emitting layer and the first pixel defining layer on the side far away from the substrate.
Wherein, the composition material of the photoresist layer can refer to the composition material of the polymer material substrate in the substrate. It is understood that the light blocking layer may protect the first light emitting layer, the third light emitting layer and the first pixel defining layer, and when the substrate is processed on a side away from the first buffer layer, the first thin film transistor layer and the first pixel defining layer may be prevented from being damaged.
And S303, forming a second buffer layer on one side of the substrate close to the second light-emitting layer.
Specifically, the second buffer layer may completely cover a region of the substrate opposite to the second light emitting layer to achieve a buffering effect, and the composition material of the second buffer layer may be referred to the above description.
And S304, forming the second through hole on the second buffer layer.
It is to be understood that, after the second buffer layer is formed, the second via hole may be formed again on the partial region of the second thin film transistor, the substrate, and the second buffer layer.
And S305, forming a second pixel defining layer on one side, far away from the substrate, of the second buffer layer, wherein the second pixel defining layer is used for separating two adjacent second light emitting parts.
Wherein the constituent material of the second pixel defining layer includes, but is not limited to, an organic material.
S306, removing the light resistance layer, and forming the first light-emitting layer and the third light-emitting layer on the side of the first thin film transistor layer far away from the substrate, and forming the second light-emitting layer on the side of the substrate far away from the first thin film transistor layer.
It can be understood that the light blocking layer has an insulating property, and therefore, the first light emitting layer and the second light emitting layer can be fabricated only after the light blocking layer is removed, so that the first light emitting layer is electrically connected to the first thin film transistor, the second light emitting layer is electrically connected to the second thin film transistor, and the third light emitting layer is electrically connected to the third thin film transistor.
And S307, forming a first cover plate on one side of the first light-emitting layer and the third light-emitting layer, which is far away from the substrate, and forming a second cover plate on one side of the second light-emitting layer, which is far away from the substrate, wherein the first cover plate is a flexible cover plate, and the second cover plate is a rigid cover plate.
It can be understood that, when the first light emitting layer and the third light emitting layer are respectively used for displaying a picture in different directions, the display panel can be bent by the bending layer, and the first cover plate is a flexible cover plate, which facilitates bending of the display panel; also, the second cover 906 is a rigid cover that can support the display panel to prevent the display panel from collapsing downward. It should be noted that the first cover plate may be disposed in the first region and the second region, and is prevented from being disposed in the third region, which may cause the first cover plate to fall off when the display panel is bent.
It is understood that step S307 may further include: and forming a power supply module on one side of the substrate far away from the second thin film transistor layer, wherein the power supply module is positioned in the second area and provides working voltage for the first thin film transistor layer and the second thin film transistor layer.
It is understood that the step S307 may further include: and a first polaroid and a first protective film are sequentially arranged on one side, far away from the substrate, of the first cover plate, and a second polaroid and a second protective film are sequentially arranged on one side, far away from the substrate, of the second cover plate, so that corresponding functions are realized.
The application provides a display panel and a manufacturing method thereof, wherein the display panel comprises: a substrate; the first thin film transistor layer is arranged on the substrate and comprises a first thin film transistor and a second thin film transistor which are arranged on the same layer; the first light-emitting layer is arranged on one side, far away from the substrate, of the first thin film transistor layer and is electrically connected with the first thin film transistor, and the first thin film transistor controls the light-emitting condition of the first light-emitting layer; and the second light-emitting layer is arranged on one side of the substrate, which is far away from the first thin film transistor layer, and is electrically connected with the second thin film transistor, and the second thin film transistor controls the light-emitting condition of the second light-emitting layer. According to the display device, the first thin film transistor used for controlling the light emitting condition of the first light emitting layer and the second thin film transistor used for controlling the light emitting condition of the second light emitting layer are arranged on the same layer, so that the two display panels are prevented from being assembled to realize double-sided display after being manufactured respectively, and the light weight, the light weight and the cost performance of the display are improved while the double-sided display is realized.
The display panel and the manufacturing method thereof provided by the embodiment of the present application are introduced in detail, and a specific example is applied to illustrate the principle and the embodiment of the present application, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (9)
1. A display panel, comprising:
the substrate comprises a first area and a second area, wherein the second area is arranged on at least one side of the first area;
the first thin film transistor layer is arranged on the substrate and is arranged in the first area, the first thin film transistor layer comprises a first thin film transistor and a second thin film transistor, and the first thin film transistor and the second thin film transistor are arranged on the same layer;
the first light-emitting layer is arranged on one side, far away from the substrate, of the first thin film transistor layer and is electrically connected with the first thin film transistor, and the first thin film transistor controls the light-emitting condition of the first light-emitting layer;
the second light-emitting layer is arranged on one side of the substrate far away from the first thin film transistor layer, the second light-emitting layer is electrically connected with the second thin film transistor, and the second thin film transistor controls the light-emitting condition of the second light-emitting layer;
the second thin film transistor layer is arranged on the substrate and is arranged in the second area, the second thin film transistor layer and the first thin film transistor layer are arranged in the same layer, and the second thin film transistor layer comprises a third thin film transistor;
and the third light-emitting layer is arranged on one side of the second thin film transistor layer far away from the substrate, and is electrically connected with the third thin film transistor, and the third thin film transistor controls the light-emitting condition of the third light-emitting layer.
2. The display panel according to claim 1, characterized in that the display panel further comprises:
the first flat layer is arranged on one side, close to the first light-emitting layer, of the first thin film transistor layer and comprises a first through hole, the first through hole is opposite to the first thin film transistor, and the first light-emitting layer is electrically connected with the first thin film transistor through the first through hole;
the second through hole is formed in the substrate, the second through hole is opposite to the second thin film transistor, and the second light emitting layer is electrically connected with the second thin film transistor through the second through hole.
3. The display panel according to claim 2, characterized in that the display panel further comprises:
the second flat layer is arranged on one side, close to the third light-emitting layer, of the second thin film transistor layer and comprises a third through hole, the third through hole is opposite to the third thin film transistor, and the third light-emitting layer is electrically connected with the third thin film transistor through the third through hole.
4. The display panel according to claim 3, wherein the second flat layer and the first flat layer are disposed in the same layer.
5. The display panel according to claim 1, wherein the substrate further comprises a third region, the third region being located between the first region and the second region, the third region being used to bend the display panel, the display panel further comprising:
and the bending layer is arranged on the substrate, the bending layer is positioned in the third area, and the bending layer and the second thin film transistor layer are arranged in the same layer.
6. The display panel according to claim 1, characterized in that the display panel further comprises:
the power module is arranged on one side of the substrate far away from the second thin film transistor layer, the power module is located in the second area, and the power module provides working voltage for the first thin film transistor layer and the second thin film transistor layer.
7. The display panel according to claim 1, wherein the first light-emitting layer includes a plurality of first light-emitting portions, the second light-emitting layer includes a plurality of second light-emitting portions, the third light-emitting layer includes a plurality of third light-emitting portions, an arrangement density of the plurality of second light-emitting portions is the same as or different from an arrangement density of the plurality of first light-emitting portions, and an arrangement density of the plurality of third light-emitting portions is the same as the arrangement density of the plurality of first light-emitting portions.
8. A method for manufacturing a display panel, for preparing the display panel according to any one of claims 1 to 7, the method comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, and the second area is arranged on at least one side of the first area;
forming a first thin film transistor layer and a second thin film transistor layer which are arranged in the same layer on the substrate, wherein the first thin film transistor layer is arranged in the first area, the second thin film transistor layer is arranged in the second area, the first thin film transistor layer comprises a first thin film transistor and a second thin film transistor, the first thin film transistor and the second thin film transistor are arranged in the same layer, and the second thin film transistor layer comprises a third thin film transistor;
the light-emitting device comprises a substrate, a first thin film transistor, a second thin film transistor, a first light-emitting layer, a second light-emitting layer and a third light-emitting layer, wherein the first light-emitting layer is formed on one side, far away from the substrate, of the first thin film transistor layer, the second light-emitting layer is formed on one side, far away from the first thin film transistor layer, of the substrate, the third light-emitting layer is formed on one side, far away from the substrate, of the second thin film transistor layer, the first light-emitting layer is electrically connected with the first thin film transistor, the first thin film transistor controls the light-emitting condition of the first light-emitting layer, the second light-emitting layer is electrically connected with the second thin film transistor, the second thin film transistor controls the light-emitting condition of the second light-emitting layer, the third light-emitting layer is electrically connected with the third thin film transistor, and the third thin film transistor controls the light-emitting condition of the third light-emitting layer.
9. The method of claim 8, wherein before the step of forming a first light-emitting layer on a side of the first thin-film transistor layer away from the substrate and forming a second light-emitting layer on a side of the substrate away from the first thin-film transistor layer, the first light-emitting layer being electrically connected to the first thin-film transistor, the first thin-film transistor controlling light emission of the first light-emitting layer, the second light-emitting layer being electrically connected to the second thin-film transistor, the second thin-film transistor controlling light emission of the second light-emitting layer, the method comprises:
forming a first flat layer on one side of the first thin film transistor layer close to the substrate, wherein the first flat layer comprises a first through hole, the first through hole is arranged opposite to the first thin film transistor, and the first light-emitting layer is electrically connected with the first thin film transistor through the first through hole;
and forming a second through hole on the substrate, wherein the second through hole is opposite to the second thin film transistor, and the second light-emitting layer is electrically connected with the second thin film transistor through the second through hole.
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| CN115117135A (en) * | 2022-06-28 | 2022-09-27 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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| EP3471145A1 (en) * | 2017-10-13 | 2019-04-17 | Samsung Display Co., Ltd. | Display panel and method of fabricating the same |
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| KR102207063B1 (en) * | 2012-12-12 | 2021-01-25 | 엘지디스플레이 주식회사 | Thin film transistor, method for manufacturing the same and display device comprising the same |
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| KR20100091781A (en) * | 2009-02-11 | 2010-08-19 | 삼성전자주식회사 | Thin film transistor panel and manufacturing method thereof |
| EP3471145A1 (en) * | 2017-10-13 | 2019-04-17 | Samsung Display Co., Ltd. | Display panel and method of fabricating the same |
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