CN112086124A

CN112086124A - Double-rate test mode parameter configuration method and storage medium

Info

Publication number: CN112086124A
Application number: CN202010894529.8A
Authority: CN
Inventors: 马力
Original assignee: Lan Zhi Ic Suzhou Co ltd
Current assignee: Lan Zhi Ic Suzhou Co ltd
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2020-12-15
Anticipated expiration: 2040-08-31
Also published as: CN112086124B

Abstract

The application discloses a double-rate test mode parameter configuration method and a storage medium. The method comprises the following steps: configuring a test voltage of a chip of a memory to be tested; configuring a time sequence signal of a chip of the memory to be tested; defining a format of the timing signal; establishing an algorithm model according to the test voltage, the time sequence signal and the format; and configuring the error catcher. The test requirements of the double data rate mode are met through voltage configuration, time sequence configuration, format configuration, model configuration, error trapping memory configuration and the like. The DDR mode is designed for high-speed testing of the memory chip, the testing speed can reach 400Mhz at most in the DDR testing mode, and the testing speed is 2 times that of SDR.

Description

Double-rate test mode parameter configuration method and storage medium

Technical Field

The present invention relates to computer technologies, and in particular, to a double rate test mode parameter configuration method and a storage medium.

Background

The test procedure of the existing memory is performed in a Single Data Rate (SDR) mode. Although the SDR mode can meet the test requirements of most chips, the read-write speed of some Nand flash or Nor flash can reach 260Mhz, and the SDR mode cannot meet the test of more than 200 Mhz.

Disclosure of Invention

The embodiment of the application provides a double-rate test mode parameter configuration method and a storage medium, and effectively solves the problem that some memories have too high read-write speed and cannot be tested in a single-data-rate mode.

According to an aspect of the present application, an embodiment of the present application provides a double rate test mode parameter configuration method, including: configuring a test voltage of a chip of the memory to be tested; configuring a time sequence signal of a chip of the memory to be tested; defining a format of the timing signal; establishing an algorithm model according to the test voltage, the time sequence signal and the format; and configuring the error catcher.

Further, in the step of configuring the test voltage of the chip of the memory to be tested, the method further comprises the steps of: configuring the input voltage of a pin of the memory chip to be tested; configuring the output voltage of the pin of the memory chip to be tested; and configuring a load current loaded on a pin of the memory chip to be tested.

Further, the input voltage comprises a first input voltage and a second input voltage, the first input voltage is 0.9 times of the power supply voltage, and the second input voltage is 0.1 times of the power supply voltage; the output voltage comprises a first output voltage and a second output voltage, and the first output voltage and the second output voltage are both 0.5 times of the power supply voltage; the load current comprises a first load current and a second load current, wherein the first load current is-100 uA, and the second load current is 100 uA.

Further, in the step of configuring the timing signal of the memory chip to be tested, the method further comprises the steps of: dividing one clock cycle into a first timing signal and a second timing signal; the first timing signal is used for controlling corresponding first cycle data, and the second timing signal is used for controlling corresponding second cycle data; the levels and times of the first and second timing signals are determined according to driving methods, data acquisition, and timing edges.

Further, the formats of the timing signal include a first format and a second format; wherein the waveform of the first format in the first timing signal corresponds to the first data and the waveform in the second timing signal corresponds to the second data; the second format has four pulse signals within one clock cycle.

Further, in the step of establishing an algorithm model, the method further comprises the steps of: generating the address, data and format of the algorithm model generator; when the control operation is executed on the algorithm model generator, the algorithm model generator executes corresponding jump when a preset condition is met; and the timer of the algorithm model generator performs counting operation.

Further, in the step of configuring the error catcher, further comprising the steps of: generating the size of an X address and the size of a Y address according to the storage capacity of a memory chip to be tested; compressing the X address and the Y address to generate column data; and judging the row data generating errors according to the column data.

Further, the maximum value of the X address and the Y address does not exceed 24.

Further, after the step of compressing the X address and the Y address, the method further comprises the steps of: and generating matrix addresses corresponding to the X address and the Y address according to the row data generating errors.

According to another aspect of the present application, an embodiment of the present application provides a storage medium having a plurality of instructions stored therein, the instructions being adapted to be loaded by a processor to perform any of the double rate test mode parameter configuration methods described above.

Compared with the prior art, the method has the advantages that the test requirements of a Double Data Rate (DDR) mode are met through voltage configuration, time sequence configuration, format configuration, model configuration, error capturing memory configuration and the like. The DDR mode is aimed at high-speed test of a memory chip, and under the DDR test mode, the test speed can reach 400Mhz at most, namely the period is 2.5 ns. Through the design of the DDR test environment, the test result of the DDR mode can meet the actual requirement, and the highest speed of the DDR mode test can be 2 times of that of the SDR.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a flowchart illustrating a double rate test mode parameter configuration method according to an embodiment of the present application.

Fig. 2 is a flowchart illustrating sub-steps of step S110 in the embodiment described in the present application.

Fig. 3 is a flowchart illustrating sub-steps of step S120 in the embodiment described in the present application.

Fig. 4 is a flowchart illustrating the sub-steps of step S140 in the embodiment described in the present application.

Fig. 5 is a flowchart illustrating the sub-steps of step S150 in the embodiment described in the present application.

Fig. 6 is a schematic view of a load configuration structure provided in the embodiment of the present application.

Fig. 7 is a schematic structural diagram of a storage medium provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate. In this embodiment, the analog display screen touch unit is connected to the head tracking unit, and is configured to acquire a moving path of a sensing cursor in the display device.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

As shown in fig. 1, a flowchart of the steps of a double data rate test mode parameter configuration method provided in the embodiment of the present application is provided, where the method includes the steps of:

step S110: and configuring the test voltage of the chip of the memory to be tested.

Referring to fig. 2, step S110 specifically includes the following steps.

Step S111: the input voltage of the pins of the memory chip.

In this embodiment, the input voltage includes a first input voltage and a second input voltage, the first input voltage is 0.9 times of the power supply voltage, and the second input voltage is 0.1 times of the power supply voltage.

Step S112: and configuring the output voltage of the pin of the memory chip to be tested.

In this embodiment, the output voltage includes a first output voltage and a second output voltage, and both the first output voltage and the second output voltage are 0.5 times of the power voltage.

Step S113: and configuring the load current loaded on the pin of the memory chip to be tested.

In this embodiment, the load current includes a first load current and a second load current, the first load current is-100 uA, and the second load current is 100 uA. Referring to fig. 6, specifically, during the DDR function test, a load needs to be loaded on the IO pin to increase the data output speed, and when the load mainly acts, the level of the IO pin is in a tri-state, for example, the DPS voltage is 3V, and the level of the IO pin is kept at 1.5V. This is convenient whether the output is high or low. The pins are driven to tri-state by adding an IOL and IOH to the pins. Each pin has a PE diode bridge load for dynamically loading the device pin with current during functional test execution. In order for the output driver of the device under test to be able to drive a specified load, the pins need to be loaded with the IOL/IOH values specified by the specification. IOH is the output of drive current from the memory to the diode bridge load current. The IOL is the output load current flowing from the diode bridge into the memory. When the function test is output, two levels, namely a high level and a low level, are generated on an IO pin, the high level is judged by comparing the output level with VOH, and if the output voltage is higher than VOH, the high level is judged. The low level is determined by comparing the output level with VOL, and if the output voltage is lower than VOL, it is determined as low level. The IOH and the IOL need to give current values according to specifications when the memory pins and the tester pins of the memory are in three states, VZ is the compensation voltage of the diode bridge, and the magnitude of the VZ is determined by the load current. When no current flows into or out of the memory, the diode bridge will remain balanced and the value of VZ is the programmed set value. The device must drive voltages greater than VZ through IOH to make the output high level more stable, and must also receive IOLs to drive voltages less than VZ to make the output low level more stable.

Step S120: and configuring a time sequence signal of a chip of the memory to be tested.

Referring to fig. 3, step S120 specifically includes the following steps.

Step S121: one clock cycle is divided into a first timing signal and a second timing signal.

In this embodiment, the first timing signal is used for controlling corresponding first cycle data, and the second timing signal is used for controlling corresponding second cycle data. The levels and times of the first and second timing signals are determined according to driving methods, data acquisition, and timing edges.

Step S130: a format of the timing signal is defined.

In this embodiment, the formats of the timing signal include a first format and a second format. The waveform of the first format in the first timing signal corresponds to first data, the waveform of the second format in the second timing signal corresponds to second data, and the second format has four pulse signals in one clock period.

Step S140: and establishing an algorithm model according to the test voltage, the time sequence signal and the format.

Referring to fig. 4, step S140 specifically includes the following steps.

Step S141: and generating the address, data and format of the algorithm model generator.

Step S142: when the control operation is performed on the algorithm model generator, the algorithm model generator performs a corresponding jump when a preset condition is satisfied.

Step S143: and the timer of the algorithm model generator performs counting operation.

Step S150: an error catcher is configured.

Referring to fig. 5, the step S150 specifically includes the following steps.

Step S151: and generating the sizes of the X address and the Y address according to the storage capacity of the memory chip to be tested.

In the present embodiment, the size of the X address, the size of the Y address is configured according to the memory capacity of the chip under test. The maximum values of X and Y are 24, and the sum of X + Y cannot be greater than 40.

Step S152: compressing the X and Y addresses generates column data.

In this embodiment, the X/Y address compression function is applied, and when an error occurs in the X/Y address, the error is ignored, and the error catcher does not grab the error. For example, when an error occurs in each of the X/Y addresses, X is 0xFF35 (binary 0X 1111111100110101), Y is 0xFF53 (binary 0X 1111111101010011), X1, X3, X6, X7, Y2, Y3, Y5, and Y7, the X/Y addresses are ignored by the error catcher.

Step S153: and judging the row data generating errors according to the column data.

In this embodiment, since the memory is a matrix composed of X and Y, when the test is completed, the generated error catcher also appears in a matrix form. It should be noted that, data compression compresses multiple columns of data into one column, and the generated new data format is that if there is an error in one of multiple columns, the error is marked at the same position of the column.

Step S154: from the error-producing data, matrix addresses corresponding to the X and Y addresses are generated.

In the present embodiment, the multi-line data compression is the same as the single-line data compression, and only one error in the multi-line data is marked as an error at the same position in the generated new line. The benefit of data compression is to change a large matrix into a small matrix so that the approximate location of the error can be clearly seen.

As shown in fig. 7, the present application provides a storage medium, in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any double rate test mode parameter configuration method provided in the present application.

Wherein the storage medium may include: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.

Since the instructions stored in the storage medium may execute the steps in any double rate test mode parameter configuration method provided in the embodiment of the present application, beneficial effects that can be achieved by any double rate test mode parameter configuration method provided in the embodiment of the present application may be achieved, for details, see the foregoing embodiment, and are not described herein again.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The principle and the implementation of the present application are explained by applying specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A double-rate test mode parameter configuration method is suitable for a memory to be tested, and is characterized by comprising the following steps:

configuring a test voltage of a chip of the memory to be tested;

configuring a time sequence signal of a chip of the memory to be tested;

defining a format of the timing signal;

establishing an algorithm model according to the test voltage, the time sequence signal and the format; and

an error catcher is configured.

2. The double data rate test mode parameter configuration method as claimed in claim 1, wherein in the step of configuring the test voltage of the chip of the memory to be tested, further comprising the steps of:

configuring the input voltage of a pin of the memory chip to be tested;

configuring the output voltage of the pin of the memory chip to be tested; and

and configuring the load current loaded on the pin of the memory chip to be tested.

3. The double-data-rate-test-mode parameter configuration method of claim 2, wherein the input voltage comprises a first input voltage and a second input voltage, the first input voltage is 0.9 times the power supply voltage, and the second input voltage is 0.1 times the power supply voltage;

the output voltage comprises a first output voltage and a second output voltage, and the first output voltage and the second output voltage are both 0.5 times of the power supply voltage;

the load current comprises a first load current and a second load current, wherein the first load current is-100 uA, and the second load current is 100 uA.

4. The double data rate test mode parameter configuration method of claim 1, wherein in the step of configuring the timing signals of the memory chip to be tested, further comprising the steps of:

dividing one clock cycle into a first timing signal and a second timing signal;

the first timing signal is used for controlling corresponding first cycle data, and the second timing signal is used for controlling corresponding second cycle data; the levels and times of the first and second timing signals are determined according to driving methods, data acquisition, and timing edges.

5. The double-data-rate test mode parameter configuration method of claim 1, wherein the formats of the timing signals comprise a first format and a second format;

wherein the waveform of the first format in the first timing signal corresponds to the first data and the waveform in the second timing signal corresponds to the second data;

the second format has four pulse signals within one clock cycle.

6. The double-data-rate test mode parameter configuration method according to claim 1, wherein in the step of establishing an algorithm model, further comprising the steps of:

generating the address, data and format of the algorithm model generator;

when the control operation is executed on the algorithm model generator, the algorithm model generator executes corresponding jump when a preset condition is met; and

and the timer of the algorithm model generator performs counting operation.

7. The double data rate test mode parameter configuration method of claim 1, wherein in the step of configuring the error catcher, further comprising the steps of:

generating the size of an X address and the size of a Y address according to the storage capacity of a memory chip to be tested;

compressing the X address and the Y address to generate column data;

and judging the row data generating errors according to the column data.

8. The double-data-rate test mode parameter configuration method of claim 7, wherein the maximum value of the X address and the Y address does not exceed 24.

9. The double data rate test mode parameter configuration method of claim 7, wherein after the step of determining the row data generating the error according to the column data, further comprising the steps of:

and generating matrix addresses corresponding to the X address and the Y address according to the row data generating errors.

10. A storage medium having stored therein a plurality of instructions adapted to be loaded by a processor to perform the double data rate test mode parameter configuration method of any of claims 1 to 9.