CN112072899B - Driving method for realizing dynamic current sharing of parallel IGBTs by asynchronously controlling gate signals - Google Patents
Driving method for realizing dynamic current sharing of parallel IGBTs by asynchronously controlling gate signals Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
- H02M1/092—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the control signals being transmitted optically
Abstract
The invention relates to a driving method for realizing parallel IGBT dynamic current sharing by asynchronously controlling gate signals, which comprises the steps of determining a behavior model of IGBT switching process control quantity and a control target, acquiring initial time delay of each branch IGBT switching process, setting average time delay, adjusting pulse trigger time sequence of each branch, and issuing set time delay data by an upper computer to realize asynchronous gate triggering. A behavior model for controlling the switching process by time delay is established, a reliable theoretical basis is provided for a control mode of adjusting the gate pulse to promote the dynamic current sharing characteristic of the parallel IGBT, and more detailed switching process adjustment is realized. Collecting and counting relevant data of the IGBT time delay parameters and the current difference of each branch circuit, providing a reference for time delay control and realizing more effective gate control; the dynamic current-sharing characteristic is adjusted from the angle of gate delay control, the design and manufacturing cost of high-power hardware in the aspect of current-sharing characteristic optimization is reduced, and the flexibility of current-sharing control is improved.
Description
Technical Field
The invention relates to the field of power electronics and power transmission, in particular to a driving method for realizing dynamic current sharing of parallel IGBTs by asynchronously controlling gate signals.
Background
With the continuous improvement of current capacity of modern converter systems, a single semiconductor device cannot meet the requirement of the modern converter systems, and compared with the parallel connection of a plurality of converters for realizing current capacity expansion, the parallel connection application of the switching devices is widely concerned due to the economy and feasibility of the switching devices. Due to the difference between the control signal and the drive loop parameter, the gate voltages between the parallel IGBTs cannot be kept consistent at the switching time, so that the dynamic balance of the collector current is influenced, the IGBT which is switched on earlier or has higher current rising rate bears larger current in the switching-on process, the IGBT which is switched off later or has lower current falling rate bears larger current in the switching-off process, along with the accumulation of junction temperature and the aging of devices, the difference between the parallel IGBTs is further increased, and the stability and the reliability of the system face higher risks.
Taking the turn-on process of two IGBTs in parallel as an example, FIG. 1-1 shows the collector current (i)C1And iC2) A simplified equivalent circuit in the rising process, which mainly corresponds to 0-t in the turn-on process of the parallel IGBT in the figure 1-221(or 0 to t)22) Phase of IGBT gate voltage (v)GE) And collector current (i)C) This can be expressed by the following formula:
wherein, VG,offAnd VG,onFor the IGBT a stable value of the output voltage, V, of the drive circuit in the off and on states, respectivelyGE(th)Is the turn-on threshold of the IGBT gate, Cies＝CGE+CGCIs an input capacitance, RGFor gate resistance, K is the equivalent transconductance, assuming V in FIGS. 1-1-2G1＝VG2＝VG。
As can be seen from equations (1) and (2) and fig. 1-1 and 1-2, even if the output voltages of the driving circuits to which the parallel IGBTs belong are the same, the difference in the driving loop parameters still affects the dynamic balance of the collector currents of the IGBTs by the gate voltage.
The existing research aiming at IGBT parallel dynamic current sharing has the following contents and is worth noting:
fig. 2 is a master-slave structure type parallel driving mode, a control signal and a fault signal of a parallel IGBT are received and returned by a master driver through an optical fiber, a power supply is obtained by the master driver and becomes a stable driving power supply through a DC-DC circuit, and then electric quantities such as the same as the control signal and the like reach adjacent slave drivers through electric interfaces X2 and X3, the control signal becomes a driving voltage through a power amplifying circuit when reaching each driver and is applied to a gate (G) of each parallel IGBT, and the master driver and the slave drivers can effectively reduce delay difference generated in the transmission process of the control signal through short-distance connection established by the electric interfaces, so that the simultaneity of the driving signal is improved.
Although the method can reduce the difference of the control signals input by the driving circuits corresponding to the parallel IGBTs in the aspect of transmission delay, the method cannot inhibit the internal parameters of the parallel IGBTs and the inconsistency generated by junction temperature change and aging in the operation process, and in order to inhibit the delay difference generated by the control signals of the drivers in the transmission and power amplification processes, each chip in the driving circuits needs to have smaller processing delay, and has certain requirements on the fluctuation range of the delay.
FIG. 3 is a driving method that can be extended to the parallel connection of N (N ≧ 3) IGBTs by applying collector currents (i) to each parallel IGBT during turn-on and turn-offC) Collector-emitter voltage (v)CE) Or auxiliary emitter-power emitter voltage (v)eE) The switching time of each IGBT in the current switching period is obtained after collection, the switching time is returned to an upper computer (such as an FPGA) with higher processing speed for sorting, the delay required to be introduced by each parallel IGBT control signal is obtained through a compensation algorithm, the control signal of each drive introducing delay compensation is sent to each drive when the next switching period comes, and the dynamic imbalance degree of collector current of each parallel IGBT is limited within an expected range by adjusting each drive delay for multiple times.
The method currently uses the power emitter voltage (v)eE) As a test IGBT is the main criterion in the turn-on and turn-off process due to v in the turn-on and turn-off processEeAre opposite, the requirements are put on the number or the functions of the corresponding detection circuits, and the IGBT short-circuit protection needs to be carried out on vEeAnd vCEThe two carry out detection, and the detection circuits further occupy the space of the adapter board.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a driving method for realizing dynamic current sharing of parallel IGBTs by asynchronously controlling gate signals, which can realize the following purposes:
(1) on the premise of ensuring the power supply reliability and the drive protection function of each parallel IGBT driver, the difference of each parallel IGBT control signal in transmission delay is restrained, and the dynamic current-sharing characteristic of the parallel IGBT can be improved in a delay compensation mode;
(2) the method can effectively reduce the occupation of the corresponding detection circuit in parallel current sharing and short-circuit protection on the drive board space, and improve the utilization rate of the detection circuit.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows:
a driving method for realizing parallel IGBT dynamic current sharing by asynchronously controlling gate signals comprises the following steps:
(1) determining a behavior model of the IGBT switching process control quantity and the control target:
establishing a driving loop RC or RLC full response equation in the switching process, and then combining an IGBT behavior model to obtain a control model of a gate driving signal to the IGBT collector current;
the turn-on process of the IGBT is divided into three stages of turn-on delay, current rise and voltage drop,
in the on-delay stage, the collector current is zero and the parasitic inductance L is ignoredEiThe gate voltage expression, V, is obtained from the formula (1)G,offIs raised to VGE(th)The time required, i.e. the on-delay time td(on)Calculated by the formulas (3) and (4):
in the formula: vG,offAnd VG,onFor the IGBT a stable value of the output voltage, V, of the drive circuit in the off and on states, respectivelyGE(th)Is the turn-on threshold of the IGBT gate, Cies＝CGE+CGCIs an input capacitance, CGEIs a gate emitter capacitor, CGCIs a Miller capacitance, RGIs the gate resistance, vGEIs the gate voltage of IGBT iCIs the collector current, V, of the IGBTGE(th)Turn-on threshold, v, for the gate of an IGBTGE(t) the gate voltage in this stage is set to be VG,off(time 0) starts to increase to the gate voltage value corresponding to time t, wherein t is the gate voltage in the period from V to VG,offIncrease to vGE(t) elapsed time;
during the current rise phase when vGEReach the cut-on threshold VGE(th)Rear, collector current iCStarting to rise, taking into account the parasitic inductance LEiThe gate voltage equation is shown as the formula (1), and the collector current (1/n) · I of a single tube in the current rising stage of the n parallel IGBTs is obtained by the formula (5)LTime t required for risingd(cr)；
Wherein:
△VGE＝VGE(pl)-VGE(th) (6)
VGE(ave)＝0.5·[VGE(pl)+VGE(th)] (7)
in the formula: delta VGEIs the change of the gate voltage during the current rise, VGE(ave)Is the average of the Miller plateau and the opening threshold, VGE(pl)In order to be a miller platform,
according to the formulas (4) and (5), a gate delay control compensation behavior model is established, and the gate delay compensation is realized to realize the balanced control of the current difference in the opening process;
for the turn-off process, the turn-off delay and voltage rise stages are mainly divided;
in the turn-off delay stage, the driving voltage is changed from VG,onBecomes VG,offThen, the input capacitor starts to discharge, the gate voltage is reduced to the gate voltage corresponding to the collector current of the IGBT in the active region, the collector voltage starts to rise, and the gate voltage is maintained at the Miller platform V againGE(pl)In the vicinity, the gate voltage is represented by the equation (8):
the time required to complete this phase, i.e. the turn-off delay time td(off)As shown in formula (9):
collector-emitter voltage rising stage: at this stage, after the gate voltage is reduced to the gate voltage corresponding to the collector current of the IGBT in the active region, the collector voltage starts to rise and the gate voltage is maintained at the Miller platform V againGE(pl)Nearby, when the collector current is large, the change rate of the collector-emitter voltage in the behavior model is used for obtaining the time t required for the collector-emitter voltage to rise from the on-state saturation voltage drop to the direct-current side voltage in the voltage rising staged(vr)As shown in formula (10):
in the formula, CGC(sat)Maintaining the corresponding miller capacitance value when the on-state saturation voltage drop is maintained for the collector-emitter voltage;
according to the formulas (9) and (10), a gate delay control compensation behavior model is established, and the gate delay compensation is realized to realize the balanced control of the current difference in the turn-off process;
(2) acquiring initial time delay of each branch IGBT switching process:
the judgment of the state of the IGBT on/off process is mainly based on the detection of the voltage quantity, and for the on process, the voltage v of a power emitter is usedeEThe rising edge when the zero voltage rises to the peak value corresponds to the current rising stage, and the upper computer starts timing when sending a switching-on control signal to a driving circuit of each IGBT and starts timing by v pairseECollected and compared with a reference value Vref1After comparison, taking the rising edge of the pulse signal output by the comparator as a criterion for time recording ending, thereby obtaining time delay relevant to the turn-on delay stage and the current rising stage of each parallel IGBT;
for the detection of the state of the turn-off process, the upper computer starts to time after sending a turn-off control signal to use the voltage v of the collector and the emitterCEThe rising edge when the on-state saturation voltage rises to the bus voltage corresponds to the voltage rising stage by vCECollected and compared with a reference value Vref2After comparison, taking the rising edge of the pulse signal output by the comparator as a criterion for timing ending, thereby obtaining the time delay related to the turn-off delay stage and the voltage rising stage of each parallel IGBT;
(3) setting average delay time, and adjusting pulse trigger time sequence of each branch:
through the acquisition of the states of the IGBT turn-on/turn-off process and the time delay of the corresponding stage in the step (2), each IGBT drive board transmits relevant time delay information to an upper computer through an optical fiber signal for time delay adjustment of a control signal of the next switching process, therefore, a reference control signal needs to be selected to obtain the lead-lag time of each IGBT gate signal, and the following modes can be considered for the selection of the reference control signal: selecting the IGBT with the current closest to the average current as a reference, and introducing time delay to other branches for control, namely an average time delay asynchronous driving control mode;
(4) the upper computer sends down the set delay data to realize the asynchronous gate trigger:
the upper computer obtains the lead-lag time of each IGBT gate signal through data processing and then adjusts the gate trigger time sequence to act on the next switching process so as to improve the dynamic current sharing of the parallel IGBTs.
On the basis of the scheme, VGE(th)The method comprises the steps of obtaining through a mode of building a test circuit.
Based on the above scheme, the gate emitter capacitor CGECalculated by equation (11):
on the basis of the scheme, VGE(pl)The solution is performed by equation (2):
in the formula (2), iC＝(1/n)ILSolving for v in the second line of equation (2)GETo obtain VGE(pl)For the parameter K in the formula (2), the parameter K is obtained by substituting the value in the transmission characteristic curve in the formula (2), and the transmission characteristic curve is obtained by referring to a data manual or building a test circuit.
On the basis of the scheme, the parasitic inductance LEiThe acquisition comprises the steps of firstly building a Buck circuit, testing the IGBT in an on state under low bus voltage and low load inductance, and acquiring collector current iCCollector voltage VCcAnd a power emitter voltage VeEThe parasitic inductance L is obtained by the following expressions (13) and (14)CAnd LEIn combination with the total parasitic inductance minus L given in the data sheetCAnd LEThe sum is obtained to obtain the inductance LEiThe size of (d);
on the basis of the scheme, CGCAs variable capacitance by testing the gate current i at a single operating pointGAnd collector-emitter voltage vCEThe change rate of (A) is obtained by constructing a parameter equation by referring to a data manual (C)GC(sat)Also obtained by the above process.
The technical scheme of the invention has the following beneficial effects:
(1) by establishing a behavior model for accurately describing the control of the time delay on the switching process, a reliable theoretical basis is provided for a control mode of regulating the dynamic current sharing characteristic of the gate pulse to promote the parallel IGBT, and further more detailed switching process regulation is realized;
(2) acquiring and counting relevant data of time delay parameters and current differences of the IGBT of each branch circuit, providing a reference for time delay control, and realizing more effective gate control;
(3) the dynamic current-sharing characteristic is adjusted from the angle of gate delay control, the design and manufacturing cost of high-power hardware needing to be invested in the aspect of current-sharing characteristic optimization is reduced, and the flexibility and the usability of current-sharing control are improved.
Drawings
The invention has the following drawings:
fig. 1-1 is a simplified equivalent circuit schematic diagram of a collector current ramp-up process.
Fig. 1-2 are waveform diagrams of a parallel IGBT turn-on process.
Fig. 2 is a schematic diagram of a parallel driving mode of a master-slave structure type.
Fig. 3 is a schematic diagram of a parallel driving method with a delay compensation function.
Fig. 4 is a schematic diagram of a driving method for realizing parallel IGBT dynamic current sharing by asynchronously controlling gate signals.
Fig. 5 is a block diagram of a driving circuit.
FIG. 6 is a schematic diagram of a driving method for realizing dynamic current sharing of parallel IGBTs by asynchronously controlling gate signals.
Fig. 7 is a schematic diagram of an IGBT turn-on process state detection circuit.
Detailed Description
The invention is described in further detail below with reference to fig. 4-7.
(1) And (3) establishing a behavior model for accurately describing the control of the switch process by the time delay: neglecting parasitic inductance and considering the gate drive loop RC full response during the turn-on delay period to obtain formula (3), by making v in formula (3)GE(t) is equal to the turn-on threshold VGE(th)The on-delay time shown in formula (4) is obtained, wherein VGE(th)The voltage can be obtained by building a test circuit, namely, the auxiliary terminals c and g of the IGBT module are short-circuited, voltage is applied between g and e to observe the change condition of collector current, the voltage can be referred to a data manual and starts from recommended turn-off driving voltage and gradually rises, and when the collector current exceeds a certain threshold value, the corresponding v can be consideredGE＝VGE(th)Thereby obtaining the specific turn-on threshold value of the IGBT module, and the gate emitter capacitance CGEThe Miller capacitance C can be ignored during the turn-on delay periodGCAnd obtaining C through the relationship between the gate voltage and the current (as shown in formula (11))GEWith the value of v measured in the on-delay stageGEAnd t is substituted into formula (3) to obtain a driving resistor RGV to be obtainedGE(th)、CGE≈CiesAnd RGCalculating the opening delay time t after substituting formula (4)d(on)The theoretical value of (1).
In the current rising stage, considering that a certain induction voltage is generated on the parasitic inductance inside the IGBT module when the collector current changes greatly, the relation between the collector current change and time obtained after the formula (1) is deformed, integrated and processed approximately is shown as the formula (12)
Inverse solution of Δ t gives the formula (5), wherein CiesAnd RGHas been obtained from a previous parameter extraction procedure, VGE(pl)Can be obtained by letting i in the formula (2)C＝(1/n)ILAnd solving for v in the second line of equation (2)GEThe parameter K in the formula (2) can be obtained by substituting the value in the transmission characteristic curve in the formula (2), and the transmission characteristic curve can be obtained by referring to a data manual or building a test circuit. For parasitic inductance LEiWhen the IGBT is tested to be in an on state under low bus voltage and low load inductance by building a Buck circuit, the current i of the collector electrode isCLinearly rising, voltage V between power terminal C and auxiliary terminal CCcAnd a voltage V between the auxiliary terminal E and the power terminal EeEWill also vary linearly with it by collecting collector current iCVoltage VCcAnd VeEParasitic inductance L can be obtained by the following expressions (13) and (14)CAnd LEIn combination with the total parasitic inductance minus L given in the data sheetCAnd LEThe sum can obtain the inductance LEiThe size of (2).
The parameters obtained by extraction are substituted into formula (5) through the process, namely the current of the collector is increased to (1/n) I from zero after the turn-on delay stage of the single-tube IGBT is finished through calculationLRequired time td(cr)The theoretical value of (1).
The acquisition process of equations (8), (9) associated with the turn-off delay phase is similar to the turn-on delay phase, where VGE(pl)The extraction of (A) has already been mentioned in the preceding text, for Cies＝CGE+CGC，CGEHas been obtained by the previous parameter extraction processTo, and CGCAs variable capacitance by testing the gate current i at a single operating pointGAnd collector-emitter voltage vCEThe change rate of (C) is obtained by constructing a parameter equation by referring to a data manualGC(sat)And thus also). Will VGE(pl)、CiesAnd RGFormula (9) is substituted to calculate the turn-off delay time td(off)The theoretical value of (1).
For the voltage rise phase, due to VGE(pl)、CGC(sat)And RGThe time t required for the collector-emitter voltage to rise from the on-state saturation voltage drop to the direct-current side voltage in the stage is obtained by substituting the parameters into the formula (10)d(vr)The theoretical value of (1).
By establishing the model and extracting the relevant parameters and carrying out delay calculation and correlating with delay, the dynamic current-sharing characteristic of the parallel IGBT can be theoretically estimated and the subsequent current-sharing realization process can be guided.
(2) Measuring time delay parameters of each branch: as shown in fig. 4, the driver of each parallel IGBT adopts a structure of "independent driving power supply + independent driving core + independent adapter board": drivers of all parallel IGBTs share the same direct-current voltage as the input of an isolated DC-DC driving power supply, the reliability and the stability of power supply are ensured, each IGBT can be effectively protected in real time by an independent driving core, state detection and fault information can be fed back to an upper computer (such as an FPGA), the IGBT can rapidly and accurately analyze and execute input signals containing complex information, an independent adapter plate enables users to adjust partial driving parameters according to actual requirements, and a driving block diagram is shown in figure 5.
The upper computer sends a control signal to the driving circuits of the parallel IGBTs through optical fibers and then starts to record time delay, each driving circuit enables a state detection circuit of an on/off process or a corresponding chip pin after receiving the on/off control signal, the detection circuit outputs a corresponding logic level and then outputs the logic level through a driving board optical fiber to be transmitted to the upper computer in a pulse mode, the pulse can distinguish states of the on process, the off process, faults and the like through setting pulse width or codes, the upper computer records time delay after receiving the pulse corresponding to the state detection of the on/off process and stores the time delay to a region corresponding to the IGBT of the pulse source until the time delay information related to the on/off process of the parallel IGBTs is acquired and stored. If the received pulse corresponds to the fault state of the IGBT, corresponding protection actions (such as blocking a control signal) are executed.
(3) And (3) control signal delay distribution based on an average delay principle: the compensation delay (sign positive-negative corresponding delay and advanced control) which is actually required to be introduced by other IGBTs is obtained by solving the average value of initial delay of the switching-on or switching-off process of each parallel IGBT stored by an upper computer, comparing the average value with each initial delay, selecting the IGBT corresponding to the delay closest to the average value as a reference control signal, subtracting the initial delay of each branch IGBT from the initial delay of the IGBT corresponding to the reference control signal, and transmitting the compensation delay (sign positive-negative corresponding delay and advanced control) to each driver in the next switching period through an optical fiber, thereby finally limiting the dynamic current imbalance of each parallel IGBT within a certain range. The control logic of the upper computer and the driving core is shown in FIG. 6
The IGBT turning-on process state detection circuit is schematically shown in fig. 7, and most of the existing IGBTs have an auxiliary emitter or kelvin emitter terminal (E) for improving the control effect of the driving circuit on the gate, so that a parasitic inductance exists between the auxiliary emitter (E) and the power emitter (E), and the IGBT turning-on process state can be detected by comparing the voltage induced at two ends of the parasitic inductance with a threshold value during the IGBT turning-on process. For IGBT turn-off process state detection circuit, structure and traditional methodCEThe desaturation detection circuit is similar and will not be described herein.
The technical key points and points to be protected of the invention are as follows:
(1) a delayed IGBT behavior model in a current sharing key stage is refined, theoretical expectation and subsequent control guidance are provided for the dynamic current sharing characteristics of the parallel IGBTs in a delayed correlation mode, and gate delay control is more accurate and reliable.
(2) Under the gate pole delay control, reference signals are selected by a driving circuit feedback code and an upper computer on the basis of an average delay principle, then the reference signals are calculated with initial delays of other branches, delay is introduced for the reference signals, and the delay is distributed to each parallel IGBT driving circuit, so that accurate and effective dynamic current sharing control is realized.
Those not described in detail in this specification are within the skill of the art.
Claims (6)
1. A driving method for realizing parallel IGBT dynamic current sharing by asynchronously controlling a gate signal is characterized by comprising the following steps:
(1) determining a behavior model of the IGBT switching process control quantity and the control target:
establishing a driving loop RC or RLC full response equation in the switching process, and then combining an IGBT behavior model to obtain a control model of a gate driving signal to the IGBT collector current;
the turn-on process of the IGBT is divided into three stages of turn-on delay, current rise and voltage drop,
in the on-delay stage, the collector current is zero and the parasitic inductance L is ignoredEiThe gate voltage expression, V, is obtained from the formula (1)G,offIs raised to VGE(th)The time required is the turn-on delay time td(on)Calculated by the formulas (3) and (4):
in the formula: vG,offAnd VG,onFor the IGBT a stable value of the output voltage, V, of the drive circuit in the off and on states, respectivelyGE(th)Is the turn-on threshold of the IGBT gate, Cies＝CGE+CGCIs an input capacitance, CGEIs a gate emitter capacitor, CGCIs a Miller capacitance, RGIs the gate resistance, vGEIs the gate voltage of IGBT iCIs the collector current, V, of the IGBTGE(th)Turn-on threshold, v, for the gate of an IGBTGE(t) the gate voltage in this stage is set to be VG,offThe gate voltage value corresponding to the time when the gate voltage starts to increase to t is the gate voltage in the period from VG,offIncrease to vGE(t) elapsed time;
during the current rise phase when vGEReach the cut-on threshold VGE(th)Rear, collector current iCStarting to rise, taking into account the parasitic inductance LEiThe gate voltage equation is shown as the formula (1)', and the collector currents (1/n) · I of the single tubes in the current rising stage in the n parallel IGBTs are obtained by the formula (5)LTime t required for risingd(cr)；
Wherein:
△VGE＝VGE(pl)-VGE(th) (6)
VGE(ave)＝0.5·[VGE(pl)+VGE(th)] (7)
in the formula: delta VGEIs the change of the gate voltage during the current rise, VGE(ave)Is the average of the Miller plateau and the opening threshold, VGE(pl)In order to be a miller platform,
according to the formulas (4) and (5), a gate delay control compensation behavior model is established, and the gate delay compensation is realized to realize the balanced control of the current difference in the opening process;
for the turn-off process, the turn-off delay and voltage rise stages are divided;
in the turn-off delay stage, the driving voltage is changed from VG,onBecomes VG,offThen, the input capacitor starts to discharge, the gate voltage is reduced to the gate voltage corresponding to the collector current of the IGBT in the active region, the collector voltage starts to rise, and the gate voltage is maintained at the Miller platform V againGE(pl)In the vicinity, the gate voltage is represented by the equation (8):
the time required to complete this phase is the turn-off delay time td(off)As shown in formula (9):
collector-emitter voltage rising stage: at this stage, after the gate voltage is reduced to the gate voltage corresponding to the collector current of the IGBT in the active region, the collector voltage starts to rise and the gate voltage is maintained at the Miller platform V againGE(pl)Nearby, when the collector current is large, the change rate of the collector-emitter voltage in the behavior model is used for obtaining the time t required for the collector-emitter voltage to rise from the on-state saturation voltage drop to the direct-current side voltage in the voltage rising staged(vr)As shown in formula (10):
in the formula, CGC(sat)Maintaining the corresponding miller capacitance value when the on-state saturation voltage drop is maintained for the collector-emitter voltage;
according to the formulas (9) and (10), a gate delay control compensation behavior model is established, and the gate delay compensation is realized to realize the balanced control of the current difference in the turn-off process;
(2) acquiring initial time delay of each branch IGBT switching process:
the judgment of the state of the IGBT on/off process is mainly based on the detection of the voltage quantity, and for the on process, the voltage v of a power emitter is usedeEFrom zero voltage toThe rising edge at the peak value corresponds to the current rising stage, and the upper computer starts timing when sending a turn-on control signal to the driving circuit of each IGBT and controls veECollected and compared with a reference value Vref1After comparison, taking the rising edge of the pulse signal output by the comparator as a criterion for time recording ending, thereby obtaining time delay relevant to the turn-on delay stage and the current rising stage of each parallel IGBT;
for the detection of the state of the turn-off process, the upper computer starts to time after sending a turn-off control signal to use the voltage v of the collector and the emitterCEThe rising edge when the on-state saturation voltage rises to the bus voltage corresponds to the voltage rising stage by vCECollected and compared with a reference value Vref2After comparison, taking the rising edge of the pulse signal output by the comparator as a criterion for timing ending, thereby obtaining the time delay related to the turn-off delay stage and the voltage rising stage of each parallel IGBT;
(3) setting average delay time, and adjusting pulse trigger time sequence of each branch:
through the acquisition of the states of the IGBT turn-on/turn-off process and the time delay of the corresponding stage in the step (2), each IGBT drive board transmits related time delay information to an upper computer through an optical fiber signal for the time delay adjustment of a control signal of the next switching process, a reference control signal is selected to obtain the lead-lag time of each IGBT gate signal, and the selection of the reference control signal adopts an average time delay asynchronous driving control mode;
(4) the upper computer sends down the set delay data to realize the asynchronous gate trigger:
the upper computer obtains the lead-lag time of each IGBT gate signal through data processing and then adjusts the gate trigger time sequence to act on the next switching process so as to improve the dynamic current sharing of the parallel IGBTs.
2. The driving method for realizing parallel IGBT dynamic current sharing by using the asynchronous control gate signal according to claim 1, wherein V isGE(th)The method comprises the steps of obtaining through a mode of building a test circuit.
3. The method of claim 1The driving method for realizing the dynamic current sharing of the parallel IGBT by the asynchronous control gate pole signal is characterized in that a gate emitter capacitor CGECalculated by equation (11):
in the formula: i.e. iGIs the gate current.
4. The driving method for realizing parallel IGBT dynamic current sharing by using the asynchronous control gate signal according to claim 1, wherein V isGE(pl)The solution is performed by equation (2):
in the formula (2), iC＝(1/n)ILSolving for v in the second line of equation (2)GETo obtain VGE(pl)For the parameter K in the formula (2), the parameter K is obtained by substituting the value in the transmission characteristic curve in the formula (2), and the transmission characteristic curve is obtained by referring to a data manual or building a test circuit.
5. The driving method for realizing parallel IGBT dynamic current sharing by using the asynchronous control gate signal according to claim 1, wherein parasitic inductance LEiThe acquisition comprises the steps of firstly building a Buck circuit, testing the IGBT in an on state under low bus voltage and low load inductance, and acquiring collector current iCCollector voltage VCcAnd a power emitter voltage VeEThe parasitic inductance L is obtained by the following expressions (13) and (14)CAnd LEIn combination with the total parasitic inductance minus L given in the data sheetCAnd LEThe sum is obtained to obtain the inductance LEiThe size of (d);
6. the driving method for realizing parallel IGBT dynamic current sharing by using the asynchronous control gate signal according to claim 1, wherein C isGCAs variable capacitance by testing the gate current i at a single operating pointGAnd collector-emitter voltage vCEAnd constructing a parameter equation by referring to a data manual to obtain the change rate of (C)GC(sat)Also obtained by the above process.
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