CN112071889A - Array substrate, display device and manufacturing method - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 184
- 239000010410 layer Substances 0.000 claims abstract description 183
- 239000012044 organic layer Substances 0.000 claims abstract description 49
- 230000008020 evaporation Effects 0.000 claims abstract description 48
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- 238000000034 method Methods 0.000 claims description 25
- 230000008021 deposition Effects 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 11
- 230000004044 response Effects 0.000 claims description 7
- 238000007740 vapor deposition Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 16
- 230000005540 biological transmission Effects 0.000 description 13
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- 229920001621 AMOLED Polymers 0.000 description 3
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/84—Passivation; Containers; Encapsulations
- H10K50/844—Encapsulations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/17—Passive-matrix OLED displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
- H10K77/10—Substrates, e.g. flexible substrates
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses an array substrate, a display device and a manufacturing method, wherein the array substrate comprises a first display area and a second display area, the first display area comprises first pixels which are arranged according to a first pixel density array, an organic layer of the first display area comprises a first isolation groove with a first depth, an inorganic layer of the first display area comprises a first through hole which penetrates through the inorganic layer, and the first through hole and the first isolation groove are correspondingly arranged to expose the first isolation groove; the second display area comprises second pixels arranged according to a second pixel density array, the organic layer of the second display area comprises a second isolation groove with a second depth, the inorganic layer of the second display area comprises a second through hole penetrating through the inorganic layer, the second through hole and the second isolation groove are correspondingly arranged to partially expose the second isolation groove, and the evaporation layer of the second display area is disconnected corresponding to the edge position of the second isolation groove; the first pixel density is greater than the second pixel density, and the first depth is less than the second depth.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display device and a manufacturing method.
Background
In recent years, high screen ratio electronic products are more and more popular in the market, and a full screen is more and more popular. The technology of passive driving organic light emitting diode unit (PMOLED) under-screen image pickup with low pixel density is one of the technical directions for improving the screen occupation ratio. In order to realize controllability when a PMOLED region is lighted, an isolation groove needs to be designed on an array substrate to isolate the cathode of an OLED device in the region, however, the problems of peeling of a film layer of the array substrate and poor bubbling are easily caused when the isolation groove is formed in the existing process flow, and the yield of the array substrate is greatly influenced.
Therefore, a new array substrate, a display device and a manufacturing method are needed.
Disclosure of Invention
In order to solve at least one of the above problems, a first embodiment of the present invention provides an array substrate including a first display region and a second display region,
the array substrate comprises an organic layer, an inorganic layer, an anode, a pixel defining layer and a vapor deposition layer which are sequentially stacked on a substrate, wherein the organic layer, the inorganic layer, the anode, the pixel defining layer and the vapor deposition layer are arranged on the substrate in a stacked mode
The first display area comprises a plurality of first pixels arranged according to a first pixel density array, the organic layer of the first display area comprises first isolation grooves with a first depth arranged between adjacent first pixels, the inorganic layer of the first display area comprises first via holes penetrating through the inorganic layer, and the first via holes and the first isolation grooves are correspondingly arranged to expose the first isolation grooves;
the second display area comprises a plurality of second pixels arranged according to a second pixel density array, the organic layer of the second display area comprises second isolation grooves with a second depth arranged between the adjacent second pixels, the inorganic layer of the second display area comprises second through holes penetrating through the second display area, the second through holes and the second isolation grooves are correspondingly arranged to partially expose the second isolation grooves, and the evaporation layer of the second display area is disconnected corresponding to the edge positions of the second isolation grooves;
the first pixel density is greater than the second pixel density, and the first depth is less than the second depth.
Further, the thickness of the evaporation layer corresponding to the edge position of the first isolation groove is smaller than that of the evaporation layer corresponding to the pixel defining layer position;
or
The evaporation layer is disconnected corresponding to the edge position of the first isolation groove.
Further, the first depth is greater than 0.1 μm and less than 1 μm.
Further, the side wall of the second isolation groove protrudes to the outer side of the inorganic layer to form a concave structure;
and/or
The second depth is greater than 1 μm and less than 2 μm.
Further, the first display area adopts an active driving type organic light emitting diode unit, and the second display area adopts a passive driving type organic light emitting diode unit;
or
The first display area and the second display area both adopt active driving type organic light emitting diode units.
A second embodiment of the present invention provides a method for manufacturing the array substrate, including:
sequentially stacking an organic layer and an inorganic layer formed on a substrate;
patterning to form a first via hole and a second via hole penetrating through the inorganic layer, and a first isolation groove and a third isolation groove, wherein the first isolation groove and the third isolation groove are formed on the organic layer and have a first depth and correspond to the first via hole and the second via hole, the first via hole and the first isolation groove are arranged in a first pixel density array to form a first display area, the second via hole and the third isolation groove are arranged in a second pixel density array to form a second display area, and the first pixel density is greater than the second pixel density;
an anode and a pixel defining layer sequentially formed on the inorganic layer, the first display region including a plurality of first anodes and corresponding first pixel defining layers arranged in a first pixel density array, the second display region including a plurality of second anodes and corresponding second pixel defining layers arranged in a second pixel density array;
patterning the third isolation trench to form a second isolation trench having a second depth, the second isolation trench partially exposed from the second via;
and forming an evaporation coating which covers the pixel defining layer, the exposed first isolation groove, the anode and the second isolation groove, wherein the evaporation coating is disconnected corresponding to the edge position of the second isolation groove.
Further, the forming an evaporation layer covering the pixel defining layer, the exposed first isolation groove, the anode and the second isolation groove further comprises:
in response to a first isolation groove having the first depth, a thickness of the deposition layer corresponding to an edge position of the first isolation groove is smaller than a thickness corresponding to the pixel defining layer position;
or
In response to a first isolation groove having the first depth, the deposition layer is broken corresponding to an edge position of the first isolation groove.
Further, the first depth is greater than 0.1 μm and less than 1 μm.
Further, the patterning the third isolation trench to form a second isolation trench having a second depth, the exposing the second isolation trench portion from the second via further comprising: the side wall of the second isolation groove protrudes towards the outer side of the inorganic layer to form an inwards concave structure;
and/or
The second depth is greater than 1 μm and less than 2 μm.
A third embodiment of the invention provides a display device including the array substrate as described above.
The invention has the following beneficial effects:
aiming at the existing problems at present, the invention provides an array substrate, on the basis of controlling the display of a second display area by separating a vapor deposition layer covered on the second display area through a second isolation groove with a second depth, a first isolation groove with a first depth and positioned between adjacent first pixels is arranged on an organic layer of the first display area, and a first via hole which is correspondingly arranged with the first isolation layer and penetrates through an inorganic layer exposes the organic layer at the corresponding position to avoid the generation of film layer stripping and poor bubbling in the manufacturing process of the array substrate; meanwhile, the first isolation groove can effectively block an electronic transverse transmission path of the evaporation layer or increase transmission resistance, so that bad crosstalk between devices on the array substrate is avoided, the problems in the prior art can be solved, the production cost is effectively reduced, the product yield and the production efficiency are improved, and the wide application prospect is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a block diagram illustrating a layer structure of an array substrate according to an embodiment of the present invention;
fig. 2 is a block diagram illustrating a top view structure of an array substrate according to an embodiment of the present invention;
FIGS. 3a to 3d are block diagrams illustrating a layer structure of an array substrate in the related art;
FIGS. 4a-4b are schematic diagrams illustrating the peeling and bubbling failure of an array substrate in the prior art;
fig. 5 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 6a to 6d are diagrams illustrating a process of forming an array substrate according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
It is noted that references herein to "on … …", "formed on … …" and "disposed on … …" can mean that one layer is formed or disposed directly on another layer or that one layer is formed or disposed indirectly on another layer, i.e., there is another layer between the two layers. As used herein, unless otherwise specified, the term "on the same layer" means that two layers, components, members, elements or portions can be formed by the same patterning process, and the two layers, components, members, elements or portions are generally formed of the same material. Herein, unless otherwise specified, the expression "patterning process" generally includes the steps of coating of photoresist, exposure, development, etching, stripping of photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, or the like using one mask plate.
It is further noted that, in the description of the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
As shown in fig. 3a to 3d, in the prior art, the array substrate includes a first display area and a second display area, wherein the first display area employs an active driving type organic light emitting diode unit AMOLED, the second display area employs a passive driving type organic light emitting diode unit PMOLED, and in the second display area for under-screen image capture, the evaporation layer of the PMOLED device in the area is blocked by providing an isolation groove 112' on the array substrate to control the lighting of the second display area. Specifically, the isolation groove 112 ' on the array substrate is mainly realized by etching the organic layer 11 ' to form the isolation groove 112 '. As shown in fig. 3a, first, an inorganic layer 12 'is formed on an organic layer 11', then, as shown in fig. 3b, a via hole is etched in a region where an isolation trench needs to be etched in the inorganic layer 12 ', then, as shown in fig. 3c, other layer structures such as an anode 13', a pixel defining layer 14 ', and a supporting layer 17' are formed on the organic layer, and finally, as shown in fig. 3d, an isolation trench etching is performed on the organic layer 11 ', thereby forming an isolation trench 112' structure.
However, the inorganic layer 12 ' on the organic layer 11 ' is deposited over the entire surface during deposition, and for the AMOLED in the first display region, the remaining of the inorganic layer 12 ' may prevent the organic layer corresponding to the region from discharging water vapor in a subsequent high-temperature process, so that the internal pressure of each film layer is increased, which may result in poor film layer peeling as shown in fig. 4a and poor bubbling as shown in fig. 4b, and further, the EV evaporation process may not be performed on the array substrate, thereby making it very difficult to process and manufacture the array substrate. Meanwhile, if the inorganic layer 12 'in the first display region is etched in a large area to form the isolation trench, the etching gas may damage the surface of the organic layer 11', which may cause unevenness of the anode film and a series of optical defects such as color shift. Further, when the OLED device is disposed on the array substrate, since the pixel density of the first display region is high, the inter-sub-pixel distance of each pixel is shorter, and thus, there is a problem of crosstalk in which electrons are laterally transferred between the sub-pixels due to the common organic layer formed by evaporation. Therefore, to solve the above problems, the present invention provides an array substrate, a display device and a manufacturing method thereof.
As shown in fig. 1 and 2, an embodiment of the present invention provides an array substrate including a first display area AA and a second display area BB, the array substrate including an organic layer 11, an inorganic layer 12, an anode 13, a pixel defining layer 14, and an evaporation layer 15, which are sequentially stacked on a substrate 16, wherein
The first display area AA includes a plurality of first pixels 141 arranged in a first pixel density array, the organic layer 11 of the first display area AA includes first isolation grooves 111 disposed between adjacent first pixels 141 and having a first depth, the inorganic layer 11 of the first display area AA includes first via holes penetrating therethrough, and the first via holes and the first isolation grooves are disposed correspondingly to expose the first isolation grooves;
the second display area BB includes a plurality of second pixels 142 arranged in a second pixel density array, the organic layer 11 of the second display area includes second isolation grooves 112 with a second depth disposed between adjacent second pixels 142, the inorganic layer 12 of the second display area includes second via holes penetrating therethrough, the second via holes are disposed corresponding to the second isolation grooves to partially expose the second isolation grooves, and the evaporation layer 15 of the second display area is disconnected corresponding to an edge position 152 of the second isolation grooves 112;
the first pixel density is greater than the second pixel density, and the first depth is less than the second depth.
In this embodiment, the evaporation layer includes an organic light emitting layer and a cathode, and as shown in fig. 1 and 2, in the array substrate according to the embodiment of the present invention, the second isolation groove having the second depth and located between the adjacent second pixels is provided on the organic layer in the second display region, so that the evaporation layer covering the edge position of the second isolation groove is cut off, that is, the cathode in the second display region is effectively cut off, thereby implementing lighting control of each second pixel in the second display region. Meanwhile, the first isolation groove with the first depth and arranged between the adjacent first pixels and the first via hole penetrating through the inorganic layer and correspondingly arranged with the first isolation layer are arranged on the organic layer of the first display area, so that the organic layer at the corresponding position is exposed, water vapor can be rapidly discharged from the organic layer in a subsequent high-temperature process, the internal pressure of each film layer is reduced, and the film layer stripping and bubbling defects generated in the manufacturing process of the array substrate are avoided; and when the OLED device is manufactured on the array substrate, the first isolation groove with a certain depth between the adjacent first pixels can cut off or thin the evaporation layer of the OLED device formed on the array substrate, and the poor crosstalk generated by the OLED device arranged on the array substrate is avoided by blocking the electronic transverse transmission path of the evaporation layer or increasing the transmission resistance, so that the problems in the prior art are solved, the production cost can be effectively reduced, the product yield and the production efficiency are effectively improved, and the OLED device has a wide application prospect.
In this embodiment, as shown in fig. 1 and fig. 2, the inorganic layer 12 of the first display area AA includes a first via hole penetrating through the inorganic layer, the first isolation groove 111 corresponding to the first via hole is located between two adjacent first pixels 141, and the first via hole completely exposes the first isolation groove 111, so as to provide a vapor exhaust channel for the organic layer 11 under the inorganic layer 12, so that in the subsequent manufacturing process of the array substrate, the vapor generated by the organic layer due to high temperature is quickly exhausted, thereby reducing the internal pressure of each film layer, avoiding the generation of poor film layer peeling and poor bubbling, and effectively improving the yield of the array substrate. In a specific example, the etching area of all the first isolation grooves accounts for 2% -5% of the area of the light emitting area formed in the first display area, and a water vapor discharge channel is effectively provided for the organic layer on the basis of ensuring that the overall strength of the array substrate is not affected.
It should be noted that the two adjacent first pixels may be two adjacent pixels, or two adjacent sub-pixels; since the second isolation trench completely isolates the cathode between the pixels, the two adjacent second pixels are usually disposed between two adjacent columns of pixels, and may also be disposed between adjacent pixels or adjacent sub-pixels, which is not specifically limited in this application. Those skilled in the art should perform setting according to actual application requirements to realize that the first isolation groove is used to solve the existing problem as a design criterion on the basis of performing display control on each pixel of the second display area by using the second isolation groove, which is not described herein again.
In an alternative embodiment, the thickness of the evaporation layer corresponding to the edge position of the first isolation groove is smaller than the thickness of the evaporation layer corresponding to the pixel defining layer position.
In this embodiment, the thickness of the evaporation layer at the edge of the first isolation groove is reduced to increase the resistance of the evaporation layer, so as to avoid poor crosstalk generated by the OLED device disposed on the array substrate. In a specific example, when the first depth of the first isolation groove is greater than 0.1 μm and less than 1 μm, for example, the depth of the first isolation groove is 0.2 μm, the first isolation groove is disposed outside the first pixel, for example, the first isolation groove is a closed ring-shaped structure surrounding the first sub-pixel, and the evaporation layer formed outside the first sub-pixel is not completely cut off by the first isolation groove. As shown in fig. 1, the thickness of the deposition layer 15 formed at the edge position 151 of the first isolation groove 111, i.e., at the boundary between the organic layer 11 and the inorganic layer 12, i.e., at the edge position corresponding to the first isolation groove, is smaller than the thickness of the deposition layer 15 formed on the pixel defining layer 14, thereby increasing the resistance of the deposition layer 15. Therefore, in the electrically connected state, the resistance of the OLED device formed on the array substrate for lateral transmission of electrons is increased, and the crosstalk failure can be effectively improved.
In another alternative embodiment, the deposition layer 15 is broken at an edge position 151 corresponding to the first isolation groove 111.
In the embodiment, by cutting off part of the transverse electron transmission path, poor crosstalk generated by electron transmission of the OLED device arranged on the array substrate can be avoided. In a specific example, the first depth of the first isolation trenches is greater than 0.1 μm and less than 1 μm, for example, when the depth of the first isolation trenches is 0.9 μm, the first isolation trenches are arranged as shown in fig. 2, two adjacent first isolation trenches 111 on the same straight line in the vertical direction are not connected, the first isolation trenches 111 in the vertical direction are also not connected with the corresponding first isolation trenches 111 in the transverse direction, and a certain distance is provided between each first isolation trench. At this time, the vapor deposition layer 15 formed at the edge position 151 of the first isolation groove shown in fig. 1, that is, at the boundary between the organic layer and the inorganic layer is cut off, and the electron transport path in the lateral direction is also partially cut off. Therefore, in the electrically connected state, the resistance of the OLED device formed on the array substrate for lateral transmission of electrons is increased, and the crosstalk failure can be effectively improved.
In this embodiment, the etching depth of the first depth is shallow, and the first via hole and the first isolation trench corresponding to the first via hole can be formed at the same time. In a specific example, the first isolation trench having the first depth in the present embodiment may be formed by performing over-etching by controlling an etching condition such as an etching time when the inorganic layer is subjected to the etching process of the first via hole. Therefore, the process flow for forming the first isolation groove is simple, no additional process step is added, no auxiliary jig is needed for processing, and the first depth does not damage the surface of the organic layer, thereby effectively ensuring the yield of the array substrate.
In an alternative embodiment, as shown in fig. 1, the sidewalls of the second isolation trench 112 protrude toward the outer side of the inorganic layer 12 to form a concave structure.
In this embodiment, as shown in the schematic layer structure interface diagram of the array substrate shown in fig. 1, the aperture of the second via hole on the inorganic layer 12 is smaller than the groove diameter of the second isolation groove 112, so that, in the top view direction, the aperture of the second via hole only exposes a part of the second isolation groove 112, and the unexposed part of the second isolation groove corresponds to the surface 152 of the inorganic layer and does not form the evaporation layer 15, i.e., the evaporation layer 15 is cut at the edge position 152 of the second isolation groove in response to the etching depth and the etching groove diameter of the second isolation groove, thereby achieving effective control of the cathode of the OLED device.
In a specific example, the second depth is greater than 1 μm and less than 2 μm. Namely, when the second depth value of the second isolation groove is in the range of 1-2 μm, the evaporation layer 15 is cut off at 152, and the cathode of the OLED device can be effectively controlled.
Specifically, as shown in fig. 2, the second isolation groove 112 is an extended groove that penetrates the width of the array substrate, and can effectively cut off the deposition layer 15 covering thereon, thereby implementing effective control of the OLED device in the second display area. In this embodiment, the groove diameter of the second isolation groove may be 2-5 μm, the etching area of all the second isolation grooves accounts for 10% -20% of the area of the light emitting region formed in the second display region, and the cathode of the OLED device may be effectively controlled on the basis of ensuring that the overall strength of the array substrate is not affected.
It should be noted that, in this embodiment, as shown in fig. 1, a supporting layer 17 is further disposed on the pixel defining layer 14 for supporting in the manufacturing step, and the evaporation layer 15 further covers the supporting layer 17, this embodiment is only used for illustrating the present technical solution, and the specific structure of the array substrate is not limited, and it is within the scope of the present application to solve the above problem by disposing the first isolation groove in the first display region.
In an alternative embodiment, the first display area AA employs active driving type organic light emitting diode units, and the second display area BB employs passive driving type organic light emitting diode units (PMOLED).
In this embodiment, the transmittance of the display device can be ensured and the off-screen image capturing function of the display device can be realized by respectively providing the active driving type organic light emitting diode unit (AMOLED) with the first pixel density in the first display region and the passive driving type organic light emitting diode unit (PMOLED) with the second pixel density in the second display region.
In another alternative embodiment, the first display area AA and the second display area BB both use active driving type organic light emitting diode units.
In this embodiment, since the pixel densities of the first display area and the second display area are different, for example, the first pixel density is much greater than the second pixel density, the active driving type organic light emitting diode unit is used in both the first display area AA and the second display area BB, and the under-screen image capturing function of the display device can also be realized.
Therefore, a person skilled in the art can realize the under-screen image capturing function of the display device by setting the organic light emitting diode units of different driving types, and can also realize the under-screen image capturing function of the display device by setting the organic light emitting diode units of the same type actively driven in different display areas and distributed with different pixel densities. This implementation can be convenient for set up optical device like camera under the screen in the position that the second display area corresponds in follow-up processing procedure, need not to dig the hole or set up "qiliu" to array substrate to realize the most genuine full face screen display and show.
Corresponding to the array substrate provided in the foregoing embodiment, as shown in fig. 5, an embodiment of the present application further provides a method for manufacturing the array substrate, including:
an organic layer 11 and an inorganic layer 12 formed on a substrate 16 in this order;
patterning to form a first via hole and a second via hole penetrating through the inorganic layer 12, and a first isolation groove 111 corresponding to the first via hole and a third isolation groove 113 corresponding to the second via hole, which are formed on the organic layer and have a first depth, wherein the first via hole and the first isolation groove 111 are arranged in a first pixel density array and form a first display area AA, the second via hole and the third isolation groove 113 are arranged in a second pixel density array and form a second display area BB, and the first pixel density is greater than the second pixel density;
an anode electrode 13 and a pixel defining layer 14 sequentially formed on the inorganic layer 12, the first display area AA including a plurality of first anode electrodes and corresponding first pixel defining layers arranged in a first pixel density array, and the second display area BB including a plurality of second anode electrodes and corresponding second pixel defining layers arranged in a second pixel density array;
patterning the third isolation trench 113 to form a second isolation trench 112 having a second depth, the second isolation trench 112 being partially exposed from the second via;
forming an evaporation layer 15 covering the pixel defining layer 14, the exposed first isolation groove 111, the anode 13 and the second isolation groove 112, wherein the evaporation layer 15 is disconnected corresponding to the edge position 152 of the second isolation groove 112.
In this embodiment, in the array substrate manufactured by the above manufacturing method, on the basis of controlling the display of the second display region by blocking the evaporation layer covered on the second isolation groove with the second depth, the organic layer at the corresponding position is exposed by providing the first isolation groove with the first depth between the adjacent first pixels on the organic layer of the first display region, and the first via hole penetrating through the inorganic layer and provided corresponding to the first isolation layer, so as to avoid the film peeling and the bubbling failure generated in the manufacturing process of the array substrate; meanwhile, the first isolation groove can effectively block partial electronic transverse transmission paths of the evaporation layer and increase transmission resistance, so that bad crosstalk between devices on the array substrate is avoided, the problems in the prior art can be solved, the production cost is effectively reduced, the product yield and the production efficiency are improved, and the wide application prospect is achieved.
Those skilled in the art will appreciate that the foregoing embodiments and the attendant advantages are also applicable to this embodiment, and therefore, the description of the same parts is omitted.
The method for manufacturing the array substrate according to the embodiment of the invention will now be described with reference to fig. 6a to 6 d:
in a first step, as shown in fig. 6a, an organic layer 11 is formed on a substrate 16 through a deposition process, and then an inorganic layer 12 is formed on the organic layer 11 through a deposition process.
And secondly, as shown in fig. 6b, forming a first via hole and a second via hole penetrating through the inorganic layer 12 by an etching process, wherein the shapes of the first via hole and the second via hole are set according to practical application. In the etching process of the first via hole, performing over-etching by setting etching conditions such as etching time and the like to form a first isolation groove 111 with a first depth on the organic layer 11, wherein the first isolation groove corresponds to the first via hole; similarly, a third isolation groove 113 having a first depth and corresponding to the second via hole is formed during the etching process of the second via hole. At this time, the first via holes and the first isolation grooves are arranged in a first pixel density array to form a first display area AA, the second via holes and the third isolation grooves are arranged in a second pixel density array to form a second display area BB, and the first pixel density is greater than the second pixel density. And the first isolation groove formed in the step and positioned on the organic layer of the first display area exposes the organic layer, so that a channel for quickly removing water vapor is provided for the organic layer in the subsequent process. The position and the structural design of the first isolation groove are similar to those of the array substrate according to the foregoing embodiments of the present invention, and are not described herein again.
In another alternative embodiment, the first depth of the first isolation trench formed in this step is greater than 0.1 μm and less than 1 μm.
In a third step, as shown in fig. 6c, an anode electrode 13, a pixel defining layer 14, and a supporting layer 17 are sequentially formed on the inorganic layer 12, the first display region includes a plurality of first anode electrodes and corresponding first pixel defining layers arranged in a first pixel density array, and the second display region includes a plurality of second anode electrodes and corresponding second pixel defining layers arranged in a second pixel density array.
In this embodiment, a support layer 17 is further disposed on the pixel defining layer 14, and the evaporation layer 15 further covers the support layer 17. It should be noted that, this embodiment is only used for illustrating the present technical solution, and the specific structure of the array substrate is not limited, and it is within the scope of the present application to solve the above problem by providing the first isolation trench in the first display region.
Fourthly, as shown in fig. 6d, the second isolation trench 112 with the second depth is formed by etching on the basis of the third isolation trench 113, and the diameter of the formed second isolation trench 112 is larger than the aperture of the second via hole, so that a part of the second isolation trench is exposed from the second via hole. Further, the sidewall of the second isolation trench 112 protrudes to the outside of the inorganic layer 12 to form a concave structure.
In an optional embodiment, the step further comprises: the second depth is greater than 1 μm and less than 2 μm.
The second isolation groove 112 formed in this step is designed with its structure and depth, so that the evaporation layer corresponding to the edge position 152 of the second isolation groove is disconnected, thereby completely disconnecting the cathode to effectively control the cathode of the OLED device. Since the second isolation trench needs to be etched in a large area and a large depth, a mask plate is usually used to form the second isolation trench in this step.
And fifthly, performing evaporation on the basis of the layer structure shown in fig. 6d to form the array substrate shown in fig. 1, specifically, forming an evaporation layer 15 covering the pixel defining layer 14, the exposed first isolation groove 111, the anode 13 and the second isolation groove 112, wherein the evaporation layer 15 is disconnected corresponding to the edge position 152 of the second isolation groove 112.
In an alternative embodiment, forming the evaporation layer 15 covering the pixel defining layer 14, the exposed first isolation groove 111, the anode 13, and the second isolation groove 112 further includes: in response to the first isolation groove having the first depth, the thickness of the deposition layer 15 corresponding to the edge position 151 of the first isolation groove 111 is smaller than the thickness corresponding to the position of the pixel defining layer 14.
In another alternative embodiment, forming the evaporation layer 15 covering the pixel defining layer 14, the exposed first isolation groove 111, the anode 13, and the second isolation groove 112 further includes: in response to the first isolation groove 111 having the first depth, the deposition layer 15 is disconnected corresponding to the edge position 151 of the first isolation groove 111.
In the two embodiments, the thickness of the evaporation layer at the edge position 151 of the first isolation groove 111 is reduced, or the evaporation layer at the edge position 151 of the first isolation groove 111 is partially cut off, so that the transmission resistance of the evaporation layer is increased to effectively avoid poor crosstalk.
It should be noted that, as those skilled in the art should understand, the specific structure and the manufacturing method of the array substrate in the embodiment of the present invention are not specifically limited, and it is within the scope of the present application that the first isolation trench is disposed in the first display region to solve the above problem, and therefore, the details are not repeated.
Based on the array substrate of the above embodiment, another embodiment of the present invention further provides a display device, including the array substrate.
In this embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
Aiming at the existing problems at present, the invention provides an array substrate, on the basis of controlling the display of a second display area by separating a vapor deposition layer covered on a second isolation groove with a second depth, a first isolation groove with a first depth and positioned between adjacent first pixels is arranged on an organic layer of the first display area, and a first via hole which is correspondingly arranged with the first isolation layer and penetrates through an inorganic layer exposes the organic layer at the corresponding position to avoid film layer stripping and poor bubbling generated in the manufacturing process of the array substrate; meanwhile, the first isolation groove can effectively block an electronic transverse transmission path of the evaporation layer or increase transmission resistance, so that bad crosstalk between devices on the array substrate is avoided, the problems in the prior art can be solved, the production cost is effectively reduced, the product yield and the production efficiency are improved, and the wide application prospect is achieved.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (10)
1. The array substrate comprises a first display area and a second display area, and is characterized by comprising an organic layer, an inorganic layer, an anode, a pixel defining layer and a vapor deposition layer which are sequentially stacked on a substrate, wherein the organic layer, the inorganic layer, the anode, the pixel defining layer and the vapor deposition layer are sequentially stacked on the substrate
The first display area comprises a plurality of first pixels arranged according to a first pixel density array, the organic layer of the first display area comprises first isolation grooves with a first depth arranged between adjacent first pixels, the inorganic layer of the first display area comprises first via holes penetrating through the inorganic layer, and the first via holes and the first isolation grooves are correspondingly arranged to expose the first isolation grooves;
the second display area comprises a plurality of second pixels arranged according to a second pixel density array, the organic layer of the second display area comprises second isolation grooves with a second depth arranged between the adjacent second pixels, the inorganic layer of the second display area comprises second through holes penetrating through the second display area, the second through holes and the second isolation grooves are correspondingly arranged to partially expose the second isolation grooves, and the evaporation layer of the second display area is disconnected corresponding to the edge positions of the second isolation grooves;
the first pixel density is greater than the second pixel density, and the first depth is less than the second depth.
2. The array substrate of claim 1,
the thickness of the evaporation layer corresponding to the edge position of the first isolation groove is smaller than that of the evaporation layer corresponding to the position of the pixel defining layer;
or
The evaporation layer is disconnected corresponding to the edge position of the first isolation groove.
3. The array substrate of claim 2, wherein the first depth is greater than 0.1 μm and less than 1 μm.
4. The array substrate of claim 1,
the side wall of the second isolation groove protrudes towards the outer side of the inorganic layer to form an inwards concave structure;
and/or
The second depth is greater than 1 μm and less than 2 μm.
5. The array substrate of any one of claims 1 to 4,
the first display area adopts an active driving type organic light emitting diode unit, and the second display area adopts a passive driving type organic light emitting diode unit;
or
The first display area and the second display area both adopt active driving type organic light emitting diode units.
6. A method of fabricating the array substrate of any one of claims 1-5, comprising:
sequentially stacking an organic layer and an inorganic layer formed on a substrate;
patterning to form a first via hole and a second via hole penetrating through the inorganic layer, and a first isolation groove and a third isolation groove, wherein the first isolation groove and the third isolation groove are formed on the organic layer and have a first depth and correspond to the first via hole and the second via hole, the first via hole and the first isolation groove are arranged in a first pixel density array to form a first display area, the second via hole and the third isolation groove are arranged in a second pixel density array to form a second display area, and the first pixel density is greater than the second pixel density;
an anode and a pixel defining layer sequentially formed on the inorganic layer, the first display region including a plurality of first anodes and corresponding first pixel defining layers arranged in a first pixel density array, the second display region including a plurality of second anodes and corresponding second pixel defining layers arranged in a second pixel density array;
patterning the third isolation trench to form a second isolation trench having a second depth, the second isolation trench partially exposed from the second via;
and forming an evaporation coating which covers the pixel defining layer, the exposed first isolation groove, the anode and the second isolation groove, wherein the evaporation coating is disconnected corresponding to the edge position of the second isolation groove.
7. The method of claim 6, wherein forming an evaporated layer covering the pixel defining layer, the exposed first isolation trench, the anode, and the second isolation trench further comprises:
in response to a first isolation groove having the first depth, a thickness of the deposition layer corresponding to an edge position of the first isolation groove is smaller than a thickness of the deposition layer corresponding to the pixel defining layer position;
or
In response to a first isolation groove having the first depth, the deposition layer is broken corresponding to an edge position of the first isolation groove.
8. The method of claim 6, wherein the first depth is greater than 0.1 μm and less than 1 μm.
9. The method of claim 6,
the patterning the third isolation trench to form a second isolation trench having a second depth, the second isolation trench partially exposed from the second via further comprising: the side wall of the second isolation groove protrudes towards the outer side of the inorganic layer to form an inwards concave structure;
and/or
The second depth is greater than 1 μm and less than 2 μm.
10. A display device comprising the array substrate according to any one of claims 1 to 5.
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