CN112071359B - SRAM memory single particle and charge-discharge effect test system and method based on FPGA - Google Patents

Abstract

The invention provides a SRAM memory single event and charge-discharge effect test system and method based on FPGA, comprising: a test unit; the test unit comprises a PC (personal computer), an upper computer, a lower computer, a single event effect simulation source, a charge-discharge effect simulation source and an electromagnetic shielding unit; the PC is connected with the upper computer through a serial port; the upper computer is connected with the lower computer through a shielding wire; the lower computer is arranged in the environment of a single event effect simulation source or a charge-discharge simulation source; the PC, the upper computer and the power supply unit are arranged in the electromagnetic shielding unit. The method can acquire characteristic parameters of the SRAM under the comprehensive influence of the single event effect and the charge and discharge effect, such as information parameters of an overturning section, an overturning curve, an overturning threshold value and the like, under the irradiation condition of a laboratory simulation source, and compares the influence of the device after being irradiated by the single event effect on the charge and discharge effect with the influence of the device after being irradiated by the charge and discharge effect on the single event effect.

Description

SRAM memory single particle and charge-discharge effect test system and method based on FPGA

Technical Field

The invention relates to the technical field of single event and charge and discharge effect testing, in particular to a system and a method for testing single event and charge and discharge effect of an SRAM (static random access memory) based on an FPGA (field programmable gate array), and particularly relates to a testing method for detecting internal storage data upset of the SRAM due to the single event effect and the charge and discharge effect.

Background

The SRAM device refers to a Static Random-Access Memory (SRAM), and the structure is characterized in that data stored inside can be maintained as long as power is maintained, and the stored data disappears when power is lost. The SRAM memory has been widely used in satellite electronic systems, such as memories of satellite computers and payload systems, because of its advantages of fast read/write, large storage capacity, low power consumption, etc. However, the single event effect and the charge and discharge effect caused by the space radiation can cause the restarting, latching, overturning and other faults of the satellite-borne SRAM, and the ground simulation test verification of the single event effect and the charge and discharge effect of the SRAM becomes vital as the requirements for the long service life and the high reliability of the satellite are gradually improved.

The phenomenon of internal storage data upset caused by charge and discharge effects of the SRAM device is very similar to that of internal storage data upset caused by single event effect, and the existing SRAM memory space radiation effect test methods only aim at the single event effect, cannot evaluate faults induced by the charge and discharge effects, and cannot distinguish the faults. There is no test method for SRAM memory single particle and charge-discharge comprehensive effect.

Patent document CN108133731A discloses an atmospheric neutron-induced SRAM device failure rate detection method and system, which performs atmospheric neutron single event effect detection on an SRAM array to obtain measurement data of the atmospheric neutron single event effect detection of the SRAM array; acquiring the total capacity of the SRAM array; and obtaining the failure rate of the SRAM device according to the measurement data and the total capacity of the SRAM array. The patent leaves room for improvement in both structure and performance.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide an SRAM memory single event and charge-discharge effect test system and method based on an FPGA.

The invention provides an SRAM memory single event and charge-discharge effect test system based on an FPGA, which comprises: a test unit; the test unit comprises a PC (personal computer), an upper computer, a lower computer, a single event effect simulation source, a charge-discharge effect simulation source and an electromagnetic shielding unit; the PC is connected with the upper computer through a serial port; the upper computer is connected with the lower computer through a shielding wire; the lower computer is arranged in the environment of a single event effect simulation source or a charge-discharge effect simulation source; the PC, the upper computer and the power supply unit are arranged in the electromagnetic shielding unit.

Preferably, the PC includes: PC hardware devices and control software; and the PC is connected with the upper computer through a serial port. The PC is connected with an upper computer containing an FPGA control chip through a serial port and is used for sending a control instruction to the upper computer, controlling the upper computer, receiving data from the upper computer, realizing functions of data analysis and the like.

Preferably, the upper computer includes: the device comprises an FPGA control chip, a power supply module, an OSC module, an RS422 interface, a communication interface component with a lower computer, a Flash chip and a JTAG interface; the Flash chip is used for storing an FPGA configuration file of the upper computer; the JTAG interface is used for testing and directly configuring an upper computer FPGA; the upper computer comprises an FPGA control module (Xilinx company chip), a power supply module, an OSC (open channel computer), an RS422 interface, a communication interface module with the lower computer, a Flash chip, a JTAG (joint test action group) interface and the like; the FPGA is an upper computer control chip.

Preferably, the lower computer includes: an SRAM circuit board to be tested; the SRAM circuit board to be tested comprises: SRAM chip, power module, IO mouth to be measured.

Preferably, the single event effect simulation source includes any one of: -a heavy ion accelerator; -a proton accelerator; -a source of californium; -a pulsed laser; and selecting a proper simulation source according to experimental needs.

Preferably, the charge-discharge effect simulation source includes: the device comprises an electrostatic discharge generator, an electron gun and a radioactive source, and a proper simulation source is selected according to experimental needs.

Preferably, the method further comprises the following steps: a power supply unit; the power supply unit provides constant power supplies for the PC, the upper computer and the lower computer; the power supply unit can limit and protect the threshold value larger than the set current.

Preferably, the electromagnetic shielding unit includes: metal sheet, faraday cage. The electromagnetic shielding unit is used for testing the charging and discharging effect of the chip, the lower computer, the upper computer, the PC and the testing equipment are isolated, when the simulation source generates a discharging pulse at one end of the lower computer, the reflection is realized through the metal plate, and the interference of the discharging pulse on the upper computer, the PC and the testing equipment is relieved.

According to the SRAM memory single particle and charge-discharge effect test method based on the FPGA, the SRAM memory single particle and charge-discharge effect test system based on the FPGA is adopted, and comprises the following steps:

step S1: building a test unit before an irradiation test, and arranging a lower computer containing an SRAM device to be tested in a charge-discharge effect simulation source environment;

step S2: powering up a test system;

step S3: configuring an FPGA control module of an upper computer; the following two ways can be adopted:

1) through PC, configure with JTAG interface;

2) the FLASH chip is configured in an SPI form through an upper computer board;

step S4: and writing test data into the SRAM device to be tested. Specifically, the PC transmits a write command, a write address and data (such as 55H) to be written into an SRAM memory to an upper computer FPGA control module through a communication interface; after receiving the writing requirement of the PC terminal, the FPGA control module of the upper computer decodes and executes a writing time sequence to the SRAM to be tested, and transmits data to the SRAM device to be tested; the SRAM device to be tested receives test data sent by the upper computer;

step S5: checking whether the SRAM device to be tested successfully writes data; specifically, the PC transmits a reading instruction and a reading address to an upper computer FPGA control module through a communication interface; the FPGA control module of the upper computer receives the reading requirement of the PC end, decodes and executes a reading time sequence, reads the data of the SRAM device to be tested and transmits the data to the PC in real time; and the PC receives the result returned by the upper computer and compares the result with the written data. If the data are the same, the SRAM writes the data successfully, and the next step can be carried out; if the difference indicates that the SRAM fails to write the data, checking each module of the PC, the upper computer and the lower computer and executing the step S2;

step S6: starting a charge-discharge effect simulation source for irradiation; when the charge-discharge effect simulation source is an electrostatic discharge generator, the discharge voltage of the electrostatic discharge generator is adjusted, the gun head can be used for discharging a coupling metal plate to generate electromagnetic pulses, and the electromagnetic pulses are coupled to the SRAM device to be tested through radiation conduction, or the gun head can be used for directly injecting, discharging and coupling pins of the SRAM device to be tested into the device; when the charge-discharge effect simulation source is an electron gun or a radioactive source, a satellite dielectric material is selected as an irradiated object, and discharge pulse radiation is generated through electron irradiation or injected into an SRAM (static random access memory) device;

step S7: reading data of the SRAM device to be tested after irradiation; specifically, the PC transmits a reading instruction and a reading address to an upper computer FPGA control module through a communication interface; the FPGA control module of the upper computer receives the reading requirement of the PC end, decodes and executes a reading time sequence, reads the data of the SRAM device to be tested and transmits the data to the PC in real time; and the PC machine receives the result returned by the upper computer, judges whether the data received by the PC machine is consistent with the written data or not, if not, indicates that data overturning occurs, and records the stored data overturning result caused by charging and discharging.

When the PC and the upper computer cannot perform reading and writing operations, namely the PC and the upper computer are considered to be interrupted due to the influence of the charging and discharging effects, at the moment, the phenomenon data is recorded, the system power supply is disconnected, the PC and the upper computer are electrified again, the step S2 is executed, and the restarting detection process is started.

Step S8: if the data in the SRAM memory is not turned or the number of turned data does not meet the requirement, repeating the steps S6-S7, and properly adjusting the charge-discharge simulation parameters; if the data in the SRAM memory is to be updated, repeating the steps S4-S7;

step S9: stopping testing when the discharge times or the data turnover number in the SRAM memory meet the requirements, and recording the stored data turnover result caused by charging and discharging;

step S10: moving the lower computer to a single event effect simulation source environment, and building a test system;

step S11: powering up a test system;

step S12: an FPGA control module of an upper computer is configured,

the method comprises two modes: 1) through PC, configure with JTAG interface;

2) the FLASH chip is configured in an SPI form through an upper computer board;

step S13: and writing test data into the SRAM device to be tested. (ii) a

Step S14: checking whether the SRAM device to be tested successfully writes data, and if the data are successfully written, performing the next step; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S13;

step S15: starting a single event effect simulation source to irradiate;

step S16: stopping irradiation when the irradiation fluence meets the requirement, and simultaneously stopping testing;

step S17: moving the lower computer to a charge-discharge effect simulation source environment again, and building a test system;

step S18: powering up a test system;

step S19: configuring an FPGA control module of an upper computer, comprising two modes: 1) through PC, configure with JTAG interface; 2) the FLASH chip is configured in an SPI form through an upper computer board;

step S20: and writing test data into the SRAM device to be tested.

Step S21: and checking whether the SRAM device to be tested successfully writes data. If the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S20;

step S22: starting a charge-discharge effect simulation source for irradiation;

step S23: and reading the data of the SRAM device to be tested after irradiation, judging whether the received data is consistent with the written data, if not, indicating that data turnover occurs, and recording the stored data turnover result caused by charging and discharging.

When the PC and the upper computer cannot perform reading and writing operations, namely the PC and the upper computer are considered to be interrupted due to the influence of the charging and discharging effects, at the moment, the phenomenon data is recorded, the system power supply is disconnected, the PC and the upper computer are electrified again, the step S18 is executed, and the restarting detection process is started.

Step S24: if the data in the SRAM memory is not turned or the number of turned data does not meet the requirement, repeating the steps S22-23, and properly adjusting the charge-discharge simulation parameters; if the data in the SRAM memory needs to be updated, the steps S20-23 are repeated;

step S25: stopping testing when the discharge times or the data turnover number in the SRAM memory meet the requirements, and recording the stored data turnover result caused by charging and discharging;

step S26: comparing the stored data upset results caused by charging and discharging before and after the SRAM device is irradiated by the single particles in the step S9 and the step S25, and obtaining the influence rule result information of the single particle effect irradiation on the charging and discharging effect.

According to the SRAM memory single particle and charge-discharge effect test method based on the FPGA, the SRAM memory single particle and charge-discharge effect test system based on the FPGA is adopted, and the method comprises the following steps:

step S1: building a test unit before an irradiation test, and arranging a lower computer comprising an SRAM device to be tested in a single event effect simulation source environment;

step S2: the testing system is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S3: configuring an FPGA control module of an upper computer, comprising two modes: 1) through PC, configure with JTAG interface; 2) the FLASH chip is configured in an SPI form through an upper computer board;

step S4: and writing test data into the SRAM device to be tested. Specifically, the PC transmits a write command, a write address and data (such as 55H) to be written into an SRAM memory to an upper computer FPGA control module through a communication interface; after receiving the writing requirement of the PC terminal, the FPGA control module of the upper computer decodes and executes a writing time sequence to the SRAM to be tested, and transmits data to the SRAM device to be tested; the SRAM device to be tested receives test data sent by the upper computer;

step S5: and checking whether the SRAM device to be tested successfully writes data. Specifically, the PC transmits a reading instruction and a reading address to an upper computer FPGA control module through a communication interface; the FPGA control module of the upper computer receives the reading requirement of the PC end, decodes and executes a reading time sequence, reads the data of the SRAM device to be tested and transmits the data to the PC in real time; and the PC receives the result returned by the upper computer and compares the result with the written data. If the data are the same, the SRAM writes the data successfully, and the next step can be carried out; if the difference indicates that the SRAM fails to write the data, checking each module of the PC, the upper computer and the lower computer and executing the step S2;

step S6: starting a single event effect simulation source to irradiate;

step S7: and reading the data of the SRAM device to be tested after irradiation. Specifically, the PC transmits a reading instruction and a reading address to an upper computer FPGA control module through a communication interface; the FPGA control module of the upper computer receives the reading requirement of the PC end, decodes and executes a reading time sequence, reads the data of the SRAM device to be tested and transmits the data to the PC in real time; and the PC machine receives the result returned by the upper computer, judges whether the data received by the PC machine is consistent with the written data or not, if not, indicates that data overturning occurs, and records and stores the data overturning result.

When the PC and the upper computer cannot perform reading and writing operations, namely, the faults such as function interruption and the like are considered to occur due to the single event effect, at the moment, the phenomenon data is recorded, the system power supply is disconnected, the power supply is powered on again, the step S2 is executed, and the restarting detection process is started.

Step S8: if the data in the SRAM memory is not inverted or the number of inversions does not meet the requirement, repeating the step S6-7, and properly adjusting the single event effect simulation source parameters; if the data in the SRAM memory is to be updated, repeating the step S4-7;

step S9: stopping testing when the irradiation fluence or the data turnover number in the SRAM reaches the requirement, and recording the stored data turnover result caused by the single particle;

step S10: moving the lower computer to a charge-discharge effect simulation source environment, and building a test unit;

step S11: the testing unit is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S12: configuring an FPGA control module of an upper computer, comprising two modes: 1) through PC, configure with JTAG interface; 2) the FLASH chip is configured in an SPI form through an upper computer board;

step S13: writing test data into the SRAM device to be tested;

step S14: checking whether the SRAM device to be tested successfully writes data; if the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S13;

step S15: starting a charge-discharge effect simulation source to perform pulse irradiation; when the charge-discharge effect simulation source is an electrostatic discharge generator, the discharge voltage of the electrostatic discharge generator is adjusted, the gun head can be used for discharging a coupling metal plate to generate electromagnetic pulses which are coupled to the SRAM device to be tested through radiation conduction, and the gun head can also be used for directly injecting, discharging and coupling pins of the SRAM device to be tested into the device; when the charge-discharge effect simulation source is an electron gun or a radioactive source, a satellite dielectric material is selected as an irradiated object, and discharge pulse radiation is generated through electron irradiation or injected into an SRAM (static random access memory) device;

step S16: stopping irradiation when parameters such as the irradiation times of the discharge pulse, the voltage and the like meet requirements, and stopping testing at the same time;

step S17: moving the lower computer to the single event effect simulation source environment again, and building a test unit;

step S18: the testing unit is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S19: configuring an FPGA control module of an upper computer, comprising two modes: 1) through PC, configure with JTAG interface; 2) the FLASH chip is configured in an SPI form through an upper computer board;

step S20: and writing test data into the SRAM device to be tested.

Step S21: and checking whether the SRAM device to be tested successfully writes data. If the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S20;

step S22: starting a single event effect simulation source to irradiate;

step S23: reading data of the SRAM device to be tested after irradiation; judging whether the received data is consistent with the written data, if not, indicating that data turnover occurs, and recording a stored data turnover result caused by charging and discharging;

when the PC and the upper computer cannot perform reading and writing operations, namely, the faults such as function interruption and the like are considered to occur due to the single event effect, at the moment, the phenomenon data is recorded, the system power supply is disconnected, the power supply is powered on again, the step S18 is executed, and the restarting detection process is started;

step S24: if the data in the SRAM memory is not overturned or the overturning quantity does not meet the requirement, repeating the steps S22-S23, and properly adjusting the single event effect simulation source parameters; if the data in the SRAM memory is to be updated, repeating the steps S20-S23;

step S25: stopping testing when the irradiation fluence or the data turnover number in the SRAM reaches the requirement, and recording the stored data turnover result caused by the single particle;

step S26: comparing the stored data upset results caused by the single particles before and after the SRAM device is subjected to charge-discharge irradiation in the step S9 and the step S25, and obtaining the result information of the influence rule of the charge-discharge effect irradiation on the single particle effect of the device.

Compared with the prior art, the invention has the following beneficial effects:

1. the method can acquire characteristic parameters of the SRAM under the comprehensive influence of the single event effect and the charge and discharge effect, such as information parameters of an overturning section, an overturning curve, an overturning threshold value and the like, under the irradiation condition of a laboratory simulation source, and compares the influence of the device on the charge and discharge effect after being irradiated by the single event effect with the influence of the device on the single event effect after being irradiated by the charge and discharge;

2. the invention does not need to replace the upper computer and the PC machine aiming at different effects, and simultaneously, only the lower computer containing the SRAM device to be tested needs to be replaced when different devices are tested, thereby improving the testing efficiency and the accuracy of the capability of the device to be tested for resisting single particles and charge-discharge effects.

3. The invention has reasonable structure and convenient use and can overcome the defects of the prior art.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a schematic view of a process of the influence of a single event effect on a charge-discharge effect after irradiation of a test device provided by the present invention;

FIG. 2 is a schematic view of a process of the single event effect influence of the test device irradiated by the charge and discharge effect.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

Specifically, in an embodiment, as shown in fig. 1-2, a system for comprehensively testing a single event effect and a charge-discharge effect of an SRAM memory based on an FPGA includes a PC, an upper computer, a lower computer, a single event effect simulation source, a charge-discharge effect simulation source, a power supply, an electromagnetic shielding system, and the like.

A method for comprehensively testing the single event effect and the charge-discharge effect of an SRAM based on an FPGA. The test method comprises the following steps: a testing system is set up before an irradiation test, and comprises a PC (personal computer), an upper computer, a lower computer, a single event effect simulation source, a charge-discharge effect simulation source, a power supply, an electromagnetic shielding system and the like. The PC is connected with the upper computer through a serial port, the upper computer is connected with the lower computer through a shielding wire, the lower computer is placed in a simulated source environment, and the PC, the upper computer and the power supply unit are installed in an electromagnetic shielding system;

the PC machine comprises PC hardware equipment and control software, is connected with an upper computer containing an FPGA control chip through a serial port and is used for sending a control instruction to the upper computer, controlling the upper computer, receiving data from the upper computer, realizing functions of data analysis and the like;

the upper computer comprises an FPGA control module (Xilinx company chip), a power supply module, an OSC (open channel computer), an RS422 interface, a communication interface module with the lower computer, a Flash chip, a JTAG (joint test action group) interface and the like; the FPGA is an upper computer control chip; the Flash chip is used for storing an FPGA configuration file of the upper computer; the JTAG interface is used for testing and directly configuring an upper computer FPGA;

the lower computer is a circuit board containing an SRAM to be tested and comprises an SRAM chip to be tested, a power supply module, an IO port and the like;

the single event effect simulation source comprises but is not limited to simulation sources such as heavy ion accelerator, proton accelerator, californium source or pulsed laser, and the appropriate simulation source is selected according to experiment needs;

the charge-discharge effect simulation sources include but are not limited to an electrostatic discharge generator, an electron gun, a radioactive source and the like, and proper simulation sources are selected according to experimental needs;

the power supply unit provides constant power supplies for the PC, the upper computer and the lower computer, and has a large current limiting protection function;

the electromagnetic shielding system is a tool consisting of a metal plate and a Faraday cage, is used for testing the charging and discharging effect of the chip, realizes the isolation of the lower computer, the upper computer, the PC and the testing equipment, realizes the reflection through the metal plate when the analog source generates a discharging pulse at one end of the lower computer, and slows down the interference of the upper computer, the PC and the testing equipment by the discharging pulse.

The working mode is as follows:

the influence of the test device on the charge and discharge effect after being irradiated by the single event effect is shown in fig. 1.

Step S1: building a test system before an irradiation test, and placing a lower computer containing an SRAM device to be tested in a charge-discharge effect simulation source environment;

step S2: the testing system is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S3: configuring an FPGA control module of an upper computer, comprising two modes: 1) through PC, configure with JTAG interface; 2) the FLASH chip is configured in an SPI form through an upper computer board;

step S4: and writing test data into the SRAM device to be tested. Specifically, the PC transmits a write command, a write address and data (such as 55H) to be written into an SRAM memory to an upper computer FPGA control module through a communication interface; after receiving the writing requirement of the PC terminal, the FPGA control module of the upper computer decodes and executes a writing time sequence to the SRAM to be tested, and transmits data to the SRAM device to be tested; the SRAM device to be tested receives test data sent by the upper computer;

step S5: and checking whether the SRAM device to be tested successfully writes data. Specifically, the PC transmits a reading instruction and a reading address to an upper computer FPGA control module through a communication interface; the FPGA control module of the upper computer receives the reading requirement of the PC end, decodes and executes a reading time sequence, reads the data of the SRAM device to be tested and transmits the data to the PC in real time; and the PC receives the result returned by the upper computer and compares the result with the written data. If the data are the same, the SRAM writes the data successfully, and the next step can be carried out; if the difference indicates that the SRAM fails to write the data, checking each module of the PC, the upper computer and the lower computer and executing the step S2;

step S6: and starting a charge-discharge effect analog source for irradiation. When the charge-discharge effect simulation source is an electrostatic discharge generator, the discharge voltage of the electrostatic discharge generator is adjusted, the gun head can be used for discharging a coupling metal plate to generate electromagnetic pulses which are coupled to the SRAM device to be tested through radiation conduction, and the gun head can also be used for directly injecting, discharging and coupling pins of the SRAM device to be tested into the device; when the charge-discharge effect simulation source is an electron gun or a radioactive source, a satellite dielectric material is selected as an irradiated object, and discharge pulse radiation is generated through electron irradiation or injected into an SRAM (static random access memory) device;

step S7: and reading the data of the SRAM device to be tested after irradiation. Specifically, the PC transmits a reading instruction and a reading address to an upper computer FPGA control module through a communication interface; the FPGA control module of the upper computer receives the reading requirement of the PC end, decodes and executes a reading time sequence, reads the data of the SRAM device to be tested and transmits the data to the PC in real time; and the PC machine receives the result returned by the upper computer, judges whether the data received by the PC machine is consistent with the written data or not, if not, indicates that data overturning occurs, and records the stored data overturning result caused by charging and discharging.

When the PC and the upper computer cannot perform reading and writing operations, namely the PC and the upper computer are considered to be interrupted due to the influence of the charging and discharging effects, at the moment, the phenomenon data is recorded, the system power supply is disconnected, the PC and the upper computer are electrified again, the step S2 is executed, and the restarting detection process is started.

Step S8: if the data in the SRAM memory is not turned or the number of turned data does not meet the requirement, repeating the steps S6-S7, and properly adjusting the charge-discharge simulation parameters; if the data in the SRAM memory needs to be updated, repeating the steps S4-7;

step S9: stopping testing when the discharge times or the data turnover number in the SRAM memory meet the requirements, and recording the stored data turnover result caused by charging and discharging;

step S10: moving the lower computer to a single event effect simulation source environment, and building a test system;

step S11: the testing system is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S12: configuring an FPGA control module of an upper computer, comprising two modes: 1. through PC, configure with JTAG interface; 2. the FLASH chip is configured in an SPI mode through an upper computer board;

step S13: and writing test data into the SRAM device to be tested. (ii) a

Step S14: and checking whether the SRAM device to be tested successfully writes data. If the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S13;

step S15: starting a single event effect simulation source to irradiate;

step S16: stopping irradiation when the irradiation fluence meets the requirement, and simultaneously stopping testing;

step S17: moving the lower computer to a charge-discharge effect simulation source environment again, and building a test system;

step S18: the testing system is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S19: configuring an FPGA control module of an upper computer, comprising two modes: 1. through PC, configure with JTAG interface; 2. the FLASH chip is configured in an SPI mode through an upper computer board;

step S20: and writing test data into the SRAM device to be tested.

Step S21: and checking whether the SRAM device to be tested successfully writes data. If the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S20;

step S22: and starting a charge-discharge effect analog source for irradiation.

Step S23: and reading the data of the SRAM device to be tested after irradiation. And judging whether the received data is consistent with the written data, if not, indicating that data inversion occurs, and recording a stored data inversion result caused by charging and discharging.

When the PC and the upper computer cannot perform reading and writing operations, namely the PC and the upper computer are considered to be interrupted due to the influence of the charging and discharging effects, at the moment, the phenomenon data is recorded, the system power supply is disconnected, the PC and the upper computer are electrified again, the step S18 is executed, and the restarting detection process is started.

Step S24: if the data in the SRAM memory is not turned or the number of turned data does not meet the requirement, repeating the steps S22-23, and properly adjusting the charge-discharge simulation parameters; if the data in the SRAM memory is to be updated, repeating the steps S20-23;

step S25: stopping the test when the discharge times or the data turnover number in the SRAM meet the requirements, and recording the storage data turnover result caused by charge and discharge;

step S26: comparing the stored data upset results caused by charging and discharging before and after the SRAM device is irradiated by the single particles in the step S9 and the step S25, and summarizing the rule of the influence of the single particle effect irradiation on the charging and discharging effect.

The influence of the test device on the single event effect after being irradiated by charging and discharging is shown in fig. 2. Step S1: building a test system before an irradiation test, and placing a lower computer containing an SRAM device to be tested in a single event effect simulation source environment;

step S2: the testing system is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S3: configuring an FPGA control module of an upper computer, comprising two modes: 1) through PC, configure with JTAG interface; 2) the FLASH chip is configured in an SPI form through an upper computer board;

step S4: and writing test data into the SRAM device to be tested. Specifically, the PC transmits a write command, a write address and data (such as 55H) to be written into an SRAM memory to an upper computer FPGA control module through a communication interface; after receiving the writing requirement of the PC terminal, the FPGA control module of the upper computer decodes and executes a writing time sequence to the SRAM to be tested, and transmits data to the SRAM device to be tested; the SRAM device to be tested receives test data sent by the upper computer;

step S5: and checking whether the SRAM device to be tested successfully writes data. Specifically, the PC transmits a reading instruction and a reading address to an upper computer FPGA control module through a communication interface; the FPGA control module of the upper computer receives the reading requirement of the PC end, decodes and executes a reading time sequence, reads the data of the SRAM device to be tested and transmits the data to the PC in real time; and the PC receives the result returned by the upper computer and compares the result with the written data. If the data are the same, the SRAM writes the data successfully, and the next step can be carried out; if the difference indicates that the SRAM fails to write the data, checking each module of the PC, the upper computer and the lower computer and executing the step S2;

step S6: starting the single event effect simulation source to irradiate.

Step S7: and reading the data of the SRAM device to be tested after irradiation. Specifically, the PC transmits a reading instruction and a reading address to an upper computer FPGA control module through a communication interface; the FPGA control module of the upper computer receives the reading requirement of the PC end, decodes and executes a reading time sequence, reads the data of the SRAM device to be tested and transmits the data to the PC in real time; and the PC machine receives the result returned by the upper computer, judges whether the data received by the PC machine is consistent with the written data or not, if not, indicates that data overturning occurs, and records the data overturning result stored.

When the PC and the upper computer cannot perform reading and writing operations, namely, the faults such as function interruption and the like are considered to occur due to the single event effect, at the moment, the phenomenon data is recorded, the system power supply is disconnected, the power supply is powered on again, the step S2 is executed, and the restarting detection process is started.

Step S8: if the data in the SRAM memory is not turned or the turning quantity does not meet the requirement, repeating the step S6-7, and properly adjusting the single event effect simulation source parameters; if the data in the SRAM memory needs to be updated, repeating the steps S4-7;

step S9: stopping testing when the irradiation fluence or the data turnover number in the SRAM reaches the requirement, and recording the stored data turnover result caused by the single particle;

step S10: moving the lower computer to a charge-discharge effect simulation source environment, and building a test system;

step S11: the testing system is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S12: configuring an FPGA control module of an upper computer, comprising two modes: 1. through PC, configure with JTAG interface; 2. the FLASH chip is configured in an SPI form through an upper computer board;

step S13: and writing test data into the SRAM device to be tested. (ii) a

Step S14: and checking whether the SRAM device to be tested successfully writes data. If the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S13;

step S15: starting a charge-discharge effect simulation source to perform pulse irradiation; when the charge-discharge effect simulation source is an electrostatic discharge generator, the discharge voltage of the electrostatic discharge generator is adjusted, the gun head can be used for discharging a coupling metal plate to generate electromagnetic pulses which are coupled to the SRAM device to be tested through radiation conduction, and the gun head can also be used for directly injecting, discharging and coupling pins of the SRAM device to be tested into the device; when the charge-discharge effect simulation source is an electron gun or a radioactive source, a satellite dielectric material is selected as an irradiated object, and discharge pulse radiation is generated through electron irradiation or injected into an SRAM (static random access memory) device;

step S16: stopping irradiation when parameters such as the irradiation times of the discharge pulse, the voltage and the like meet requirements, and stopping testing at the same time;

step S17: moving the lower computer to the single event effect simulation source environment again, and building a test system;

step S18: the testing system is powered on and comprises a PC (personal computer), an upper computer, a lower computer and a power supply unit;

step S19: configuring an FPGA control module of an upper computer, comprising two modes: 1. through PC, configure with JTAG interface; 2. the FLASH chip is configured in an SPI form through an upper computer board;

step S20: and writing test data into the SRAM device to be tested.

Step S21: and checking whether the SRAM device to be tested successfully writes data. If the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S20;

step S22: starting the single event effect simulation source to irradiate.

Step S23: and reading the data of the SRAM device to be tested after irradiation. And judging whether the received data is consistent with the written data, if not, indicating that data inversion occurs, and recording the inversion result of the stored data caused by charging and discharging.

When the PC and the upper computer cannot perform reading and writing operations, namely, the faults such as function interruption and the like are considered to occur due to the single event effect, at the moment, the phenomenon data is recorded, the system power supply is disconnected, the power supply is powered on again, the step S18 is executed, and the restarting detection process is started.

Step S24: if the data in the SRAM memory is not turned or the turning quantity does not meet the requirement, repeating the step S22-23, and properly adjusting the single event effect simulation source parameters; if the data in the SRAM memory needs to be updated, the steps S20-23 are repeated;

step S25: stopping testing when the irradiation fluence or the data turnover number in the SRAM reaches the requirement, and recording the stored data turnover result caused by the single particle;

step S26: comparing the stored data upset results caused by the single particles before and after the SRAM device is subjected to charge-discharge irradiation in the step S9 and the step S25, and summarizing the rule of influence of the charge-discharge effect irradiation on the single particle effect of the device.

In conclusion, the invention can test the SRAM memory single particle and charge-discharge comprehensive effect.

In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (2)

1. A SRAM memory single particle and charge-discharge effect test method based on FPGA is characterized in that an SRAM memory single particle and charge-discharge effect test system based on FPGA is adopted, and the method comprises the following steps: a test unit;

the test unit comprises a PC (personal computer), an upper computer, a lower computer, a single event effect simulation source, a charge-discharge effect simulation source and an electromagnetic shielding unit;

the PC is connected with the upper computer through a serial port;

the upper computer is connected with the lower computer through a shielding wire;

the lower computer is arranged in the environment of a single event effect simulation source or a charge-discharge effect simulation source;

the PC, the upper computer and the power supply unit are arranged in the electromagnetic shielding unit;

the PC machine includes: PC hardware devices and control software;

the PC is connected with the upper computer through a serial port;

the host computer includes: the device comprises an FPGA control chip, a power supply module, an OSC module, an RS422 interface, a communication interface component with a lower computer, a Flash chip and a JTAG interface;

the Flash chip is used for storing an FPGA configuration file of the upper computer;

the JTAG interface is used for testing and directly configuring an upper computer FPGA;

the lower computer comprises: an SRAM circuit board to be tested;

the SRAM circuit board to be tested comprises: the device comprises an SRAM chip to be tested, a power supply module and an IO port;

the single event effect simulation source comprises any one of the following:

-a heavy ion accelerator;

-a proton accelerator;

-a source of californium;

-a pulsed laser;

the charge-discharge effect simulation source comprises any one of the following:

-an electrostatic discharge generator;

-an electron gun;

-a radioactive source;

further comprising: a power supply unit;

the power supply unit can limit and protect the current with the threshold value larger than the set value

The electromagnetic shielding unit includes: metal plates, faraday cages;

the test method comprises the following steps:

step S1: building a test unit before an irradiation test, and arranging a lower computer containing an SRAM device to be tested in a charge-discharge effect simulation source environment;

step S2: powering up a test system;

step S3: configuring an FPGA control module of an upper computer;

step S4: writing test data into the SRAM device to be tested;

step S5: checking whether the SRAM device to be tested successfully writes data;

step S6: starting a charge-discharge effect simulation source for irradiation;

step S7: reading data of the SRAM device to be tested after irradiation;

step S8: if the data in the SRAM memory is not overturned or the overturning quantity does not meet the requirement, repeating the steps S6-S7, and adjusting the charge-discharge simulation parameters;

if the data in the SRAM memory is updated, repeating the steps S4-S7;

step S9: stopping testing when the discharge times or the data turnover number in the SRAM memory meet the requirements, and recording the stored data turnover result caused by charging and discharging;

step S10: moving the lower computer to a single event effect simulation source environment, and building a test system;

step S11: powering up a test system;

step S12: an FPGA control module of an upper computer is configured,

step S13: writing test data into the SRAM device to be tested;

step S14: checking whether the SRAM device to be tested successfully writes data, and if the data are successfully written, performing the next step; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S13;

step S15: starting a single event effect simulation source to irradiate;

step S16: stopping irradiation when the irradiation fluence meets the requirement, and simultaneously stopping the test;

step S17: moving the lower computer to a charge-discharge effect simulation source environment again, and building a test system;

step S18: powering up a test system;

step S19: configuring an FPGA control module of an upper computer;

step S20: writing test data into the SRAM device to be tested;

step S21: checking whether the SRAM device to be tested successfully writes data; if the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S20;

step S22: starting a charge-discharge effect simulation source for irradiation;

step S23: reading data after irradiation of an SRAM device to be tested, judging whether the received data is consistent with the written data, if not, indicating that data turnover occurs, and recording a stored data turnover result caused by charging and discharging;

when the PC and the upper computer cannot perform reading and writing operations, recording phenomenon data, disconnecting a system power supply, electrifying again, executing the step S18, and starting to perform a restart detection process;

step S24: if the data in the SRAM memory is not overturned or the overturning quantity does not meet the requirement, repeating the step S22-23, and adjusting the charge-discharge simulation parameters; if the data in the SRAM memory is to be updated, repeating the step S20-23;

step S25: stopping testing when the discharge times or the data turnover number in the SRAM memory meet the requirements, and recording the stored data turnover result caused by charging and discharging;

step S26: comparing the stored data upset results caused by charging and discharging before and after the SRAM device is irradiated by the single particles in the step S9 and the step S25, and obtaining the influence rule result information of the single particle effect irradiation on the charging and discharging effect.

2. An SRAM memory single event and charge-discharge effect test method based on FPGA is characterized in that the SRAM memory single event and charge-discharge effect test method based on FPGA of claim 1 is adopted, and comprises the following steps:

step S1: building a test unit before an irradiation test, and arranging a lower computer comprising an SRAM device to be tested in a single event effect simulation source environment;

step S2: powering up a test system;

step S3: configuring an FPGA control module of an upper computer;

step S4: writing test data into the SRAM device to be tested;

step S5: checking whether the SRAM device to be tested successfully writes data;

step S6: starting a single event effect simulation source to irradiate;

step S7: reading data of the SRAM device to be tested after irradiation;

step S8: if the data in the SRAM memory is not overturned or the overturning quantity does not meet the requirement, repeating the steps S6-S7, and adjusting the single event effect simulation source parameters; if the data in the SRAM memory is to be updated, repeating the steps S4-S7;

step S9: stopping testing when the irradiation fluence or the data turnover number in the SRAM reaches the requirement, and recording the stored data turnover result caused by the single particle;

step S10: moving the lower computer to a charge-discharge effect simulation source environment, and building a test unit;

step S11: powering up the test unit;

step S12: configuring an FPGA control module of an upper computer;

step S13: writing test data into the SRAM device to be tested;

step S14: checking whether the SRAM device to be tested successfully writes data; if the data is successfully written, the next step can be carried out; if the data writing fails, checking each module of the PC, the upper computer and the lower computer and executing the step S13;

step S15: starting a charge-discharge effect simulation source to perform pulse irradiation;

step S16: stopping irradiation when parameters such as the irradiation times of the discharge pulse, the voltage and the like meet requirements, and stopping testing at the same time;

step S17: moving the lower computer to the single event effect simulation source environment again, and building a test unit;

step S18: powering up the test unit;

step S19: configuring an FPGA control module of an upper computer;

step S20: writing test data into the SRAM device to be tested;

step S21: checking whether the SRAM device to be tested successfully writes data; if the data is successfully written, the next step can be carried out; if the data writing fails, checking the PC, the upper computer and the lower computer and executing the step S20;

step S22: starting a single event effect simulation source to irradiate;

step S23: reading data of the SRAM device to be tested after irradiation; judging whether the received data is consistent with the written data, and if not, recording a stored data overturning result caused by charging and discharging;

when the PC and the upper computer cannot perform reading and writing operations, recording phenomenon data, disconnecting a system power supply, electrifying again, executing the step S18, and starting to perform a restart detection process;

step S24: if the data in the SRAM memory is not overturned or the overturning quantity does not meet the requirement, repeating the steps S22-S23, and adjusting the single event effect simulation source parameters; if the data in the SRAM memory is updated, repeating the steps S20-S23;

step S25: stopping testing when the irradiation fluence or the data overturning quantity in the SRAM reaches the requirement, and recording the stored data overturning result caused by the single particle;

step S26: comparing the stored data upset results caused by the single particles before and after the SRAM device is subjected to charge-discharge irradiation in the step S9 and the step S25, and obtaining the result information of the influence rule of the charge-discharge effect irradiation on the single particle effect of the device.

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