CN1120572C - Delay device calibrated by phase-locked loop and its calibration method - Google Patents
Delay device calibrated by phase-locked loop and its calibration method Download PDFInfo
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Abstract
The present invention relates to a delay device calibrated by a phase-locked loop and a calibration method thereof. The delay device has the function of receiving an input signal and outputting a delay output signal after delayed for preset time, the input signal is changed by referring to a clock signal, and the required delay time is a quarter of a cycle of the clock signal. The delay device comprises a multiplexer, a phase inverter, a phase detector, a counter and a delay element, wherein a phase-locked loop is composed of the phase detector, the counter and the delay element in the process of calibration. The present invention can automatically calibrate the required delay time.
Description
The invention relates to a kind of device of signal delay and determine the method for its time of delay, and particularly come adjustment deferred mount and the adjusting process of time of delay relevant for a kind of phase-locked loop that uses.
By means of the semiconductor scientific and technological progress, the progress of the operational capability of computer is at a tremendous pace.Present computer is made of digital circuit, during its running, all is with reference to same or several clocks (clock), makes intrasystem different device Collaboration each other.
In early days, the running speed of computer is lower, and the transfer of data between different device can transmit in better simply mode.
Please refer to Fig. 1, it illustrates the mode that cooperates clock to transmit data.As shown in FIG., the data that signal DAT representative transmits, signal CLK then is the waveform of system clock, and wherein data-signal DAT changes along with clock signal clk, so receiving terminal can correctly receive the data-signal DAT that sends the transmission end according to the variation of clock signal clk.But this kind data mode only is applicable to the slow system of early stage running, and after the operation frequency of system promotes, the mode that this kind cooperates clock signal to transmit data can't be guaranteed the correctness that data transmit.Its issuable problem will be described below.
Please refer to Fig. 2, its illustrate is transmitted the circuit block diagram of data for cooperating clock.As shown in FIG., conveyer 210 sends data-signal DAT to receiving system 220 via lead 230, the process that is transmitting, can make the part of signal delay, comprise the circuit transmission delay (Flight time) that the buffer (Buffer) 214 of conveyer 210 and receiving system 220 inside and 224 delays that produced and transfer wire 230 are produced, in addition the trigger 222 of the trigger 212 of conveyer 210 and receiving system 220 inside all reference clock signal CLK come locking data, and clock signal clk is in the process that lead 240 transmits, owing to the delay of circuit, also can produce the problem of clock skew (Clock Skew).In the digital system of a reality, the clock signal of transmission end and receiving terminal can have the delay of 2～3ns.Based on above-mentioned considering, in order correctly to transmit data, must prolong the time that data keep (hold), therefore can't improve the frequency of clock signal, also just make to be difficult to break through on the data transmission bauds.
In order to improve the problem of above-mentioned clock signal delay, further improve the usefulness of transfer of data, be to develop the transmission that cooperates data with data strobe signal (Data Strobe), make data when transmitting, be unlikely because of the speed raising and make data loss.Please refer to Fig. 3 A and Fig. 3 B, wherein Fig. 3 A illustrate is the block diagram of circuit, and Fig. 3 B is the oscillogram of its signal.As shown in the figure, the trigger 316 of conveyer 310 converts clock signal clk to data strobe signal DS, then data-signal DAT is accompanied by data strobe signal DS and transmits, the trigger 322 of receiving system 320 promptly can receive data according to data strobe signal DS.So, can eliminate (T time of delay of buffer
Bufer) and (T time of delay of transfer wire
Flight), and rising edge and falling edge at data strobe signal DS all can transmit data, be that Double Data reads (Double Data Read, abbreviation DDR) function mode, DDR SDRAM (synchronous RAM for example, Synchronous Dynamic Random AccessMemory is called for short SDRAM).Suppose not consider the skew (Skew) of the data strobe signal DS between transmission end and receiving terminal, then the speed of transfer of data only is subject to the settling time (setup time) and the retention time (hold time) of the trigger (flip flop) of receiving terminal, its time approximately about 1ns, comprises the settling time of 0.5ns and the retention time of 0.5ns.
In the practical application of industrial circle, be to produce data strobe signal DS with the practice at transmission end synchronous driving data-signal DAT and data strobe signal DS.That is the transmission end sends data-signal DAT and data strobe signal DS simultaneously at the edge of same clock signal, by identical deferring procedure (trace) balance (T time of delay of buffer and transmission line
BufferAnd T
Flight), and skew (skew) between data-signal DAT and the data strobe signal DS is reached minimize.The sequential chart of transmission end sees also Fig. 3 B and illustrates.But carry out because the access of data is rising edge and falling edges at data strobe signal DS,, can guarantee that just correct access is to data so receiving terminal must postpone a period of time with data strobe signal DS.
Please refer to Fig. 4 A and Fig. 4 B, wherein Fig. 4 A illustrate is into adding the block diagram of data delay element at receiving terminal, and Fig. 4 B illustrate is sequential chart.As shown in the figure, through behind the delay element, the rising edge of data strobe signal DS ' after the resulting delay of triggering (trigger) of the trigger of receiving terminal and falling edge are all in the part of the stable state of data-signal DAT, so trigger can lock onto correct data.
There are several modes can make delay element in fact, for example utilize the circuit of prolongation circuitous on the printed substrate that the transmission time is prolonged, or in integrated circuit, use passive device to do delay element.But these methods are not very desirable, for example utilize the extension wire on the printed substrate to do delay element, in complicated day by day now computer system, have ten different data strobe signals of surpassing, making every effort to not have the wiring that enough areas are done delay element on the printed circuit board (PCB) of miniaturization.On the other hand, in integrated circuit, use passive device to do the mode of delay element, because the problem of processing procedure, have very big error the time of delay of the delay element of making, its maximum and minimum value may reach the difference of twice, for example will manufacture the delay element of 1ns time of delay, the time of delay of its finished product may be between 0.67us to 2ns.
In fact, the design of delay element is very difficult, no matter because be too much or very few the time of delay of data strobe signal, all can make receiving terminal receive incorrect data.Can receiving terminal receive correct data, depends on that retardation between data strobe signal DS and the data-signal DAT is (in case with D
Ds_daRepresent) whether suitable, that is whether the rising edge of data strobe signal DS or falling edge drop in the stability region of correct readout data signal DAT.
Influence the retardation D between data strobe signal DS and the data-signal DAT
Ds_daFactor comprise: 1. pure in data strobe signal DS and skew data-signal DAT (in case with ρ s represent) of transmission end to receiving terminal.2. the delay that delay element caused (in case representing) with sd.
So retardation D between data strobe signal DS and the data-signal DAT
Ds_daBe ρ s+sd.
The factor that influences signal bias ρ s comprises: the difference of the start voltage (threshold) of the difference of the difference of output buffer, the wiring of printed substrate, output buffer, the settling time that reaches trigger and the difference of retention time ... etc.On the other hand, influence delay element time of delay sd factor then comprise: the frequency of the design of delay element, temperature, humidity, voltage, different CPU, and electromagnetic interference ... etc.Under all multifactor dynamic effects, be example with the operation frequency of 66Mhz, may have the difference of 0.5～1.8ns, instability very.And, under different operation frequencies, for example 66Mhz, 75Mhz, 83Mhz, 100Mhz, and 133Mhz... etc., the retardation that is produced has nothing in common with each other again, along with the raising of operation frequency, the cycle of clock signal becomes short more, and the patient offset error scope of institute of system is just low more.Is it just suitable that data strobe signal will postpone how many values on earth? if the time that data strobe signal DS postpones is oversize or too short, receiving terminal all can't receive correct data.So system can't normal operation, very then works as machine.But, when through after the detailed calculating, obtain a length of delay after, but may be because the change of factors such as temperature, voltage, frequency or electromagnetic interference, ρ s and sd are changed, make length of delay originally no longer drop on the scope the inside in best limit (best margin).Therefore, adopt above solution, when system in order to reach high-speed data transmission rate, often have data loss or when the danger of machine.
At the problems referred to above, industrial circle has the people to propose another kind of new solution, its conception is to allow time of 1/4th in the cycle of data strobe signal DS delay clock signals CLK, no matter the clock frequency of institute's reference why during System Operation, data strobe signal DS after the delay is begun at the positive half cycle of clock signal clk or the mid portion of negative half period forever, so can guarantee to receive correct data.
Please refer to Fig. 5, its illustrate is the circuit block diagram of the time of delay of 1/4th clock signal periods of generation of known technology.
As shown in the figure, delay element 511,512,513, and 514, phase detectors 520, and counter 530 constitute a phase-locked loop, can make two input I1 of phase detectors 520 and I2 signal phase place as far as possible near or equate.Wherein delay element 511,512,513,514, and 515 be all the same delay element of characteristic, that is when by its other control end C input delay parameter the time, will be the same the time of delay of each delay element.
Suitable selection delay element 511,512,513, and 514, can make delay element 511,512,513, and 514, phase detectors 520, and the phase-locked loop that constituted of counter 530 when stable state, be the signal that clock signal clk postpones one-period in the signal of the input I1 of phase detectors 520 gained.Because delay element 511,512,513,514, and 515 characteristic be the same, therefore at this moment, delay element 511,512,513,514, reach 1/4th of cycle that is all clock signal time of delay all mutually of 515.Wherein delay element 515 promptly can be used to the delay element as the data strobe signal DS of receiving terminal.
Though above-mentioned employing phase-locked loop decides the method for the delay parameter of delay element, can determine time of delay accurately, in phase-locked loop, must use four delay elements simultaneously, and delay element can take sizable area on chip.And in present computer system, the system clock of multiple frequency is used in the capital simultaneously, at each system clock, all must there be one group of this kind phase-locked loop to decide the delay parameter of relevant delay element, if adopt this kind practice, will occupy many areas, this is quite uneconomic.
Comprehensive above-mentioned discussion, known as can be known delay element has following shortcoming:
1. use extension lead to make the method for signal delay, time of control lag accurately, and to take the area of bigger printed substrate, can not be applicable to various operation frequency.
2. using passive device to make the practice of signal delay, also is control lag time accurately, and influenced by various external factors and change its length of delay, and the while can not be applicable to various operation frequency.
3. use phase-locked loop to decide delay parameter,, also can be applicable to different operation frequencies though can obtain required length of delay accurately, more uneconomical.When system needs a plurality of different deferred mount, promptly need extra many groups circuit, can take bigger chip area.
Therefore a purpose of the present invention is exactly a kind of energy deferred mount of accurate control lag time to be provided, can be applicable to different operation frequencies, and is not subject to the influence of external variable.
Another object of the present invention provides a kind of deferred mount of less expensive, can dwindle the required chip area of total system.
Another purpose of the present invention is a kind of adjusting process that uses the deferred mount of phase-locked loop adjustment to be provided, can to determine required time of delay accurately.
For reaching above-mentioned and other purposes of the present invention, the present invention proposes a kind of deferred mount that uses the phase-locked loop adjustment, and the function of this deferred mount is for accepting an input signal, then it is postponed a scheduled time after, export a delay output signal.This input signal is for changing with reference to a clock signal, and the time of delay that needs be this clock signal cycle 1/4th.
This deferred mount comprises multiplexer, trigger, phase detectors, counter, reaches delay element.
Wherein, multiplexer can be selected a multiplex signal as output in this input signal and a reference signal among the two according to a state of selecting signal, and this reference signal is the frequency-doubled signal of this clock signal.The effect of inverter is then for anti-phase to produce complementary reference signal with reference signal.
Phase detectors have a first input end, one second input, reach an output, and wherein first input end is accepted this complementation reference signal, and second input is then accepted the signal of this multiplex signal through this delay element.
Counter has an input and an output, and this input is coupled to the output of these phase detectors, in order to change a count value of this output output.
Delay element has an input, an output, reaches a control end, this input is accepted this multiplex signal, this output is coupled to second input of these phase detectors, and this output is exported this delay output signal, this control end is coupled to the output of this counter, the time of delay of the signal of the signal of the input of this this delay element of count value decision input and the output output of this delay element.
When wanting the time of delay of adjustment delay element, change the state of selecting signal, making multiplexer select reference signal is multiplex signal, then the phase place of the signal of the first input end of phase detectors and second input can reach unanimity.
Finish after the adjustment of time of delay, change the state of selecting signal, making multiplexer select input signal is multiplex signal, and is maintained fixed the time of delay of delay element.
According to a preferred embodiment of the present invention, is maintained fixed the time of delay of delay element, the count value that can allow counter export remains unchanged and gets final product.
According to a preferred embodiment of the present invention, the adjusting process of the time of delay of this deferred mount, when adjustment, to select the state of signal to change, make phase detectors, counter, reach delay element formation phase-locked loop, the phase place of signal of two inputs of phase detectors is reached unanimity, promptly finish the adjustment of time of delay.After finishing adjustment, change the state of selecting signal again, output again behind the delay institute preset time that this deferred mount can be correct with input signal.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Brief Description Of Drawings:
Fig. 1 cooperates clock to transmit the sequential chart of data;
Fig. 2 cooperates clock to transmit the circuit block diagram of data;
Fig. 3 A cooperates data strobe signal to transmit the circuit block diagram of data;
Fig. 3 B is the sequential chart of Fig. 3 A;
Fig. 4 A is the circuit block diagram that cooperates data strobe signal to transmit data and add delay element at receiving terminal;
Fig. 4 B is the signal timing diagram of Fig. 4 A;
Fig. 5 is the circuit block diagram of time of delay of 1/4th clock signal periods of generation of known technology;
Fig. 6 A is the block diagram of deferred mount of the use phase-locked loop adjustment of one embodiment of the invention;
Fig. 6 B is the signal timing diagram of the signal of Fig. 6 A;
Fig. 7 is the block diagram of deferred mount of the use phase-locked loop adjustment of another embodiment of the present invention.
Fig. 8 is the block diagram of deferred mount of the use phase-locked loop adjustment of yet another embodiment of the invention.
Preferred embodiment
Please refer to Fig. 6 A and Fig. 6 B, wherein Fig. 6 A illustrates a kind of block diagram that uses the deferred mount of phase-locked loop adjustment according to a preferred embodiment of the present invention, and Fig. 6 B then is the wave form varies figure of signal wherein.
Please refer to Fig. 6 A and illustrate, deferred mount 600 comprises multiplexer 610, phase detectors (Phase detector) 620, counter 630, delay element (Delay Element) 640 and inverter 650.The major function of deferred mount 600 is to accept data strobe (Data strobe) signal DS, after it is postponed one period regular time, again by the data strobe signal after the signal DOUT output delay, the time of delay that comprises multiplexer 610 and delay element 640 its time of delay altogether, but the parameter by delay element 640 is adjusted, and phase detectors 620, counter 630, and 640 of delay elements are to constitute the phase-locked loop of proofreading and correct (Phase Lock Loop), utilize signal CLKX2 to work as the reference signal of the delay parameter of the delay element 640 of making decision, data strobe signal DS produces according to clock signal clk (not illustrating among the figure), and reference signal CLKX2 is the frequency-doubled signal of clock signal clk.
As shown in the figure, data strobe signal DS and signal CLKX2 be the input A and the input B of input multiplexer 610 respectively, multiplexer 610 is also accepted the control of adjustment signal CAL, the state that changes signal CAL can select data strobe signal DS and signal CLKX2 the two one of by the output Y output of multiplexer 610.The multiplex signal that multiplexer 610 output Y send is delivered to the input I of delay element 640 again, delay element 640 with signal delay one preset time after, send by output 0, the time of its delay is decided by the parameter that control end C sends into.Delay element 640 can form with a plurality of buffer serial connections, and the number that changes the buffer of serial connection can make change the time of delay of signal.
The complementary reference signal CLKX2 of signal CLKX2 after trigger 650 is anti-phase delivers to the input I1 of phase detectors 620, the signal DOUT that is sent by the output 0 of delay element 640 then sends the input I2 of phase detectors 620 back to, the signal of the output UP/DN of phase detectors 620 is delivered to counter 630 again, the signal of the output UP/DN of phase detectors 620 can be along with being changed by the phase difference of the signal CLKX2 of input I1 and I2 input and DOUT, the count value of counter 630 is up increased progressively or down successively decreases.Counter 630 is the control of acceptable signal CAL also, makes it stop counting.
The count value of counter 630 outputs is used as delay parameter, delivers to the control end C of delay element 640, can be used to determine the time of delay of delay element 640.
Deferred mount 600 is before running, and is essential earlier through the step of adjustment, determines the time of delay of delay element 640.When carrying out adjustment, can change the state of signal CAL, make multiplexer 610 select signal CLKX2 is delivered to delay element 640, also make counter 630 be subjected to the control of phase detectors 620 to change its count value in addition.So, can make phase detectors 620, counter 630, reach loop circuit of delay element 640 formation, its effect can make the phase of input signals of two input I1 of phase detectors 620 and I2 close as far as possible or equal, even also the phase place of signal CLKX2 and signal DOUT is the same.
Please refer to the signal timing diagram that Fig. 6 B is illustrated, clock signal clk is the clock of System Operation, and data strobe signal DS produces according to clock signal clk, and is therefore synchronous with it.Signal CLKX2 then is the frequency-doubled signal of clock signal clk, promptly its cycle have only clock signal clk cycle 1/2, the cycle that makes clock signal clk is Tc, then the cycle of signal CLKX2 is Tc/2.In addition, signal CLKX2 then is the complementary signal of signal CLKX2.
In the block diagram of deferred mount 600, suitable selection delay element 640, when making its period that is in adjustment, last stable state can make signal CLKX2 consistent with the phase place of signal DOUT.Wherein, signal DOUT is the signal after the delayed element 640 of signal CLKX2 postpones, that is, make signal CLKX2 postpone the time of Tc/4, just can make its phase place consistent with signal CLKX2, just just in time be Tc/4 the time of delay of delay element 640, and promptly four/one-period of clock signal clk has so promptly been finished the adjustment of the time of delay of delay element 640.
Finished after the adjustment of delay parameter, change the state of signal CAL, make multiplexer 610 select data strobe signal DS is delivered to delay element 640 through its output Y, counter 630 is failed, keep last count value, deferred mount 600 is exported by signal DOUT after getting final product accurate four/one-period with data strobe signal DS delay clock signals CLK again.Certainly known this skill person should understand, when deferred mount 600 is in normal operation, signal CAL is may command phase detectors 620 or delay element 640 also, phase detectors 620 are not acted on or delay element 640 to fix its delay parameter constant, in a word, make phase detectors 620, counter 630, and delay element 640 no longer form a loop circuit, time of delay of delay element 640 is no longer changed gets final product.So data strobe signal DS gets final product the signal in 1/4 cycle of output delay clock signal clk through behind the deferred mount 600.
When deferred mount 600 is applied in the personal computer system, can when system start-up, carry out the adjustment of delay parameter, in addition, if be to use when the control of DDR SDRAM, then also can when SDRAM does the cycle of renewal (refresh), carry out the adjustment of delay parameter.
Fig. 7 and Fig. 8 are the block diagrams of deferred mount of the use phase-locked loop adjustment of two other embodiment of the present invention.As be familiar with this skill person and can know by inference easily, the position difference that this two embodiment is a trigger, function that it is reached and operation principles all are same as an embodiment.Only be noted that among Fig. 8, because trigger 850 is between multiplexer 610 and delay element 640, so the signal of input multiplexer 610 is the complementary signal of data strobe signal DS, the data strobe signal that can correctly be postponed at the output of delay element 640.
From above discussion, the deferred mount of use phase-locked loop of the present invention as can be known adjustment has following advantage at least:
1. need not to use extension lead to make signal delay, control lag time accurately, and can reduce the area of required printed substrate, also can be applicable to various operation frequency.
2. not as control lag time accurately of the designed delay element of passive device and influenced by various external factors and change the shortcoming of its length of delay.
3. only need additive phase detector and counter adjustment to go out required delay parameter, the circuit of its formation is simpler, can reduce shared chip area.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when the change that can do a little and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (9)
1. a deferred mount that uses the phase-locked loop adjustment is accepted an input signal and is exported a delay output signal, and this delay output signal is the signal that this input signal postpones a scheduled time, it is characterized in that this deferred mount comprises:
One phase detectors have a first input end, one second input, reach an output, and this first input end receives the complementary signal of a reference signal;
One counter has an input and an output, and this input is coupled to the output of these phase detectors, in order to change the count value of this output output: and
One delay element, have an input, an output, reach a control end, this input is accepted this input signal and this reference signal either-or, this output is coupled to this second input of these phase detectors, and this output is exported this delay output signal, this control end is coupled to the output of this counter, the time of delay of the signal that the signal of the input of this this delay element of count value decision input and the output of this delay element are exported; More comprise:
One multiplexer, have a first input end, one second input, one output and a control end, its output is coupled to this input of this delay element, its first input end is coupled to this input signal, and its second input is coupled to this reference signal, and its control end is coupled to one and selects signal, in order to the state according to this selection signal, the signal of selecting its output is this input signal and this reference signal either-or;
One inverter, its input is coupled to this reference signal, and exports the complementary signal of this reference signal.
Such as claim 1 the deferred mount of use phase-locked loop adjustment of mark, it is characterized in that this count value is maintained fixed when the state that changes this selections signal is the output of this multiplexer to select this input signal.
3. a deferred mount that uses the phase-locked loop adjustment is accepted an input signal and is exported a delay output signal, and this delay output signal is the signal that this input signal postpones a scheduled time, it is characterized in that this deferred mount comprises:
One phase detectors have a first input end, one second input, an and output, and this first input end receives a reference signal;
One counter has an input and an output, and this input is coupled to the output of these phase detectors, in order to change the count value of this output output; And
One delay element, have an input, an output, reach a control end, this input is accepted this input signal and this reference signal either-or, this output is exported this delay output signal, and the complementary signal of this delay output signal is coupled to second input of these phase detectors, this control end is coupled to the output of this counter, the time of delay of the signal that the signal of the input of this this delay element of count value decision input and the output of this delay element are exported; More comprise:
One multiplexer, have a first input end, one second input, one output and a control end, its output is coupled to this input of this delay element, its first input end is coupled to this input signal, and its second input is coupled to this reference signal, and its control end is coupled to one and selects signal, in order to the state according to this selection signal, the signal of selecting its output is this input signal and this reference signal either-or;
One inverter, its input is coupled to this delay output signal, and exports the complementary signal of this delay output signal.
4. the deferred mount of use phase-locked ring road adjustment as claimed in claim 3 is characterized in that this count value is maintained fixed when the state that changes this selection signal is the output of this multiplexer to select this input signal.
5. a deferred mount that uses the phase-locked loop adjustment is accepted the complementary signal of an input signal and is exported a delay output signal, and this delay output signal is the signal that this input signal postpones a scheduled time, it is characterized in that this deferred mount comprises:
One phase detectors have a first input end, one second input, reach an output, and this first input end receives a reference signal;
One counter has an input and an output, and this input is coupled to the output of these phase detectors, in order to change the count value of this output output; And
One delay element, have an input, an output, reach a control end, this input is accepted complementary signal and this input signal either-or of this reference signal, this output is exported this delay output signal, and this delay output signal is coupled to this second input of these phase detectors, this control end is coupled to the output of this counter, the time of delay of the signal that the signal of the input of this this delay element of count value decision input and the output of this delay element are exported; More comprise:
One multiplexer, have a first input end, one second input, one output and a control end, its first input end is coupled to the complementary signal of this input signal, its second input is coupled to this reference signal, its control end is coupled to one and selects signal, in order to according to this state of selecting signal, selects complementary signal and this reference signal either-or of the signal of its output for this input signal;
One inverter, its input is coupled to the output of this multiplexer, and its output is coupled to this delay element.
6. the deferred mount of use phase-locked loop as claimed in claim 5 adjustment is characterized in that this count value is maintained fixed when the state that changes this selection signal is the output of this multiplexer with the complementary signal of selecting this input signal.
7. deferred mount that uses the phase-locked loop adjustment, accept an input signal and export a delay output signal, this delay output signal is the signal that this input signal postpones a scheduled time, and this input signal is with reference to a clock signal, it is characterized in that this deferred mount comprises:
One multiplexer, accept this input signal and a reference signal, export a multiplex signal, and accept a control of selecting signal, this selections signal comprises one first state and one second state, when this selection signal is this first state, it is this multiplex signal that this multiplexer is selected this input signal, when this selected signal to be this second state, this multiplexer selected this reference signal to be this multiplex signal, and wherein this reference signal is the frequency-doubled signal of this clock signal;
One inverter is accepted this reference signal, exports a complementary reference signal;
One phase detectors have a first input end, one second input, reach an output, and this first input end receives this complementation reference signal;
One counter has an input and an output, and this input is coupled to the output of these phase detectors, in order to change a count value of this output output; And
One delay element, have an input, an output, reach a control end, this input is accepted this multiplex signal, this output is coupled to second input of these phase detectors, and this output is exported this delay output signal, this control end is coupled to the output of this counter, the time of delay of the signal of the signal of the input of this this delay element of count value decision input and the output output of this delay element:
When this selected signal to be this second state, the phase place of this first input end of these phase detectors and the signal of this second input reached unanimity, and when this selected signal to be this first state, be maintained fixed the time of delay of this delay element.
8. the deferred mount of use phase-locked loop as claimed in claim 7 adjustment is characterized in that this scheduled time is four/one-period of this clock signal.
9. a method of using phase-locked loop adjustment delay parameter in order to determine a delay parameter of a delay element, is characterized in that this method comprises the following steps:
Provide phase detectors and a counter, two inputs of this phase-detection utensil and an output;
One reference signal and a complementary reference signal are provided;
This reference signal is imported these two inputs of these phase detectors respectively with this complementation reference signal behind this delay element;
The output of these phase detectors changes the count value of this counter;
The count value of this counter changes the time of delay of this delay element; And
When the phase of input signals of two inputs of these phase detectors was consistent, the count value of this counter i.e. this delay parameter.
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| CN100412749C (en) * | 2004-10-21 | 2008-08-20 | 威盛电子股份有限公司 | Memory signal timing regulation method and related device |
| CN100376081C (en) * | 2005-09-15 | 2008-03-19 | 威盛电子股份有限公司 | Delayed locking loop capable of sharing counter and related method |
| KR100714874B1 (en) * | 2005-09-27 | 2007-05-07 | 삼성전자주식회사 | Delay line circuit having adjustable delay step and delay cell for the same |
| US20080013664A1 (en) * | 2006-07-11 | 2008-01-17 | Mediatek Inc. | Phase error measurement circuit and method thereof |
| US8384456B1 (en) * | 2011-11-18 | 2013-02-26 | Texas Instruments Incorporated | Integrated phase-locked and multiplying delay-locked loop with spur cancellation |
| ES2875016T3 (en) * | 2015-01-30 | 2021-11-08 | Ingeteam Power Tech Sa | Synchronization system for an electrical generating unit and associated method |
-
2000
- 2000-02-12 CN CN 00101898 patent/CN1120572C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1309468A (en) | 2001-08-22 |
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Granted publication date: 20030903 |