CN112054783A - Trigger and trigger with scanning end - Google Patents
Trigger and trigger with scanning end Download PDFInfo
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- CN112054783A CN112054783A CN201910492126.8A CN201910492126A CN112054783A CN 112054783 A CN112054783 A CN 112054783A CN 201910492126 A CN201910492126 A CN 201910492126A CN 112054783 A CN112054783 A CN 112054783A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/021—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of more than one type of element or means, e.g. BIMOS, composite devices such as IGBT
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Abstract
The invention discloses a trigger circuit, comprising: the first signal processing part is used for generating and outputting a first signal according to the received working signal and comprises a first input end and a first output end; a first clock control section for outputting the received signal under control of a first clock signal; the first clock control part comprises a first clock input end, a first clock signal control end and a first clock output end; a second clock control section for outputting the received signal under control of a second clock signal; the second clock control part comprises a second clock input end, a second clock signal control end and a second clock output end; a second signal processing section for generating and outputting a second signal from the received signal; the second signal processing section includes a second input terminal and a second output terminal. The trigger circuit can operate under the low-voltage working condition, occupies small area, consumes less power and can meet the speed and performance requirements of the application of the Internet of things.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a trigger and a trigger with a scanning end.
Background
At present, the internet of things (IoT) technology is continuously developed vigorously, and the requirements on the system are higher and higher. In the technology of the internet of things, the design of an application chip of the internet of things is an important design index for meeting the performance requirement and the power consumption and the cost. The design of flip-flop circuits is particularly important in chip design. Flip-flop circuits are used in large numbers in chip design. Typically, the total area of the flip-flops in a chip occupies 50% or more of the total area of the chip. Therefore, how to design the trigger with ultra-low power consumption and ultra-small area is extremely important for the development of the current and future application chips of the internet of things.
Existing Flip-flops include Transmission-Gate Flip-Flop (TGFF) and adaptive-coupled Flip-Flop (ACFF).
Referring to fig. 1, in a circuit design of a conventional transmission gate flip-flop, a local clock buffer needs to be designed. However, the local clock buffer is designed with a large-sized transistor to provide sufficient driving capability, but occupies a large area and consumes a large amount of power.
Referring to fig. 2, a further improvement is made in the circuit design of the conventional adaptive-coupled flip-flop (ACFF). A single-phase clock structure is adopted in the circuit design, and a local time buffer is not needed in the single-phase clock structure. Therefore, the adaptive coupled flip-flop can save 77% of power consumption compared to the transmission gate flip-flop. However, although the energy consumption of the adaptive coupled flip-flop is reduced, the number of transistors is reduced by only 2 compared with that of the transmission gate flip-flop, and high power consumption and large area occupation are still consumed.
Therefore, how to design a trigger with ultra-low power consumption and ultra-small area is extremely important for the development of the application chip of the internet of things.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a method.
In order to achieve the purpose of the invention, the invention adopts the following technical scheme:
according to an aspect of the present invention, there is provided a flip-flop circuit, comprising:
the first signal processing part is used for generating and outputting a first signal according to the received working signal, and comprises a first input end used for receiving the working signal and a first output end used for outputting the first signal;
a first clock control part for outputting the received signal under control of a first clock signal, the first clock control part including a first clock input terminal for receiving a signal, a first clock signal control terminal for receiving a clock signal, and a first clock output terminal for outputting the received signal under control of the first clock signal; the first clock input end is connected with the first output end;
a second clock control section for outputting the received signal under control of a second clock signal, the second clock control section including a second clock input terminal for receiving the signal, a second clock signal control terminal for receiving the clock signal, and a second clock output terminal for outputting the received signal under control of the second clock signal; the second clock input end is connected with the first clock output end;
a second signal processing section for generating and outputting a second signal from the received signal, the second signal processing section including a second input terminal for receiving the signal and a second output terminal for outputting the second signal; the second input end is connected with the second clock output end;
the clock signal comprises a first clock signal and a second clock signal, and the logic level of the first clock signal is opposite to that of the second clock signal.
Further, the second clock input terminal is connected to the first clock output terminal through a third signal processing section;
the second input end is connected with the second clock output end through a fourth signal processing part;
the third signal processing part is used for generating and outputting a third signal according to the received signal, and comprises a third input end used for receiving the signal and a third output end used for outputting the third signal; the third input end is connected with the first clock output end, and the third output end is connected with the second clock input end
The fourth signal processing part is used for generating and outputting a fourth signal according to the received signal, and comprises a fourth input end used for receiving the signal and a fourth output end used for outputting the fourth signal; the fourth input end is connected with the second clock output end, and the fourth output end is connected with the second input end.
Furthermore, the first clock signal is at a low level, and the second clock signal is at a high level;
when the clock signal is a first clock signal, the first signal processing part generates and outputs a first signal according to the input working signal, and the first clock control part outputs the received first signal under the control of the first clock signal; a third signal processing unit for generating and outputting a third signal from the input first signal;
when the clock signal is a second clock signal, the second clock control part outputs the received third signal under the control of the second clock signal; the fourth signal processing part generates and outputs a fourth signal according to the received third signal; the second signal processing unit generates and outputs a second signal from the input fourth signal.
Further, the first signal processing part comprises a first PMOS tube and a first NMON tube, wherein the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and serves as a first input end, and the source electrode of the first PMOS tube is connected with a power supply; the source electrode of the first NMOS tube is grounded; the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and serves as a first output end;
the second signal processing part comprises a second PMOS tube and a second NMON tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube and serves as a fourth input end, and the source electrode of the second PMOS tube is connected with a power supply; the source electrode of the second NMOS tube is grounded; and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and serves as a second output end.
Further, the third signal processing part comprises a third PMOS transistor and a third NMOS transistor, a gate of the third PMOS transistor is connected with a gate of the third NMOS transistor and serves as a third input end, and a source of the third PMOS transistor is connected with a power supply; the source electrode of the third NMOS tube is grounded; the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube and serves as a third output end;
the fourth signal processing part comprises a fourth PMOS tube and a fourth NMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube and serves as a fourth input end, and the source electrode of the fourth PMOS tube is connected with the power supply; the source electrode of the fourth NMOS tube is grounded; and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and serves as a fourth output end.
Furthermore, the first clock control part comprises a fifth PMOS transistor and a sixth PMOS transistor, and the gate of the fifth PMOS transistor is connected with the gate of the sixth PMOS transistor and serves as a first clock signal control end; the source electrode of the fifth PMOS tube is connected with the first output end, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, and the drain electrode of the sixth PMOS tube is used as the first clock output end;
the second clock control part comprises a fifth NMOS tube and a sixth NMOS tube, and the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube and is used as a second clock signal control end; the source electrode of the fifth NMOS tube is connected with the first clock output end, the drain electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube, and the drain electrode of the sixth NMOS tube is used as the second clock output end.
Further, the flip-flop circuit further includes a scan data section and a mode selection section;
the scanning data part is used for generating and outputting a fifth signal according to the received scanning signal, and comprises a scanning input end used for receiving the scanning signal and a scanning output end used for outputting the fifth signal; the scanning output end is connected with the first clock input end;
the mode selection part is used for generating and outputting a mode control signal according to a received mode selection signal, and comprises a mode selection input end used for receiving the mode selection signal and a mode control output end used for outputting the mode control signal;
the mode selection part further comprises a first switch and a second switch, and the first switch is connected with the first signal processing part; the second switch is connected with the scanning data part;
when the mode selection signal received by the mode selection part is a scanning mode signal, the first switch is opened so as to disconnect the passage of the first signal processing part and the first clock input end, and the second switch is closed so as to connect the passage of the scanning data part and the first clock input end;
when the mode selection signal received by the mode selection part is an operation signal, the first switch is closed so as to connect the first signal processing part with the path of the first clock input end, and the second switch is opened so as to disconnect the path of the scanning data part with the path of the first clock input end.
Further, the first signal processing part further comprises a first power terminal and a first ground terminal; the first power end is used for connecting a power supply, and the first grounding end is used for grounding;
the data scanning part also comprises a second power supply end and a second grounding end; the second power end is used for connecting a power supply, and the second grounding end is used for grounding;
the scanning data part comprises a seventh PMOS tube and a seventh NMOS tube, the grid electrode of the seventh PMOS tube is connected with the grid electrode of the seventh NMOS tube and serves as a scanning input end, the source electrode of the seventh PMOS tube serves as a second power supply end, and the source electrode of the seventh NMOS tube serves as a second grounding end.
Further, the first switch comprises an eighth PMOS transistor and an eighth NMOS transistor, a gate of the eighth PMOS transistor is configured to receive a mode selection signal, a source of the eighth PMOS transistor is configured to be connected to a power supply, and a drain of the eighth PMOS transistor is connected to the first power supply terminal; the grid electrode of the eighth NMOS tube is used for receiving a mode control signal, the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is connected with the first grounding end;
the second switch comprises a ninth PMOS tube and a ninth NMOS tube, the grid electrode of the ninth PMOS tube is used for receiving a mode control signal, the source electrode of the ninth PMOS tube is connected with the first output end, and the drain electrode of the ninth PMOS tube is connected with the first clock input end; the grid electrode of the ninth NMOS tube is used for receiving a mode selection signal, the source electrode of the ninth NMOS tube is connected with the first output end, and the drain electrode of the ninth NMOS tube is connected with the first clock input end.
Further, the mode selection part comprises a tenth PMOS transistor and a tenth NMOS transistor, a gate of the tenth PMOS transistor is connected with a gate of the tenth NMOS transistor and serves as the scan input terminal, and a source of the tenth PMOS transistor is connected with a power supply; the source electrode of the tenth NMOS tube is grounded; and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the tenth NMOS tube and serves as the scanning output end.
The invention has the beneficial effects that: the trigger circuit can operate under the low-voltage working condition, occupies small area, consumes less power and can meet the speed and performance requirements of the application of the Internet of things.
Drawings
The above and other aspects, features and advantages of embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a prior art transmission gate flip-flop;
FIG. 2 is a circuit diagram of a prior art adaptively coupled flip-flop;
FIG. 3 is a circuit diagram of a flip-flop circuit of an embodiment of the present invention;
FIG. 4 illustrates the delay between the input and output of the flip-flop circuit of the embodiment of the present invention at different operating voltages;
fig. 5 is a circuit diagram of a flip-flop circuit of a further embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the invention and its practical application to thereby enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. In the drawings, the shapes and sizes of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or similar elements.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
Example one
Fig. 3 is a circuit diagram of a flip-flop circuit of an embodiment of the present invention.
Referring to fig. 3, a first embodiment of the present invention discloses a flip-flop circuit including: a first signal processing section 10, a first clock control section 20, a second clock control section 30, and a second signal processing section 20.
Specifically, the first signal processing section 10 is configured to generate and output a first signal according to the received operation signal. The first signal processing section 10 includes a first input terminal for receiving the operation signal, and a first output terminal for outputting the first signal.
Specifically, the first clock control section 20 is configured to output the received signal under control of the first clock signal. The first clock control section 20 includes a first clock input terminal for receiving a signal, a first clock signal control terminal for receiving a clock signal, and a first clock output terminal for outputting the received signal under control of the first clock signal. The first clock input end is connected with the first output end.
Specifically, the second clock control section 30 is configured to output the received signal under the control of the second clock signal. The second clock control section 30 includes a second clock input terminal for receiving a signal, a second clock signal control terminal for receiving a clock signal, and a second clock output terminal for outputting the received signal under the control of the second clock signal. The second clock input end is connected with the first clock output end.
Specifically, the second signal processing unit 40 generates and outputs a second signal based on the received signal. The second signal processing section 40 includes a second input terminal for receiving the signal, and a second output terminal for outputting the second signal. The second input terminal is connected with the second clock output terminal.
The clock signals comprise a first clock signal and a second clock signal, and the logic level of the first clock signal is opposite to that of the second clock signal.
The working signal is processed by the first signal processing section 10, passes through the first clock control section 20 under the control of the first clock signal, passes through the second clock control section 30 under the control of the second clock signal, and is finally processed by the second signal processing section to form an output signal. The flip-flop circuit of the embodiment of the present invention can normally operate at an operating voltage of 1.2V and at a clock frequency lower than 70 kHz.
In order that the flip-flop can normally operate at a clock frequency of 5kHz, the flip-flop circuit of the embodiment of the present invention further includes a third signal processing section 50 and a fourth signal processing section 60.
Specifically, the third signal processing section 50 is connected between the second clock input terminal and the first clock output terminal. The third signal processing section (50) is configured to generate and output a third signal from the received signal, and the third signal processing section (50) includes a third input terminal configured to receive the signal and a third output terminal configured to output the third signal. The third input end is connected with the first clock output end. The third output terminal is connected with the second clock input terminal.
Specifically, the fourth signal processing section 60 is connected between the second input terminal and the second clock output terminal. The fourth signal processing section 60 is configured to generate and output a fourth signal from the received signal. The fourth signal processing section 60 includes a fourth input terminal for receiving the signal, and a fourth output terminal for outputting the fourth signal. The fourth input end is connected with the second clock output end. The fourth output end is connected with the second input end.
In one embodiment of the present invention, the first clock signal is at a low level and the second clock signal is at a high level.
When the clock signal is the first clock signal, the first signal processing section 10 generates and outputs the first signal based on the input operation signal. The first clock control section 20 outputs the received first signal under the control of the first clock signal. The third signal processing section 50 generates and outputs a third signal from the input first signal.
When the clock signal is the second clock signal, the second clock control section 30 outputs the received third signal under the control of the second clock signal. The fourth signal processing section 60 generates and outputs a fourth signal from the received third signal. The second signal processing section 40 generates and outputs a second signal from the input fourth signal.
As an embodiment of the present invention, the first signal processing section 10 includes a first PMOS transistor 11 and a first NMON transistor 12. The grid of the first PMOS transistor 11 is connected to the grid of the first NMOS transistor 12 and serves as a first input terminal. The source of the first PMOS transistor 11 is connected to a power supply. The source of the first NMOS transistor 12 is grounded. The drain of the first PMOS transistor 11 is connected to the drain of the first NMOS transistor 12 and serves as a first output terminal.
As an embodiment of the present invention, the second signal processing unit 40 includes a second PMOS transistor 41 and a second NMON transistor 42. The gate of the second PMOS transistor 41 is connected to the gate of the second NMOS transistor 42 and serves as a fourth input terminal. The source of the second PMOS transistor 41 is connected to a power supply. The source of the second NMOS transistor 42 is grounded. The drain of the second PMOS transistor 41 is connected to the drain of the second NMOS transistor 42 and serves as a second output terminal.
In one embodiment of the present invention, the third signal processing unit 50 includes a third PMOS transistor 51 and a third NMOS transistor 52. The gate of the third PMOS transistor 51 is connected to the gate of the third NMOS transistor 52 and serves as a third input terminal. And the source electrode 51 of the third PMOS tube is connected with a power supply. The source of the third NMOS transistor 52 is grounded. The drain of the third PMOS transistor 51 is connected to the drain of the third NMOS transistor 52 and serves as a third output terminal.
In one embodiment of the present invention, the fourth signal processing unit 60 includes a fourth PMOS transistor 61 and a fourth NMOS transistor 62. The gate of the fourth PMOS transistor 61 is connected to the gate of the fourth NMOS transistor 62 and serves as a fourth input terminal. The source of the fourth PMOS transistor 61 is connected to the power supply. The source of the fourth NMOS transistor 62 is grounded. The drain of the fourth PMOS transistor 61 is connected to the drain of the fourth NMOS transistor 62 and serves as a fourth output terminal.
As an embodiment of the present invention, the first clock control unit 20 includes a fifth PMOS transistor 21 and a sixth PMOS transistor 22. The gate of the fifth PMOS transistor 21 is connected to the gate of the sixth PMOS transistor 22, and serves as a first clock signal control terminal. The source of the fifth PMOS transistor 21 is connected to the first output terminal. The drain of the fifth PMOS transistor 21 is connected to the source of the sixth PMOS transistor 22. The drain of the sixth PMOS transistor 22 serves as the first clock output terminal.
As an embodiment of the present invention, the second clock control unit 30 includes a fifth NMOS transistor 31 and a sixth NMOS transistor 32. The gate of the fifth NMOS transistor 31 is connected to the gate of the sixth NMOS transistor 32, and serves as a second clock signal control terminal. The source of the fifth NMOS transistor 31 is connected to the first clock output terminal. The drain of the fifth NMOS transistor 31 is connected to the source of the sixth NMOS transistor 32. The drain of the sixth NMOS transistor 32 serves as the second clock output terminal.
The operation of the flip-flop circuit of the embodiment of the present invention will be specifically described below.
1. When the input signal D is low:
A. when the clock signal is the first clock signal (in the present embodiment, the first clock signal is at a low level, the second clock signal is at a high level, and in other embodiments, the high level is represented by 1, and the low level is represented by 0):
when the input signal D is at a low level, the first input terminal of the first signal processing unit 10 inputs the low level, and the first PMOS transistor 11 of the first signal processing unit 10 is turned on, so that the first output terminal is connected to the power supply to output the high level.
Since the clock signal is at a low level, the fifth PMOS transistor 21 and the sixth PMOS transistor 22 of the first clock control unit 20 are turned on. The first clock input terminal of the first clock control section 20 inputs a high level, and the first clock output terminal outputs a high level.
Since the third input terminal of the third signal processing unit 50 receives a high level, the fourth NMOS transistor 52 is turned on, and the third output terminal is connected to ground and outputs a low level.
Since the clock signal is at a low level, both the fifth NMOS transistor 31 and the sixth NMOS transistor 32 do not operate in the second clock control unit 30.
B. When the clock signal is the second clock signal:
the fifth NMOS transistor 31 and the sixth NMOS transistor 32 of the second clock control unit 30 are turned on, and the second clock input terminal of the second clock control unit 30 inputs a low level and the second clock output terminal outputs a low level.
When the fourth input terminal of the fourth signal processing unit 60 is at a low level, the fourth PMOS transistor 61 is turned on. The fourth output terminal of the fourth signal processing section 60 is connected to the power supply and outputs a high level.
When the second input terminal of the second signal processing unit 40 is at a high level, the second NMOS transistor 42 is turned on, and the second output terminal of the second signal processing unit 40 is connected to ground, and the output signal Q is at a low level.
2. When the input signal D is high:
A. when the clock signal is the first clock signal:
when the input signal D is at a high level, the first input terminal of the first signal processing unit 10 inputs the high level, and the first NMOS transistor 12 of the first signal processing unit 10 is turned on, so that the first output terminal is connected to ground and outputs the low level.
Since the clock signal is at a low level, the fifth PMOS transistor 21 and the sixth PMOS transistor 22 of the first clock control unit 20 are turned on. The first clock input terminal of the first clock control section 20 inputs a low level, and the first clock output terminal outputs a low level.
The third input end of the third signal processing unit 50 inputs a low level, the fourth PMOS transistor 51 is turned on, and the third output end is connected to the power supply to output a high level.
Since the clock signal is at a low level, both the fifth NMOS transistor 31 and the sixth NMOS transistor 32 do not operate in the second clock control unit 30.
B. When the clock signal is the second clock signal:
the fifth NMOS transistor 31 and the sixth NMOS transistor 32 of the second clock control unit 30 are turned on, and the second clock input terminal of the second clock control unit 30 inputs a high level and the second clock output terminal outputs a high level.
When the fourth input terminal of the fourth signal processing unit 60 is at a high level, the fourth NMOS transistor 62 is turned on. The fourth output terminal of the fourth signal processing section 60 is connected to ground and outputs a low level.
When the second input terminal of the second signal processing unit 40 is at a low level, the second PMOS transistor 41 is turned on, and the second output terminal of the second signal processing unit 40 is connected to the power supply to output the signal Q at a high level.
Compared with the prior art transmission gate flip-flop, the flip-flop circuit of the embodiment of the invention does not need to design a local clock buffer circuit, so that the additional circuit area and the power consumption can be reduced, and the input-output (C-Q) delay of the flip-flop circuit is increased, and as can be known from fig. 4, when the operating voltage of the flip-flop circuit of the embodiment of the invention is 0.6V-1.2V, the input-output delay is different from 11.2ns to 139 ps. Compared with the traditional transmission gate trigger, the trigger circuit of the embodiment of the invention has smaller area and less power consumption, and can meet the speed and performance requirements of the application of the Internet of things.
Example two
Fig. 5 is a circuit diagram of a flip-flop circuit of a further embodiment of the present invention.
Referring to fig. 5, a second embodiment of the present invention provides a flip-flop circuit of another implementation. Unlike the implementation, the flip-flop circuit of the embodiment of the present invention further includes a scan data section 70 and a mode selection section 80.
Specifically, the scan data section 70 is configured to generate and output a fifth signal according to the received scan signal. The scan data part 70 includes a scan input terminal for receiving the scan signal, and a scan output terminal for outputting the fifth signal. The scanning output end is connected with the first clock input end.
Specifically, the mode selection unit 80 is configured to generate and output a mode control signal according to the received mode selection signal. The mode selection part 80 includes a mode selection input terminal for receiving a mode selection signal, and a mode control output terminal for outputting a mode control signal.
Specifically, the mode selection part 80 further includes a first switch and a second switch. The first switch is connected to the first signal processing unit 10. The second switch is connected to the scan data section 70.
When the mode selection signal received by the mode selection part 80 is a scan mode signal, the first switch is turned off to disconnect the path between the first signal processing part 10 and the first clock input terminal. The second switch is closed to communicate the path of the scan data section 70 with the first clock input.
When the mode selection signal received by the mode selection part 80 is an operation signal, the first switch is closed to connect the first signal processing part 10 with the path of the first clock input terminal. The second switch is turned off to disconnect the scan data part 70 from the first clock input terminal.
Under the control of the mode selection part 80, the scan data part 70 or the first signal processing part 10 may be selected to operate, thereby satisfying the requirements of scan detection and actual operation.
As an embodiment of the present invention, the first signal processing part 10 further includes a first power terminal and a first ground terminal. The first power terminal is used for connecting a power supply, and the first grounding terminal is used for grounding.
The scan data part further includes a second power terminal and a second ground terminal. The second power terminal is used for connecting a power supply, and the second grounding terminal is used for grounding.
The scan data part 70 includes a seventh PMOS transistor 71 and a seventh NMOS transistor 72, and a gate of the seventh PMOS transistor 71 is connected to a gate of the seventh NMOS transistor 72 and serves as a scan input terminal. The source of the seventh PMOS transistor 71 serves as a second power terminal 72, and the source of the seventh NMOS transistor 72 serves as a second ground terminal.
As an embodiment of the present invention, the first switch includes an eighth PMOS transistor 81 and an eighth NMOS transistor 82. The gate of the eighth PMOS transistor 81 is used for receiving the mode selection signal. The source of the eighth PMOS transistor 81 is used for connecting a power supply. The drain of the eighth PMOS transistor 81 is connected to the first power terminal. The gate of the eighth NMOS transistor 82 is used to receive the mode control signal. The source of the eighth NMOS 82 is grounded, and the drain of the eighth NMOS 82 is connected to the first ground.
As an embodiment of the present invention, the second switch includes a ninth PMOS transistor 83 and a ninth NMOS transistor 84. The gate of the ninth PMOS transistor 83 is used for receiving the mode control signal. The source of the ninth PMOS transistor 83 is connected to the first output terminal. The drain of the ninth PMOS transistor 84 is connected to the first clock input terminal. The gate of the ninth NMOS transistor 83 is used to receive the mode selection signal. The source of the ninth NMOS 83 is connected to. The first output terminal is connected, and the drain of the ninth NMOS transistor 83 is connected to the first clock input terminal 21.
As an embodiment of the present invention, the mode selection part 80 includes a tenth PMOS transistor 85 and a tenth NMOS transistor 86. The gate of the tenth PMOS transistor 85 is connected to the gate of the tenth NMOS transistor 86 and serves as a scan input terminal. The source of the tenth PMOS transistor 85 is connected to the power supply. The source of the tenth NMOS transistor 85 is grounded. The drain of the tenth PMOS transistor 85 is connected to the drain of the tenth NMOS transistor 86 and serves as the scan output terminal.
The operation of the flip-flop circuit of the embodiment of the present invention will be specifically described below.
In this embodiment, when the mode selection signal SE is low, the flip-flop circuit is in the operating mode. When the mode selection signal is high, the flip-flop circuit is in the scan mode.
When the mode selection signal SE is at a low level, the tenth PMOS transistor 85 is turned on, and the mode control signal SEB is at a low level, and at this time, the operation mode is set, that is, the operation signal D is asserted, and the scan data unit 70 does not operate.
Specifically, since the mode selection signal SE is at a low level, the eighth PMOS transistor 81 is turned on, and the path between the first PMOS transistor 11 and the power supply is connected. Since the mode control signal SEB is at a high level, the eighth NMOS transistor 82 is turned on, and the path between the first NMOS transistor 12 and the ground is connected.
Meanwhile, since the mode selection signal SE is at a low level, the ninth NMOS transistor 72 is turned off, and the path between the seventh PMOS transistor 84 and the first clock input terminal is disconnected. Since the mode control signal SEB is at a high level, the ninth PMOS transistor 83 is turned off, and a path between the seventh NMOS transistor 72 and the first clock input terminal is cut off, so that the scan data part 70 does not operate.
When the mode selection signal SE is at a high level, the tenth NMOS transistor 86 is turned on, the mode control signal SEB is at a low level, and the scan mode is set, that is, the scan signal SD is asserted, and the first signal processing unit 10 does not operate.
Specifically, since the mode selection signal SE is at a high level, the eighth PMOS transistor 81 is turned off, and the path between the first PMOS transistor 11 and the power supply is cut off. Since the mode control signal SEB is at a low level, the eighth NMOS transistor 82 is turned off, and the path between the first NMOS transistor 12 and the ground is disconnected, so that the first signal processing unit 10 does not operate.
Meanwhile, since the mode selection signal SE is at a high level, the ninth NMOS transistor 72 is turned on, and the path between the seventh PMOS transistor 84 and the first clock input terminal is connected. Since the mode control signal SEB is at a low level, the ninth PMOS transistor 83 is turned on, and the path between the seventh NMOS transistor 72 and the first clock input terminal is communicated.
The flip-flop circuit of embodiments of the present invention provides a scan port so that the flip-flop circuit can meet the requirements of scan detection.
While the invention has been shown and described with reference to certain embodiments, those skilled in the art will understand that: various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (10)
1. A flip-flop circuit, comprising:
a first signal processing section (10) for generating and outputting a first signal from the received operation signal, the first signal processing section (10) including a first input terminal for receiving the operation signal, and a first output terminal for outputting the first signal;
a first clock control section (20) for outputting the received signal under control of a first clock signal, the first clock control section (20) comprising a first clock input terminal for receiving the signal, a first clock signal control terminal for receiving the clock signal, and a first clock output terminal for outputting the received signal under control of the first clock signal; the first clock input end is connected with the first output end;
a second clock control section (30) for outputting the received signal under control of a second clock signal, the second clock control section (30) comprising a second clock input terminal for receiving the signal, a second clock signal control terminal for receiving the clock signal, and a second clock output terminal for outputting the received signal under control of the second clock signal; the second clock input end is connected with the first clock output end;
a second signal processing section (40) for generating and outputting a second signal from the received signal, the second signal processing section (40) including a second input terminal for receiving the signal, and a second output terminal for outputting the second signal; the second input end is connected with the second clock output end;
the clock signal comprises a first clock signal and a second clock signal, and the logic level of the first clock signal is opposite to that of the second clock signal.
2. The flip-flop circuit according to claim 1, wherein the second clock input terminal is connected to the first clock output terminal through a third signal processing section (50);
the second input end is connected with the second clock output end through a fourth signal processing part (60);
the third signal processing part (50) is used for generating and outputting a third signal according to the received signal, and the third signal processing part (50) comprises a third input end used for receiving the signal and a third output end used for outputting the third signal; the third input end is connected with the first clock output end, and the third output end is connected with the second clock input end;
the fourth signal processing part (60) is used for generating and outputting a fourth signal according to the received signal, and the fourth signal processing part (60) comprises a fourth input end used for receiving the signal and a fourth output end used for outputting the fourth signal; the fourth input end is connected with the second clock output end, and the fourth output end is connected with the second input end.
3. The flip-flop circuit of claim 2, wherein the first clock signal is low and the second clock signal is high;
when the clock signal is a first clock signal, the first signal processing part (10) generates and outputs a first signal according to the input working signal, and the first clock control part (20) outputs the received first signal under the control of the first clock signal; a third signal processing unit (50) that generates and outputs a third signal from the input first signal;
when the clock signal is a second clock signal, the second clock control section (30) outputs the received third signal under the control of the second clock signal; a fourth signal processing unit (60) for generating and outputting a fourth signal from the received third signal; a second signal processing unit (40) generates and outputs a second signal from the input fourth signal.
4. The flip-flop circuit of claim 1,
the first signal processing part (10) comprises a first PMOS (P-channel metal oxide semiconductor) tube (11) and a first NMON tube (12), wherein the grid electrode of the first PMOS tube (11) is connected with the grid electrode of the first NMOS tube (12) and serves as a first input end, and the source electrode of the first PMOS tube (11) is connected with a power supply; the source electrode of the first NMOS tube (12) is grounded; the drain electrode of the first PMOS tube (11) is connected with the drain electrode of the first NMOS tube (12) and serves as a first output end;
the second signal processing part (40) comprises a second PMOS tube (41) and a second NMON tube (42), the grid electrode of the second PMOS tube (41) is connected with the grid electrode of the second NMOS tube (42) and serves as a fourth input end, and the source electrode of the second PMOS tube (41) is connected with a power supply; the source electrode of the second NMOS tube (42) is grounded; and the drain electrode of the second PMOS tube (41) is connected with the drain electrode of the second NMOS tube (42) and serves as a second output end.
5. The flip-flop circuit according to claim 2, wherein the third signal processing section (50) comprises a third PMOS transistor (51) and a third NMOS transistor (52), a gate of the third PMOS transistor (51) is connected to a gate of the third NMOS transistor (52) and serves as a third input terminal, and a source of the third PMOS transistor (51) is connected to a power supply; the source electrode of the third NMOS tube (52) is grounded; the drain electrode of the third PMOS tube (51) is connected with the drain electrode of the third NMOS tube (52) and serves as a third output end;
the fourth signal processing part (60) comprises a fourth PMOS tube (61) and a fourth NMOS tube (62), the grid electrode of the fourth PMOS tube (61) is connected with the grid electrode of the fourth NMOS tube (62) and serves as a fourth input end, and the source electrode of the fourth PMOS tube (61) is connected with a power supply; the source electrode of the fourth NMOS tube (62) is grounded; and the drain electrode of the fourth PMOS tube (61) is connected with the drain electrode of the fourth NMOS tube (62) and serves as a fourth output end.
6. The flip-flop according to claim 1,
the first clock control part (20) comprises a fifth PMOS (P-channel metal oxide semiconductor) tube (21) and a sixth PMOS tube (22), and the grid electrode of the fifth PMOS tube (21) is connected with the grid electrode of the sixth PMOS tube (22) and is used as a first clock signal control end; the source electrode of the fifth PMOS tube (21) is connected with the first output end, the drain electrode of the fifth PMOS tube (21) is connected with the source electrode of the sixth PMOS tube (22), and the drain electrode of the sixth PMOS tube (22) serves as the first clock output end;
the second clock control part (30) comprises a fifth NMOS tube (31) and a sixth NMOS tube (32), and the grid electrode of the fifth NMOS tube (31) is connected with the grid electrode of the sixth NMOS tube (32) and is used as a second clock signal control end; the source electrode of the fifth NMOS tube (31) is connected with the first clock output end, the drain electrode of the fifth NMOS tube (31) is connected with the source electrode of the sixth NMOS tube (32), and the drain electrode of the sixth NMOS tube (32) serves as the second clock output end.
7. The flip-flop circuit of claim 1, further comprising a scan data portion (70) and a mode selection portion (80);
the scanning data part (70) is used for generating and outputting a fifth signal according to the received scanning signal, and the scanning data part (70) comprises a scanning input end used for receiving the scanning signal and a scanning output end used for outputting the fifth signal; the scanning output end is connected with the first clock input end;
the mode selection part (80) is used for generating and outputting a mode control signal according to a received mode selection signal, and the mode selection part (80) comprises a mode selection input end used for receiving the mode selection signal and a mode control output end used for outputting the mode control signal;
the mode selection part (80) further comprises a first switch and a second switch, and the first switch is connected with the first signal processing part (10); the second switch is connected with the scanning data part (70);
when the mode selection signal received by the mode selection part (80) is a scanning mode signal, the first switch is opened so as to disconnect the passage of the first signal processing part (10) and the first clock input end, and the second switch is closed so as to connect the passage of the scanning data part (70) and the first clock input end;
when the mode selection signal received by the mode selection part (80) is an operation signal, the first switch is closed so as to connect the first signal processing part (10) with the path of the first clock input end, and the second switch is opened so as to disconnect the path of the scanning data part (70) with the first clock input end.
8. The flip-flop circuit according to claim 7, wherein said first signal processing section (10) further comprises a first power terminal and a first ground terminal; the first power end is used for connecting a power supply, and the first grounding end is used for grounding;
the scan data part (70) further comprises a second power terminal and a second ground terminal; the second power end is used for connecting a power supply, and the second grounding end is used for grounding;
the scanning data part (70) comprises a seventh PMOS tube (71) and a seventh NMOS tube (72), the grid electrode of the seventh PMOS tube (71) is connected with the grid electrode of the seventh NMOS tube (72) and is used as a scanning input end, the source electrode of the seventh PMOS tube (71) is used as a second power supply end (72), and the source electrode of the seventh NMOS tube (72) is used as a second grounding end.
9. The flip-flop circuit according to claim 8, wherein the first switch comprises an eighth PMOS transistor (81) and an eighth NMOS transistor (82), a gate of the eighth PMOS transistor (81) is for receiving a mode selection signal, a source of the eighth PMOS transistor (81) is for connecting to a power supply, and a drain of the eighth PMOS transistor (81) is connected to the first power supply terminal; the grid electrode of the eighth NMOS tube (82) is used for receiving a mode control signal, the source electrode of the eighth NMOS tube (82) is grounded, and the drain electrode of the eighth NMOS tube (82) is connected with a first grounding end;
the second switch comprises a ninth PMOS (83) and a ninth NMOS (84), the grid electrode of the ninth PMOS (83) is used for receiving a mode control signal, the source electrode of the ninth PMOS (83) is connected with the first output end, and the drain electrode of the ninth PMOS (84) is connected with the first clock input end; the grid electrode of the ninth NMOS tube (83) is used for receiving a mode selection signal, the source electrode of the ninth NMOS tube (83) is connected with the first output end, and the drain electrode of the ninth NMOS tube (83) is connected with the first clock input end (21).
10. The flip-flop circuit according to claim 8 or 9, wherein the mode selection portion (80) comprises a tenth PMOS transistor (85) and a tenth NMOS transistor (86), a gate of the tenth PMOS transistor (85) is connected to a gate of the tenth NMOS transistor (86) and serves as the scan input terminal, and a source of the tenth PMOS transistor (85) is connected to a power supply; the source electrode of the tenth NMOS tube (85) is grounded; the drain electrode of the tenth PMOS tube (85) is connected with the drain electrode of the tenth NMOS tube (86) and serves as the scanning output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910492126.8A CN112054783A (en) | 2019-06-06 | 2019-06-06 | Trigger and trigger with scanning end |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910492126.8A CN112054783A (en) | 2019-06-06 | 2019-06-06 | Trigger and trigger with scanning end |
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| Publication Number | Publication Date |
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| CN112054783A true CN112054783A (en) | 2020-12-08 |
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| CN201910492126.8A Pending CN112054783A (en) | 2019-06-06 | 2019-06-06 | Trigger and trigger with scanning end |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1191371A (en) * | 1997-02-18 | 1998-08-26 | 三菱电机株式会社 | Synchronous semiconductor memory device |
| JP2000022503A (en) * | 1998-06-30 | 2000-01-21 | Hitachi Ltd | Flip-flop circuit |
| CN101079614A (en) * | 2007-06-18 | 2007-11-28 | 清华大学 | Low power consumption clock swing range D trigger |
| JP5116901B1 (en) * | 2009-11-20 | 2013-01-09 | 株式会社半導体エネルギー研究所 | Nonvolatile latch circuit |
| TW201524124A (en) * | 2013-08-30 | 2015-06-16 | Semiconductor Energy Lab | Storage circuit and semiconductor device |
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2019
- 2019-06-06 CN CN201910492126.8A patent/CN112054783A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1191371A (en) * | 1997-02-18 | 1998-08-26 | 三菱电机株式会社 | Synchronous semiconductor memory device |
| JP2000022503A (en) * | 1998-06-30 | 2000-01-21 | Hitachi Ltd | Flip-flop circuit |
| CN101079614A (en) * | 2007-06-18 | 2007-11-28 | 清华大学 | Low power consumption clock swing range D trigger |
| JP5116901B1 (en) * | 2009-11-20 | 2013-01-09 | 株式会社半導体エネルギー研究所 | Nonvolatile latch circuit |
| TW201524124A (en) * | 2013-08-30 | 2015-06-16 | Semiconductor Energy Lab | Storage circuit and semiconductor device |
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