CN112053731A - DDR test method and device - Google Patents
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Abstract
The application provides a DDR test method and a DDR test device, which are applied to the technical field of semiconductor integrated circuit test, and the mutual influence among different data bits in a unit is detected through different test data and write-back data, so that most common memory faults are covered. Meanwhile, when the next reading operation is performed at increased intervals, data is already kept in the storage unit for a period of time, the next reading operation can also detect partial leakage faults, if the leakage faults occur inside the chip, the high-voltage cell leaks electricity to the low-voltage cell, and the high-voltage cell cannot maintain the leakage faults after a period of time. In conclusion, the method is an effective test method in the memory test field, covers most memory faults such as address decoding faults, fixing faults, conversion faults, leakage faults, coupling faults, adjacent vector sensitization faults and the like, and can be effectively applied to normal mass production procedures.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit testing technologies, and in particular, to a DDR test method and apparatus.
Background
The development of electronic technology is changing day by day, along with the improvement of the design capability and the progress of the manufacturing process of the memory chip, the speed and the capacity of the memory chip are also rapidly increased, in order to ensure the reliability of the memory chip during working, the test of the memory chip is more and more emphasized by people, the research on the test method is more and more increased, and how to detect more memory faults with the minimum test time and the minimum test cost is a key concern of testers.
A good semiconductor product is typically tested twice. The wafer test is performed once, that is, the manufactured wafer needs to be strictly tested and then subjected to steps of scribing, packaging and the like, only the wafer particles (Die) passing the test are actually packaged, and the particles not passing the test are directly eliminated. The other time is finished product testing, i.e. chips passing wafer testing and packaging cannot be truly produced, and further testing is still needed to confirm that no fault (mainly faults caused in the packaging process) exists so as to be truly qualified products. The present invention is directed to testing of packaged chips.
For the failure problem of a DRAM (Dynamic Random Access Memory), it needs to be mapped into a logic failure model, and a moving _ inversion test algorithm is developed for detecting such failures, which has many advantages, and first, storage failures ADF, SAF, TF, CF, etc. can be detected, and at the same time, other failures can be partially detected, and the algorithm is a relatively simple test algorithm.
The moving _ inversion algorithm has a simple data background, so that it is difficult to detect a coupling failure between different bits in each memory cell, and secondly, it is a continuous write-read operation from the lowest address to the highest address or from the highest address to the lowest address, so that it is difficult to cover a coupling failure to a cell in the vicinity of a cell, and thus it is necessary to improve the original algorithm.
Disclosure of Invention
The application provides a DDR test method and a DDR test device, which are used for improving the existing moving _ inversion algorithm, optimizing a test flow and effectively improving the DDR fault test coverage rate and test efficiency.
The application adopts the following technical means for solving the technical problems:
the DDR test method provided by the application tests fixed faults and coupling faults in a DDR memory chip, and comprises the following steps:
s1, accessing the DDR memory chip to call a unit digit logic data table in the DDR memory chip, wherein the unit digit logic data table is composed of a plurality of bank partitions, and each bank partition is provided with a plurality of storage units determined by columns and rows;
s2, writing test data DB into the digits in the bank partitions according to the sorting of the bank partitions of the unit digit logic data table and the sorting of the rows and the columns of the bank partitions;
s3, reading test data DB on the digit in the bank partition according to the sorting of a plurality of bank partitions of the unit digit logic data table and the sorting of rows and columns of the bank partitions, judging whether the read value is input test data, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
s4, retesting the DDR memory chip by adopting a first interval test logic of a first interval value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
s5, retesting the DDR memory chip by adopting a second distance test logic of a second distance value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
s6, retesting the DDR memory chip by adopting a third interval test logic of a third interval value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
s7, pass 2nAnd after the interval logic test corresponding to the next interval value, judging whether the DDR memory chip fails, if not, outputting a test result to the terminal equipment, and if so, discarding the DDR memory chip.
Further, step S4 of retesting the DDR memory chip by using the first interval test logic of the first interval value, and determining whether the DDR memory chip fails includes:
the bank partition is provided with a plurality of columns and a plurality of rows of storage units, the first interval value is 1, the first interval test logic is that the first storage unit in the bank partition is tested, the first storage unit starts to continuously jump to the next storage unit in the same row by the column interval being 1 to continue testing, and after the test of the last unit in the row is completed, the next row is jumped to continue testing until all the storage units in the bank partition are tested;
s41, starting from the first storage unit of the bank partition, firstly reading the test data DB written last time and judging whether the test data DB corresponds to the first storage unit, if so, executing the next test without failure, and if not, discarding the DDR memory chip;
s42, writing write-back data DBbar opposite to the test data in the same storage unit of the bank partition;
and S43, reading the write-back data DBbar again in the same storage unit of the bank partition, judging whether the write-back data DBbar corresponds to the write-back data DBbar, if so, judging whether the write-back data DBbar does not have a fault, testing the next storage unit by the same steps until all the units are tested, if all the units pass the test, executing the next step S5, and if not, abandoning the DDR memory chip.
Further, the step S5 of retesting the DDR memory chip by using the second pitch test logic with the second pitch value, and determining whether the DDR memory chip fails includes:
the bank partition is provided with a plurality of columns and a plurality of rows of storage units, the second distance value is 2, the second distance test logic is that the first storage unit in the bank partition is tested, the first storage unit starts to jump to the third storage unit in the same row at the column interval of 2 so as to jump over one storage unit, the test is continued, and the last unit in the row jumps to the next row after the test is finished, so that the test is continued until all the storage units in the bank partition are tested;
s51, reading write-back data DBbar written last time in the same storage unit of the bank partition, judging whether the write-back data DBbar corresponds to the write-back data DBbar, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
s52, writing test data DB opposite to the write-back data DBbar in the same storage unit of the bank partition;
and S53, reading the test data DB again in the same memory cell of the bank partition, judging whether the test data DB corresponds to the memory cell, if so, testing the next memory cell without failure in the same step until all the cells to be tested are tested, then performing the column separation test on the other untested cells, if all the cells pass the test, executing the next step S6, and if not, abandoning the DDR memory chip.
Further, step S6, which is to retest the DDR memory chip by using a third distance test logic with a third distance value, and determine whether the DDR memory chip fails includes:
the bank partition is provided with a plurality of rows and columns of storage units, the third distance value is 4, the third distance test logic is that the first storage unit in the test bank partition starts to jump to the fifth storage unit in the same row by the column interval of 4 so as to jump over three storage units for continuous test, the last unit in the row jumps to the next row for continuous test after the test is finished, until all the storage units of the bank partition finish the test, and the other untested columns are subjected to column interval test after one round of test is executed.
Further, the pass 2nAfter the interval logic test corresponding to the next interval value, judging whether the DDR memory chip fails, if not, outputting a test result to the terminal equipment, and if so, abandoning the DDR memory chip, comprising the following steps of:
the test result is a dot-matrix diagram to carry out quantitative test and determine whether the plurality of DDR memory chips are in fault.
The present application further provides a DDR test device, including:
the calling unit is used for accessing the DDR memory chip so as to call a unit digit logic data table in the DDR memory chip, the unit digit logic data table is composed of a plurality of bank partitions, and the bank partitions are provided with storage units determined by a plurality of columns and a plurality of rows;
the writing unit writes test data DB into the digits in the bank partitions according to the sorting of the bank partitions of the unit digit logic data table and the row and column sorting of the bank partitions;
the reading test unit is used for reading test data DB on the digit in the bank partition according to the sequencing of the plurality of bank partitions of the unit digit logic data table and the row and column sequencing of the bank partitions, judging whether the read value is input test data or not, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
the first interval test unit is used for retesting the DDR memory chip by adopting first interval test logic of a first interval value, judging whether the DDR memory chip fails or not, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
the second spacing test unit is used for retesting the DDR memory chip by adopting second spacing test logic of a second spacing value, judging whether the DDR memory chip fails or not, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
the third interval testing unit is used for retesting the DDR memory chip by adopting a third interval testing logic of a third interval value, judging whether the DDR memory chip fails or not, if not, executing the next testing without failure, and if so, abandoning the DDR memory chip;
output unit, passing through 2nAnd after the interval logic test corresponding to the next interval value, judging whether the DDR memory chip fails, if not, outputting a test result to the terminal equipment, and if so, discarding the DDR memory chip.
The application provides a DDR test method and a DDR test device, which have the following beneficial effects:
the method covers the coupling fault detection of the continuous memory storage unit and increases the detection of the mutual influence of the storage unit and the nearby units, such as short circuit and the like, through the interval reading and writing of the adjacent units of the storage unit. Through different test data and write-back data, the mutual influence among different data bits in the unit is detected, and most common memory faults are covered. Meanwhile, when the next reading operation is performed at increased intervals, data is already kept in the storage unit for a period of time, the next reading operation can also detect partial leakage faults, if the leakage faults occur inside the chip, the high-voltage cell leaks electricity to the low-voltage cell, and the high-voltage cell cannot maintain the leakage faults after a period of time. In conclusion, the method is an effective test method in the memory test field, covers most memory faults such as address decoding fault ADF, fixed fault SAF, conversion fault TF, leakage fault DRF, coupling fault CF, adjacent vector sensitization fault NPSF and the like, and can be effectively applied to normal volume production procedures through actual tests.
Drawings
FIG. 1 is a schematic flow chart illustrating an embodiment of a DDR test method of the present application;
FIG. 2 is a schematic diagram illustrating a test data write operation according to an embodiment of the DDR test method of the present application;
FIG. 3 is a schematic diagram illustrating a read operation of test data according to an embodiment of the DDR test method of the present application;
FIG. 4 is a sub-flowchart of step S4 of the DDR test method of the present application;
FIG. 5 is a schematic diagram illustrating the principle of the interval row test when the first interval value is 1 according to an embodiment of the DDR test method of the present application;
FIG. 6 is a sub-flowchart of step S5 of the DDR test method of the present application;
FIG. 7 is a schematic diagram illustrating the principle of the interval row test when the second interval value is 2 according to an embodiment of the DDR test method of the present application;
FIG. 8 is a schematic diagram illustrating the principle of the inter-row test when the third interval value is 4 according to an embodiment of the DDR test method of the present application;
FIG. 9 is a block diagram of an embodiment of a DDR test apparatus according to the present application.
The implementation, functional features and advantages of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that the terms "comprises," "comprising," and "having" and any variations thereof in the description and claims of this application and the drawings described above are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. In the claims, the description and the drawings of the specification of the present application, relational terms such as "first" and "second", and the like, may be used solely to distinguish one entity/action/object from another entity/action/object without necessarily requiring or implying any actual such relationship or order between such entities/actions/objects.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1 and fig. 2 and 3, fig. 1 is a schematic flow chart of a DDR test method in an embodiment of the present application, and fig. 2 and 3 are schematic diagrams of a unit digital logic data table during writing and during reading, respectively;
a DDR test method tests fixed faults and coupling faults in a DDR memory chip, and comprises the following steps:
s1, accessing the DDR memory chip to call a unit digit logic data table in the DDR memory chip, wherein the unit digit logic data table is composed of a plurality of bank partitions, and each bank partition is provided with a plurality of storage units determined by columns and rows;
the description adopts a testing device to execute a DDR testing method, and the DDR memory chip is put into the testing device, so that the testing device can call a unit digital logic data table in the DDR memory chip.
S2, writing test data DB into the digits in the bank partitions according to the sorting of the bank partitions of the unit digit logic data table and the sorting of the rows and the columns of the bank partitions;
referring to fig. 2, a schematic diagram of a test device writing test data DB to a plurality of bank partitions and a plurality of ranks in the bank partitions is shown, where the test data is 1 or 0 in binary; it should be noted that:
in order to be able to detect an in-word coupling failure, an increased modified test data DB is used, in which the number of consecutive 0 s and consecutive 1 s is incremented from 1 to W (W is a bit width) until K ═ log W) +1 data backgrounds are satisfied, and a test algorithm is performed for each data background once. Taking 8-bit-wide data as an example, the number of consecutive 0 s and consecutive 1 s is 1, 2, 4, 8, and there are 4 data backgrounds DB: 00000000, 00001111, 00110011, 01010101, obtaining 4 dbbars after bitwise negation: 11111111, 11110000, 11001100 and 10101010.
S3, reading test data DB on the digit in the bank partition according to the sorting of a plurality of bank partitions of the unit digit logic data table and the sorting of rows and columns of the bank partitions, judging whether the read value is input test data, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
referring to fig. 3, a schematic diagram of reading test data DB from a plurality of bank partitions and a plurality of rows and columns in the bank partitions for a test device is shown, that is: writing from the 0 th row of the first bank to the last column from the 0 th column in each row unit, ending to the last unit of the last bank, writing test data DB in each row and each column of each bank, reading data in the sequence, comparing, reading data in the sequence, reading each unit in sequence, and when finishing reading and writing the last unit, if the read value and the written value of a certain unit are different, considering that a fault occurs.
S4, retesting the DDR memory chip by adopting the first interval test logic of the first interval value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
specifically, referring to fig. 4 and 5, fig. 4 is a schematic view of the sub-flow of the step S4, and fig. 5 is a schematic view of the step S4;
the bank partition is provided with a plurality of columns and a plurality of rows of storage units, a first interval value is 1, first interval test logic is that a first storage unit in the bank partition is tested, the first storage unit starts to jump to a next storage unit continuously in the same row with a column interval of 1 to carry out continuous test, and after the test of the last unit in the row is finished, the next row is jumped to carry out continuous test until all the storage units in the bank partition are tested;
s41, in the same storage unit of the bank partition, firstly reading the test data DB written at the last time, and judging whether the test data DB corresponds to the test data DB, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
s42, writing write-back data DBbar opposite to the test data in the same storage unit of the bank partition;
and S43, reading the write-back data DBbar again in the same storage unit of the bank partition, judging whether the write-back data DBbar corresponds to the write-back data DBbar, if so, judging whether the write-back data DBbar does not have a fault, testing the next storage unit by the same steps until all the units are tested, if all the units pass the test, executing the next step S5, and if not, abandoning the DDR memory chip.
And sequentially carrying out reading operation on each unit for the second time, writing write-back data DBbar after the test data DB is inverted by bits into the unit if the unit has no fault, then reading the written DBbar again, carrying out the same operation on the next unit until the last unit with a first interval value of 1 if the data read out each time is consistent with the written data, and considering that the fault occurs if the value read out by a certain unit in the step is not the expected value. The written test data DB is read first, i.e. comprises two consecutive reads, the first read detecting a failure caused by the previous write and the second read detecting a failure caused by the first read. And the leakage fault BF can be detected in a continuous write operation or a continuous read operation.
S5, retesting the DDR memory chip by adopting a second distance test logic of a second distance value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
specifically, referring to fig. 6 and fig. 7, fig. 6 is a schematic view of the sub-flow of the step S5, and fig. 7 is a schematic view of the step S5;
the bank partition is provided with a plurality of columns and a plurality of rows of storage units, the second spacing value is 2, the second spacing test logic is that the first storage unit in the test bank partition starts to jump to the third storage unit in the same row by the column spacing of 2 so as to jump over one storage unit for continuous test, and after the test of the last unit in the row is finished, the next row is jumped for continuous test until all the storage units in the bank partition are tested;
s51, in the same storage unit of the bank partition, reading the last written-in write-back data DBbar, judging whether the write-back data DBbar corresponds to the last written-in write-back data DBbar, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
s52, writing test data DB opposite to the write-back data DBbar in the same storage unit of the bank partition;
and S53, reading the test data DB again in the same memory cell of the bank partition, judging whether the test data DB corresponds to the memory cell, if so, testing the next memory cell without failure in the same step until all the cells to be tested are tested, then performing the column separation test on the other untested cells, if all the cells pass the test, executing the next step S6, and if not, abandoning the DDR memory chip.
And reading the write-back data DBbar written in the last step for the first unit, writing the test data DB for the first unit if the first unit has no fault, and reading the written test data DB again. The same operation is then performed on the next cell, one cell apart, i.e. the second interval value for each read-write operation is 2, in such a way that it is written to the last memory cell. Thus, half of the memory units are read and written, the other half of the memory units respectively carry out operations of reading DBbar, writing DB and reading DB from the second unit in the same interval of 2 until the last memory unit is operated, the read-write operation on all the memory units is finished, and if the read unit at a certain time in the process is inconsistent with the expected value, a fault is considered to occur.
S6, retesting the DDR memory chip by adopting a third interval test logic of a third interval value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
specifically, referring to fig. 8, a schematic diagram of step S6 is shown;
the bank partition is provided with a plurality of rows and columns of storage units, a third interval value is 4, third interval test logic is that the first storage unit in the bank partition is tested, the first storage unit in the bank partition starts to jump to a fifth storage unit in the same row at a column interval of 4 so as to jump to the fifth storage unit for continuous test, the last unit in the row jumps to the next row for continuous test after the test is finished until all the storage units of the bank partition finish the test, and the other untested columns are subjected to column interval test after one round of test is executed.
And reading the test data DB written in the last step for the first unit, if the test data DB has no fault, writing write-back data DBbar for the first unit, then reading the written write-back data DBbar, and then performing the same read-write operation for one unit after the three units at a third interval value of 4 intervals until the last address, wherein one quarter of the storage units in the bank partition perform the operation. Then, starting from the second unit, the reading and writing operations of the unit are carried out with the third interval value of 4 until the last address, starting from the third unit, the reading and writing operations of the unit are carried out with the third interval value of 4 until the last unit, and starting from the fourth unit, the reading and writing operations of the unit are carried out with the third interval value of 4 until the last unit. These operations have been performed for all cells at a third interval value of 4, covering all memory cells.
S7, pass 2nAnd after the interval logic test corresponding to the next interval value, judging whether the DDR memory chip fails, if not, outputting a test result to the terminal equipment, and if so, discarding the DDR memory chip.
The test result is a dot-matrix diagram to quantitatively test and determine whether the plurality of DDR memory chips are in fault.
And the terminal equipment displays the dot matrix diagram by adopting a display module, wherein the DDR marked in the dot matrix diagram is the fault DDR which is not executed with all the steps from S1 to S7.
Referring to fig. 9, a block diagram of a DDR test device provided in the present application is shown, where the DDR test device includes:
the DDR memory chip comprises a calling unit 1 and a memory unit, wherein the calling unit 1 is used for accessing a DDR memory chip so as to call a unit digit logic data table in the DDR memory chip, the unit digit logic data table is composed of a plurality of bank partitions, and each bank partition is provided with a plurality of storage units determined by columns and rows;
the writing unit 2 writes test data DB into the digits in the bank partitions according to the sorting of the plurality of bank partitions in the unit digit logic data table and the sorting of the rows and the columns of the bank partitions;
the reading test unit 3 is used for reading test data DB on the digit in the bank partition according to the sequencing of a plurality of bank partitions of the unit digit logic data table and the sequencing of rows and columns of the bank partitions, judging whether the read value is input test data or not, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
the first interval test unit 4 is used for retesting the DDR memory chips by adopting first interval test logic of a first interval value, judging whether the DDR memory chips are in fault, if not, executing the next test without fault, and if so, abandoning the DDR memory chips;
the second pitch test unit 5 is configured to retest the DDR memory chip by using a second pitch test logic of a second pitch value, and determine whether the DDR memory chip fails, if not, execute the next test without failure, and if so, abandon the DDR memory chip;
the third interval testing unit 6 is used for retesting the DDR memory chip by adopting a third interval testing logic of a third interval value, judging whether the DDR memory chip fails, if not, executing the next testing without failure, and if so, abandoning the DDR memory chip;
In summary, the method of the present application covers the detection of coupling failure of a continuous memory storage unit and increases the detection of the mutual influence of the storage unit and nearby units, such as short circuit, etc., by reading and writing adjacent units of a storage unit at intervals. Through different test data and write-back data, the mutual influence among different data bits in the unit is detected, and most common memory faults are covered. Meanwhile, when the next reading operation is performed at increased intervals, data is already kept in the storage unit for a period of time, the next reading operation can also detect partial leakage faults, if the leakage faults occur inside the chip, the high-voltage cell leaks electricity to the low-voltage cell, and the high-voltage cell cannot maintain the leakage faults after a period of time. In conclusion, the method is an effective test method in the memory test field, covers most memory faults such as address decoding fault ADF, fixed fault SAF, conversion fault TF, leakage fault DRF, coupling fault CF, adjacent vector sensitization fault NPSF and the like, and can be effectively applied to normal volume production procedures through actual tests.
Although embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the application, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A DDR test method is characterized in that the test method tests fixed faults and coupling faults in a DDR memory chip, and comprises the following steps:
s1, accessing the DDR memory chip to call a unit digit logic data table in the DDR memory chip, wherein the unit digit logic data table is composed of a plurality of bank partitions, and each bank partition is provided with a plurality of storage units determined by columns and rows;
s2, writing test data DB into the digits in the bank partitions according to the sorting of the bank partitions of the unit digit logic data table and the sorting of the rows and the columns of the bank partitions;
s3, reading test data DB on the digit in the bank partition according to the sorting of a plurality of bank partitions of the unit digit logic data table and the sorting of rows and columns of the bank partitions, judging whether the read value is input test data, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
s4, retesting the DDR memory chip by adopting a first interval test logic of a first interval value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
s5, retesting the DDR memory chip by adopting a second distance test logic of a second distance value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
s6, retesting the DDR memory chip by adopting a third interval test logic of a third interval value, judging whether the DDR memory chip fails, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
s7, pass 2nAnd after the interval logic test corresponding to the next interval value, judging whether the DDR memory chip fails, if not, outputting a test result to the terminal equipment, and if so, discarding the DDR memory chip.
2. The DDR test method of claim 1, wherein the step S4 of retesting the DDR memory chip using a first interval test logic with a first interval value, and determining whether the DDR memory chip fails comprises:
the bank partition is provided with a plurality of columns and a plurality of rows of storage units, the first interval value is 1, the first interval test logic is that the first storage unit in the bank partition is tested, the first storage unit starts to continuously jump to the next storage unit in the same row by the column interval being 1 to continue testing, and after the test of the last unit in the row is completed, the next row is jumped to continue testing until all the storage units in the bank partition are tested;
s41, starting from the first storage unit of the bank partition, firstly reading the test data DB written at the last time, judging whether the test data DB corresponds to the test data DB, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
s42, writing write-back data DBbar opposite to the test data DB in the same storage unit of the bank partition;
and S43, reading the write-back data DBbar again in the same storage unit of the bank partition, judging whether the write-back data DBbar corresponds to the write-back data DBbar, if so, judging whether the write-back data DBbar does not have a fault, testing the next storage unit by the same steps until all the units are tested, if all the units pass the test, executing the next step S5, and if not, abandoning the DDR memory chip.
3. The DDR test method according to claim 1, wherein the step S5 of retesting the DDR memory chip by using the second pitch test logic with the second pitch value, and determining whether the DDR memory chip fails includes:
the bank partition is provided with a plurality of columns and a plurality of rows of storage units, the second distance value is 2, the second distance test logic is that the first storage unit in the bank partition is tested, the first storage unit starts to jump to the third storage unit in the same row at the column interval of 2 so as to jump over one storage unit, the test is continued, and the last unit in the row jumps to the next row after the test is finished, so that the test is continued until all the storage units in the bank partition are tested;
s51, reading write-back data DBbar written last time in the same storage unit of the bank partition, judging whether the write-back data DBbar corresponds to the write-back data DBbar, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
s52, writing test data DB opposite to the write-back data DBbar in the same storage unit of the bank partition;
and S53, reading the test data DB again in the same memory cell of the bank partition, judging whether the test data DB corresponds to the memory cell, if so, testing the next memory cell without failure in the same step until all the cells to be tested are tested, then performing the column separation test on the other untested cells, if all the cells pass the test, executing the next step S6, and if not, abandoning the DDR memory chip.
4. The DDR test method according to claim 1, wherein the step S6 of retesting the DDR memory chip using a third interval test logic with a third interval value, and determining whether the DDR memory chip fails includes:
the bank partition is provided with a plurality of rows and columns of storage units, the third distance value is 4, the third distance test logic is that the first storage unit in the test bank partition starts to jump to the fifth storage unit in the same row by the column interval of 4 so as to jump over three storage units for continuous test, the last unit in the row jumps to the next row for continuous test after the test is finished, until all the storage units of the bank partition finish the test, and the other untested columns are subjected to column interval test after one round of test is executed.
5. The DDR test method of claim 1, wherein the pass 2nAfter the interval logic test corresponding to the next interval value, judging whether the DDR memory chip fails, if not, outputting a test result to the terminal equipment, and if so, abandoning the DDR memory chip, comprising the following steps of:
the test result is a dot-matrix diagram to carry out quantitative test and determine whether the plurality of DDR memory chips are in fault.
6. A DDR test apparatus, comprising:
the calling unit is used for accessing the DDR memory chip so as to call a unit digit logic data table in the DDR memory chip, the unit digit logic data table is composed of a plurality of bank partitions, and the bank partitions are provided with storage units determined by a plurality of columns and a plurality of rows;
the writing unit writes test data DB into the digits in the bank partitions according to the sorting of the bank partitions of the unit digit logic data table and the row and column sorting of the bank partitions;
the reading test unit is used for reading test data DB on the digit in the bank partition according to the sequencing of the plurality of bank partitions of the unit digit logic data table and the row and column sequencing of the bank partitions, judging whether the read value is input test data or not, if so, executing the next test without failure, and if not, abandoning the DDR memory chip;
the first interval test unit is used for retesting the DDR memory chip by adopting first interval test logic of a first interval value, judging whether the DDR memory chip fails or not, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
the second spacing test unit is used for retesting the DDR memory chip by adopting second spacing test logic of a second spacing value, judging whether the DDR memory chip fails or not, if not, executing the next test without failure, and if so, abandoning the DDR memory chip;
the third interval testing unit is used for retesting the DDR memory chip by adopting a third interval testing logic of a third interval value, judging whether the DDR memory chip fails or not, if not, executing the next testing without failure, and if so, abandoning the DDR memory chip;
output unit, passing through 2nAnd after the interval logic test corresponding to the next interval value, judging whether the DDR memory chip fails, if not, outputting a test result to the terminal equipment, and if so, discarding the DDR memory chip.
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