CN112053717A - DICE-based anti-single-event-upset magnetic memory reading circuit - Google Patents

DICE-based anti-single-event-upset magnetic memory reading circuit Download PDF

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CN112053717A
CN112053717A CN202010910613.4A CN202010910613A CN112053717A CN 112053717 A CN112053717 A CN 112053717A CN 202010910613 A CN202010910613 A CN 202010910613A CN 112053717 A CN112053717 A CN 112053717A
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transistor
latch circuit
internal node
circuit block
circuit module
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CN112053717B (en
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张德明
王贤
张凯丽
赵巍胜
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Hefei Innovation Research Institute of Beihang University
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Hefei Innovation Research Institute of Beihang University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1697—Power supply circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to a DICE-based magnetic memory reading circuit resisting single event upset, which comprises a PRE-charging circuit module, a PRE-charging circuit module and a control circuit, wherein the input end of the PRE-charging circuit module is connected with a PRE-charging signal PRE; the output end of the pre-charge circuit module is connected with the internal node Q1, the internal node Q2, the internal node Q3 and the internal node Q4 of the latch circuit module; the output end of the latch circuit module is connected with the input end of the read circuit separation module; the output end of the read circuit separation module is connected with a bit line BL1 and a bit line BL2 of a magnetic random access memory storage unit of data information to be read; the input end of the output circuit module is connected with the internal node Q1 and the internal node Q3 of the latch circuit module; the output end OUT of the output circuit module is the output end of the magnetic memory reading circuit based on DICE single event upset resistance. The invention not only can realize the data information reading function with high speed and low power consumption, but also has the capability of resisting single event upset in the data information reading process.

Description

DICE-based anti-single-event-upset magnetic memory reading circuit
Technical Field
The invention relates to the technical field of integrated circuit radiation hardening and nonvolatile storage crossing, in particular to a DICE (digital imaging and serial digital imaging) single event upset resistant magnetic memory reading circuit.
Background
Magnetic Random Access Memory (MRAM) has a nonvolatile structure,The system has the characteristics of low power consumption, quick access, inherent radiation resistance and the like, and has great application potential in the field of future aerospace. MRAM is mainly composed of a memory cell array and a peripheral read/write circuit. As a memory cell of the MRAM, a Magnetic Tunnel Junction (MTJ) is mainly composed of two ferromagnetic layers and a Tunnel barrier layer sandwiched therebetween. The magnetization direction of one of the ferromagnetic layers is fixed, referred to as the pinned layer; while the magnetization direction of the other ferromagnetic layer is changeable and is called a free layer. Depending on the relative magnetization directions of the free and fixed layers, the MTJ can exhibit two different resistance states: when the magnetization directions of the two are the same, the MTJ exhibits a Low Resistance state (R)L) (ii) a Conversely, the MTJ exhibits a High Resistance state (R)H). Since MTJs use magnetization directions, rather than electronic charges, to store data information, they are inherently radiation resistant.
The peripheral read/write circuit of the MRAM is formed based on the conventional semiconductor technology and is susceptible to high-energy radiation particles. In MRAM products, differential signal reading circuits are widely used because of their characteristics of high speed, high reliability, low power consumption, and the like. However, when the output node of the differential signal reading circuit is hit by a radiation particle with sufficient energy, the logic level of the node is inverted, thereby causing a data information reading error, which is called a single-particle inversion. Therefore, how to design a differential signal reading circuit with single event upset resistance is one of the main challenges facing future application of MRAM to the aerospace field.
Disclosure of Invention
The invention provides a DICE-based single event upset resistant magnetic memory reading circuit, which can overcome the defects and improve the radiation resistance of an MRAM.
In order to achieve the purpose, the invention adopts the following technical scheme:
a DICE-based magnetic memory reading circuit resisting single event upset comprises a pre-charging circuit module, a latch circuit module, a reading circuit separation module and an output circuit module.
The input end of the PRE-charging circuit module is connected with a PRE-charging signal PRE; the output terminal of the precharge circuit block is connected to the internal node Q1, the internal node Q2, the internal node Q3, and the internal node Q4 of the latch circuit block.
The output end of the latch circuit module is connected with the input end of the read circuit separation module.
The output end of the read circuit separation module is connected with the bit line BL1 and the bit line BL2 of the magnetic random access memory storage unit of the data information to be read.
The input end of the output circuit module is connected with the internal node Q1 and the internal node Q3 of the latch circuit module; the output end OUT of the output circuit module is the output end of the DICE-based single event upset resistant magnetic memory reading circuit.
The pre-charging circuit module comprises 4 PMOS transistors; 4 PMOS transistors are respectively defined as P1-P4; the source electrode of the transistor P1, the source electrode of the transistor P2, the source electrode of the transistor P3 and the source electrode of the transistor P4 are all connected with a power supply VDD(ii) a The gate of the transistor P1, the gate of the transistor P2, the gate of the transistor P3 and the gate of the transistor P4 are all connected with a precharge signal PRE; the drain of the transistor P1 is connected to the internal node Q1 of the latch circuit block; the drain of the transistor P2 is connected to the internal node Q2 of the latch circuit block; the drain of the transistor P3 is connected to the internal node Q3 of the latch circuit block; the drain of the transistor P4 is connected to the internal node Q4 of the latch circuit block.
The latch circuit module comprises 4 PMOS transistors and 4 NMOS transistors; 4 PMOS transistors are respectively defined as P5-P8; the 4 NMOS transistors are respectively defined as N1-N4; the source electrode of the transistor P5, the source electrode of the transistor P6, the source electrode of the transistor P7 and the source electrode of the transistor P8 are all connected with a power supply VDD(ii) a The drain of the transistor P5 is connected with the gate of the transistor P6, the gate of the transistor N4 and the drain of the transistor N1, and the connection point is the internal node Q1 of the latch circuit module; the drain of the transistor P6 is connected to the gate of the transistor P7, the gate of the transistor N1 and the drain of the transistor N2, at the point where the latch is connectedInternal node Q2 of the circuit block; the drain of the transistor P7 is connected with the gate of the transistor P8, the gate of the transistor N2 and the drain of the transistor N3, and the connection point is the internal node Q3 of the latch circuit module; the drain of the transistor P8 is connected with the gate of the transistor P5, the gate of the transistor N3 and the drain of the transistor N4, and the connection point is the internal node Q4 of the latch circuit module; the source of the transistor N1 is connected with the source of the transistor N3, and the connection point is the output end A of the latch circuit module; the source of the transistor N2 is connected to the source of the transistor N4, the connection point being the output B of the latch circuit block.
The reading circuit separation module comprises 2 NMOS transistors; 2 NMOS transistors are defined as N5 and N6, respectively; the drain electrode of the transistor N5 is connected with the output end A of the latch circuit module; the drain electrode of the transistor N6 is connected with the output end B of the latch circuit module; the gate of the transistor N5 and the gate of the transistor N6 are both connected with a read enable signal RE; the source of the transistor N5 is connected with the bit line BL1 of the magnetic random access memory storage unit of the data information to be read; the source of transistor N6 is connected to the bit line BL2 of the MRAM memory cell from which data information is to be read.
The output circuit module comprises 2 PMOS transistors and 2 NMOS transistors; 2 PMOS transistors are defined as P9 and P10, respectively; 2 NMOS transistors are defined as N7 and N8, respectively; the source of the transistor P9 is connected with a power supply VDD(ii) a The drain of the transistor P9 is connected to the source of the transistor P10; the drain electrode of the transistor P10 is connected with the drain electrode of the transistor N7, and the connection point is the output end OUT of the output circuit module; the source of the transistor N7 is connected to the drain of the transistor N8; the source of the transistor N8 is connected with the grounding voltage GND; the gate of the transistor P9 and the gate of the transistor N8 are both connected to the internal node Q1 of the latch circuit block; the gate of the transistor P10 and the gate of the transistor N7 are both connected to the internal node Q3 of the latch circuit block.
The Magnetic random access memory storage unit of the data information to be read comprises 2 Magnetic Tunnel Junctions (MTJ) and 2 NMOS transistors; 2 MTJ are respectively definedDefined as MTJ0 and MTJ 1; 2 NMOS transistors are defined as N9 and N10, respectively; the free layer of MTJ0 and the free layer of MTJ1 are connected to bit line BL1 and bit line BL2, respectively, of the MRAM memory cell where data information is to be read; the pinned layer of MTJ0 and the pinned layer of MTJ1 are connected to the drain of transistor N9 and the drain of transistor N10, respectively; the gate of the transistor N9 and the gate of the transistor N10 are both connected to the word line WL; the source of the transistor N9 and the source of the transistor N10 are both connected to a source line SL; the magnetic random access memory storage unit of the data information to be read stores 1-bit data information by utilizing 2 MTJs in complementary resistance states: when the resistance state of MTJ0 is RLAnd the resistance state of MTJ1 is RHWhen the data information is read, the data information stored in the magnetic random access memory storage unit of the data information to be read is 1; when the resistance state of MTJ0 is RHAnd the resistance state of MTJ1 is RLAnd when the data information is read, the data information stored in the magnetic random access memory storage unit of the data information to be read is '0'.
The invention relates to a DICE-based magnetic memory read circuit resistant to single event upset, which works in two stages: one is a precharge phase; one is the data information reading phase. In these two phases, the word line WL of the mram cell to be read has a logic level "1" and the source line SL has a logic level "0".
When the magnetic memory reading circuit based on DICE single event upset resistance works in a PRE-charging stage, the logic levels of a PRE-charging signal PRE and a read enabling signal RE are both '0', a transistor P1, a transistor P2, a transistor P3 and a transistor P4 in a PRE-charging circuit module are all in a conducting state, a transistor N5 and a transistor N6 in a reading circuit separation module are all in a closing state, and the voltages of an internal node Q1, an internal node Q2, an internal node Q3 and an internal node Q4 of a latch circuit module are all PRE-charged to a supply voltage VDD。
When the magnetic memory reading circuit based on DICE single event upset resistance works in a data information reading stage, the logic levels of a PRE-charge signal PRE and a read enable signal RE are both '1', a transistor P1, a transistor P2, a transistor P3 and a transistor P4 in a PRE-charge circuit module are all in an off state, a transistor N5 and a transistor N6 in a reading circuit separation module are all in an on state, and the voltages of an internal node Q1, an internal node Q2, an internal node Q3 and an internal node Q4 of a latch circuit module depend on the resistance difference between an MTJ0 and an MTJ1 in a magnetic random access memory unit of data information to be read, which is respectively connected with an output end A and an output end B of the latch circuit module; if the resistance value of the MTJ0 in the magnetic random access memory cell of the to-be-read data information connected to the output terminal a of the latch circuit module is greater than the resistance value of the MTJ1 in the magnetic random access memory cell of the to-be-read data information connected to the output terminal B of the latch circuit module, the logic levels of the internal node Q2 and the internal node Q4 of the latch circuit module are both "0", the logic levels of the internal node Q1 and the internal node Q3 of the latch circuit module are both "1", and the logic level of the output terminal OUT of the output circuit module is "0", that is, the data information read by the magnetic memory read circuit based on DICE anti-single event upset is "0"; if the resistance value of the MTJ0 in the magnetic random access memory cell of the to-be-read data information connected to the output terminal a of the latch circuit module is smaller than the resistance value of the MTJ1 in the magnetic random access memory cell of the to-be-read data information connected to the output terminal B of the latch circuit module, the logic levels of the internal node Q2 and the internal node Q4 of the latch circuit module are both "1", the logic levels of the internal node Q1 and the internal node Q3 of the latch circuit module are both "0", and the logic level of the output terminal OUT of the output circuit module is "1", that is, the data information read by the magnetic memory read circuit based on DICE anti-single event upset is "1".
When the magnetic memory reading circuit based on DICE single event upset resistance works in a data information reading stage, if the logic levels of an internal node Q1 and an internal node Q3 of a latch circuit module are '1', the logic levels of an internal node Q2 and an internal node Q4 of the latch circuit module are '0', and the logic level of an output end OUT of an output circuit module is '0', the drain electrode of a transistor P6, the drain electrode of a transistor P8, the drain electrode of a transistor N1, the drain electrode of a transistor N3 and the drain electrode of the transistor P10 in the output circuit module in a reverse bias state, and the internal node Q1, the internal node Q2, the internal node Q3, the internal node Q4 and the output end OUT of the output circuit module are radiation sensitive nodes; in this case, the recovery process after each sensitive node is turned over by the ion radiation is as follows:
(1) when the drain of the transistor N1 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q1 of the latch circuit block is pulled low, and is inverted, so that the logic level becomes "0", thereby causing the transistor N4 in the latch circuit block to be turned off and the transistor P6 to be turned on; after the transistor P6 in the latch circuit block is turned on, the logic level of the internal node Q2 of the latch circuit block is pulled high; after the transistor N4 in the latch circuit block is turned off, the internal node Q4 of the latch circuit block is in a high-impedance state, and keeps the logic level "0", thereby causing the transistor N3 in the latch circuit block to keep the off state, and the internal node Q3 of the latch circuit block to keep the logic level "1"; the high level of the internal node Q3 of the latch circuit block turns on the transistor N2 of the latch circuit block, thereby gradually discharging the internal node Q2 of the latch circuit block; the low level of the internal node Q4 of the latch circuit block turns on the transistor P5 of the latch circuit block, thereby gradually charging the internal node Q1 of the latch circuit block; finally, the internal node Q1 and the internal node Q2 of the latch circuit module are respectively restored to the original logic levels '1' and '0'; in the whole process, the internal node Q3 of the latch circuit block keeps the logic level "1", so that the transistor P10 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "0".
(2) When the drain of the transistor P6 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q2 of the latch circuit block is pulled high, and is inverted, so that the logic level becomes "1", thereby causing the transistor P7 in the latch circuit block to be turned off and the transistor N1 to be turned on; after the transistor N1 in the latch circuit block is turned on, the logic level of the internal node Q1 of the latch circuit block is pulled low; after the transistor P7 in the latch circuit block is turned off, the internal node Q3 of the latch circuit block is in a high-impedance state and keeps the logic level "1", so that the transistor P8 in the latch circuit block keeps the off state and the internal node Q4 of the latch circuit block keeps the logic level "0"; the low level of the internal node Q4 of the latch circuit block turns on the transistor P5 of the latch circuit block, thereby gradually charging the internal node Q1 of the latch circuit block; the high level of the internal node Q3 of the latch circuit block turns on the transistor N2 in the latch circuit block, thereby gradually discharging the internal node Q2 of the latch circuit block; finally, the internal node Q2 and the internal node Q1 of the latch circuit module are respectively restored to the original logic levels '0' and '1'; in the whole process, the internal node Q3 of the latch circuit block keeps the logic level "1", so that the transistor P10 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "0".
(3) When the drain of the transistor N3 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q3 of the latch circuit block is pulled low, and is inverted, so that the logic level becomes "0", thereby causing the transistor N2 in the latch circuit block to be turned off and the transistor P8 to be turned on; after the transistor P8 in the latch circuit block is turned on, the logic level of the internal node Q4 of the latch circuit block is pulled high; after the transistor N2 in the latch circuit block is turned off, the internal node Q2 of the latch circuit block is in a high-impedance state, and keeps the logic level "0", thereby causing the transistor N1 in the latch circuit block to keep the off state, and the internal node Q1 of the latch circuit block to keep the logic level "1"; the high level of the internal node Q1 of the latch circuit block turns on the transistor N4 of the latch circuit block, thereby gradually discharging the internal node Q4 of the latch circuit block; the low level of the internal node Q2 of the latch circuit block turns on the transistor P7 of the latch circuit block, thereby gradually charging the internal node Q3 of the latch circuit block; finally, the internal node Q3 and the internal node Q4 of the latch circuit module are respectively restored to the original logic levels '1' and '0'; in the whole process, the internal node Q1 of the latch circuit block keeps the logic level "1", so that the transistor P9 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "0".
(4) When the drain of the transistor P8 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q4 of the latch circuit block is pulled high, and is inverted, so that the logic level becomes "1", thereby causing the transistor P5 in the latch circuit block to be turned off and the transistor N3 to be turned on; after the transistor N3 in the latch circuit block is turned on, the logic level of the internal node Q3 of the latch circuit block is pulled low; after the transistor P5 in the latch circuit block is turned off, the internal node Q1 of the latch circuit block is in a high-impedance state and keeps the logic level "1", so that the transistor P6 in the latch circuit block keeps the off state and the internal node Q2 of the latch circuit block keeps the logic level "0"; the low level of the internal node Q2 of the latch circuit block turns on the transistor P7 of the latch circuit block, thereby gradually charging the internal node Q3 of the latch circuit block; the high level of the internal node Q1 of the latch circuit block turns on the transistor N4 in the latch circuit block, thereby gradually discharging the internal node Q4 of the latch circuit block; finally, the internal node Q4 and the internal node Q3 of the latch circuit module are respectively restored to the original logic levels '0' and '1'; in the whole process, the internal node Q1 of the latch circuit block keeps the logic level "1", so that the transistor P9 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "0".
(5) When the drain of the transistor P10 in the output circuit block is impacted by energetic particles, the voltage of the output end OUT of the output circuit block is pulled high, and is inverted, so that the logic level is changed into '1'; because the latch circuit block is not affected by radiation, the internal node Q1 and the internal node Q3 of the latch circuit block keep the logic level "1", so that the transistor P9 and the transistor P10 in the output circuit block are turned off, the transistor N7 and the transistor N8 are turned on, the output end OUT of the output circuit block is gradually discharged, and finally the output end OUT of the output circuit block returns to the original logic level "0".
When the magnetic memory reading circuit based on DICE single event upset resistance works in a data information reading stage, if the logic levels of an internal node Q1 and an internal node Q3 of a latch circuit module are '0', the logic levels of an internal node Q2 and an internal node Q4 of the latch circuit module are '1', and the logic level of an output end OUT of an output circuit module is '1', the drain electrode of a transistor N2, the drain electrode of a transistor N4, the drain electrode of a transistor P5, the drain electrode of a transistor P7 and the drain electrode of the transistor N7 in the output circuit module in a reverse bias state, and the internal node Q1, the internal node Q2, the internal node Q3, the internal node Q4 and the output end OUT of the output circuit module are radiation sensitive nodes; in this case, the recovery process after each sensitive node is turned over by the ion radiation is as follows:
(1) when the drain of the transistor P5 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q1 of the latch circuit block is pulled high, and is inverted, so that the logic level becomes "1", thereby causing the transistor P6 in the latch circuit block to be turned off and the transistor N4 to be turned on; after the transistor N4 in the latch circuit block is turned on, the logic level of the internal node Q4 of the latch circuit block is pulled low; after the transistor P6 in the latch circuit block is turned off, the internal node Q2 of the latch circuit block is in a high-impedance state and keeps the logic level "1", so that the transistor P7 in the latch circuit block keeps the off state and the internal node Q3 of the latch circuit block keeps the logic level "0"; the low level of the internal node Q3 of the latch circuit block turns on the transistor P8 of the latch circuit block, thereby gradually charging the internal node Q4 of the latch circuit block; the high level of the internal node Q2 of the latch circuit block turns on the transistor N1 in the latch circuit block, thereby gradually discharging the internal node Q1 of the latch circuit block; finally, the internal node Q1 and the internal node Q4 of the latch circuit module are respectively restored to the original logic levels '0' and '1'; in the whole process, the internal node Q3 of the latch circuit block keeps the logic level "0", so that the transistor N7 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "1".
(2) When the drain of the transistor N2 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q2 of the latch circuit block is pulled low, and is inverted, so that the logic level becomes "0", thereby causing the transistor N1 in the latch circuit block to be turned off and the transistor P7 to be turned on; after the transistor P7 in the latch circuit block is turned on, the logic level of the internal node Q3 of the latch circuit block is pulled high; after the transistor N1 in the latch circuit block is turned off, the internal node Q1 of the latch circuit block is in a high-impedance state, and keeps the logic level "0", thereby causing the transistor N4 in the latch circuit block to keep the off state, and the internal node Q4 of the latch circuit block to keep the logic level "1"; the high level of the internal node Q4 of the latch circuit block turns on the transistor N3 of the latch circuit block, thereby gradually discharging the internal node Q3 of the latch circuit block; the low level of the internal node Q1 of the latch circuit block turns on the transistor P6 of the latch circuit block, thereby gradually charging the internal node Q2 of the latch circuit block; finally, the internal node Q2 and the internal node Q3 of the latch circuit module are respectively restored to the original logic levels '1' and '0'; in the whole process, the internal node Q1 of the latch circuit block keeps the logic level "0", so that the transistor N8 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "1".
(3) When the drain of the transistor P7 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q3 of the latch circuit block is pulled high, and is inverted, so that the logic level becomes "1", thereby causing the transistor P8 in the latch circuit block to be turned off and the transistor N2 to be turned on; after the transistor N2 in the latch circuit block is turned on, the logic level of the internal node Q2 of the latch circuit block is pulled low; after the transistor P8 in the latch circuit block is turned off, the internal node Q4 of the latch circuit block is in a high-impedance state and keeps the logic level "1", so that the transistor P5 in the latch circuit block keeps the off state and the internal node Q1 of the latch circuit block keeps the logic level "0"; the low level of the internal node Q1 of the latch circuit block turns on the transistor P6 of the latch circuit block, thereby gradually charging the internal node Q2 of the latch circuit block; the high level of the internal node Q4 of the latch circuit block turns on the transistor N3 in the latch circuit block, thereby gradually discharging the internal node Q3 of the latch circuit block; finally, the internal node Q3 and the internal node Q2 of the latch circuit module are respectively restored to the original logic levels '0' and '1'; in the whole process, the internal node Q1 of the latch circuit block keeps the logic level "0", so that the transistor N8 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "1".
(4) When the drain of the transistor N4 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q4 of the latch circuit block is pulled low, and is inverted, so that the logic level becomes "0", thereby causing the transistor N3 in the latch circuit block to be turned off and the transistor P5 to be turned on; after the transistor P5 in the latch circuit block is turned on, the logic level of the internal node Q1 of the latch circuit block is pulled high; after the transistor N3 in the latch circuit block is turned off, the internal node Q3 of the latch circuit block is in a high-impedance state, and keeps the logic level "0", thereby causing the transistor N2 in the latch circuit block to keep the off state, and the internal node Q2 of the latch circuit block to keep the logic level "1"; the high level of the internal node Q2 of the latch circuit block turns on the transistor N1 of the latch circuit block, thereby gradually discharging the internal node Q1 of the latch circuit block; the low level of the internal node Q3 of the latch circuit block turns on the transistor P8 of the latch circuit block, thereby gradually charging the internal node Q4 of the latch circuit block; finally, the internal node Q4 and the internal node Q1 of the latch circuit module are respectively restored to the original logic levels '1' and '0'; in the whole process, the internal node Q3 of the latch circuit block keeps the logic level "0", so that the transistor N7 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "1".
(5) When the drain of the transistor N7 in the output circuit block is impacted by high-energy particles, the voltage of the output end OUT of the output circuit block is pulled low, and is inverted, so that the logic level is changed into '0'; because the latch circuit block is not affected by radiation, the internal node Q1 and the internal node Q3 of the latch circuit block keep the logic level "0", so that the transistor P9 and the transistor P10 in the output circuit block are turned on, the transistor N7 and the transistor N8 are turned off, the output end OUT of the output circuit block is gradually charged, and finally the output end OUT of the output circuit block returns to the original logic level "1".
According to the technical scheme, the magnetic memory reading circuit based on DICE and resistant to single event upset can achieve the data information reading function of high speed and low power consumption, and has the capability of resisting single event upset in the data information reading process. In addition, the invention can be realized by a commercial CMOS process with low cost and short design period, and does not need a complex special anti-radiation process with high cost and long design period.
Specifically, the DICE-based single event upset resistant magnetic memory reading circuit has the following beneficial effects:
1. due to the adoption of the latch circuit module, when one of the radiation sensitive nodes is subjected to ion radiation overturn, the original logic level can be restored, so that the function of single event upset resistance can be realized;
2. because the output circuit module is adopted, the output end of the output circuit module can restore to the original logic level after being overturned by the ion radiation, and the logic level can be kept unchanged after any radiation sensitive node in the latch circuit module is overturned by the ion radiation; thereby realizing the function of single event upset resistance;
3. the magnetic memory reading circuit based on DICE single event upset resistance not only can realize the data information reading function with high speed and low power consumption, but also has the single event upset resistance in the data information reading process;
4. the DICE-based single event upset resistant magnetic memory reading circuit can be realized by a commercial CMOS process with low cost and short design period, and does not need a complex special radiation resistant process with high cost and long design period.
Drawings
FIG. 1 is a schematic diagram of a magnetic tunnel junction structure;
FIG. 2 is a schematic diagram of a MRAM cell structure using the differential signal read circuit of the present invention;
FIG. 3 is a schematic diagram of a DICE-based anti-single event upset magnetic memory read circuit according to the present invention;
the reference numbers in fig. 1 to 3 are defined as:
0 is the magnetic memory read circuit based on DICE single event upset resistance of the invention;
1 is a precharge circuit block;
2 is a latch circuit block;
3 is a read circuit separation module;
4 is an output circuit module;
MTJ represents Magnetic Tunnel Junction, which is short for Magnetic Tunnel Junction;
RL represents the resistance value of the MTJ in the low resistance state;
RH represents a resistance value when the MTJ is in a high resistance state;
BL represents a Bit Line, which is the abbreviation of Bit-Line;
WL represents the Word Line, and is the abbreviation of Word-Line;
SL represents a Source Line, which is short for Source-Line;
the NMOS represents an N-type metal Oxide semiconductor and is short for N-Mental-Oxide-semiconductor;
PMOS represents P-type metal Oxide semiconductor, which is short for P-Mental-Oxide-semiconductor;
VDD denotes a supply voltage;
GND denotes a ground voltage;
PRE represents the precharge signal;
RE denotes a read enable signal.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
A Magnetic Tunnel Junction (MTJ) is composed of two ferromagnetic layers and a tunneling barrier layer sandwiched therebetween, as shown in fig. 1; the magnetization direction of one of the ferromagnetic layers is fixed, referred to as the fixed layer, and the magnetization direction of the other ferromagnetic layer is changeable, referred to as the free layer. Depending on the relative magnetization directions of the free and fixed layers, the MTJ may exhibit two different resistance states; that is, when the magnetization directions of the two are parallel, the MTJ exhibits a Low Resistance state (R)L) (ii) a When the magnetization directions of the two are antiparallel, the MTJ exhibits a High Resistance state (R)H)。
The magnetic random access memory storage unit of the magnetic memory reading circuit based on DICE single event upset resistance of the embodiment of the invention comprises 2 MTJ and 2 NMOS transistors, as shown in FIG. 2; 2 MTJs are defined as MTJ0 and MTJ1, respectively; 2 NMOS transistors are defined as N9 and N10, respectively; the free layer of MTJ0 and the free layer of MTJ1 are connected to bit line BL1 and bit line BL2, respectively, of the MRAM memory cell; the pinned layer of MTJ0 and the pinned layer of MTJ1 are connected to the drain of transistor N9 and the drain of transistor N10, respectively; the gate of the transistor N9 and the gate of the transistor N10 are both connected to the word line WL; the source of the transistor N9 and the source of the transistor N10 are both connected to a source line SL; the magnetic random access memory storage unit stores 1-bit data information by using 2 MTJs in complementary resistance states: when the resistance state of MTJ0 is RLAnd the resistance state of MTJ1 is RHWhen the data information is stored in the magnetic random access memory storage unit, the data information is 1; when the resistance state of MTJ0 is RHAnd the resistance state of MTJ1 is RLWhen the data information is stored in the magnetic random access memory storage unit, the data information is 0.
Specifically, the magnetic memory reading circuit based on DICE single event upset resistance in the embodiment of the present invention includes a pre-charge circuit module, a latch circuit module, a reading circuit separation module, and an output circuit module, as shown in FIG. 3.
The input end of the PRE-charging circuit module is connected with a PRE-charging signal PRE; the output terminal of the precharge circuit block is connected to the internal node Q1, the internal node Q2, the internal node Q3, and the internal node Q4 of the latch circuit block.
The output end of the latch circuit module is connected with the input end of the read circuit separation module.
The output end of the read circuit separation module is connected with the bit line BL1 and the bit line BL2 of the magnetic random access memory storage unit of the data information to be read.
The input end of the output circuit module is connected with the internal node Q1 and the internal node Q3 of the latch circuit module; the output end OUT of the output circuit module is the output end of the DICE-based single event upset resistant magnetic memory reading circuit.
The pre-charging circuit module comprises 4 PMOS transistors; 4 PMOS transistors are respectively defined as P1-P4; the source electrode of the transistor P1, the source electrode of the transistor P2, the source electrode of the transistor P3 and the source electrode of the transistor P4 are all connected with a power supply VDD(ii) a The gate of the transistor P1, the gate of the transistor P2, the gate of the transistor P3 and the gate of the transistor P4 are all connected with a precharge signal PRE; the drain of the transistor P1 is connected to the internal node Q1 of the latch circuit block; the drain of the transistor P2 is connected to the internal node Q2 of the latch circuit block; the drain of the transistor P3 is connected to the internal node Q3 of the latch circuit block; the drain of the transistor P4 is connected to the internal node Q4 of the latch circuit block.
The latch circuit module comprises 4 PMOS transistors and 4 NMOS transistors; 4 PMOS transistors are respectively defined as P5-P8; the 4 NMOS transistors are respectively defined as N1-N4; the source electrode of the transistor P5, the source electrode of the transistor P6, the source electrode of the transistor P7 and the source electrode of the transistor P8 are all connected with a power supply VDD(ii) a The drain of the transistor P5, the gate of the transistor P6, the gate of the transistor N4, and the crystalThe drain of the transistor N1 is connected, and the connection point is the internal node Q1 of the latch circuit module; the drain of the transistor P6 is connected with the gate of the transistor P7, the gate of the transistor N1 and the drain of the transistor N2, and the connection point is the internal node Q2 of the latch circuit module; the drain of the transistor P7 is connected with the gate of the transistor P8, the gate of the transistor N2 and the drain of the transistor N3, and the connection point is the internal node Q3 of the latch circuit module; the drain of the transistor P8 is connected with the gate of the transistor P5, the gate of the transistor N3 and the drain of the transistor N4, and the connection point is the internal node Q4 of the latch circuit module; the source of the transistor N1 is connected with the source of the transistor N3, and the connection point is the output end A of the latch circuit module; the source of the transistor N2 is connected to the source of the transistor N4, the connection point being the output B of the latch circuit block.
The reading circuit separation module comprises 2 NMOS transistors; 2 NMOS transistors are defined as N5 and N6, respectively; the drain electrode of the transistor N5 is connected with the output end A of the latch circuit module; the drain electrode of the transistor N6 is connected with the output end B of the latch circuit module; the gate of the transistor N5 and the gate of the transistor N6 are both connected with a read enable signal RE; the source of the transistor N5 is connected with the bit line BL1 of the magnetic random access memory storage unit of the data information to be read; the source of transistor N6 is connected to the bit line BL2 of the MRAM memory cell from which data information is to be read.
The output circuit module comprises 2 PMOS transistors and 2 NMOS transistors; 2 PMOS transistors are defined as P9 and P10, respectively; 2 NMOS transistors are defined as N7 and N8, respectively; the source of the transistor P9 is connected with a power supply VDD(ii) a The drain of the transistor P9 is connected to the source of the transistor P10; the drain electrode of the transistor P10 is connected with the drain electrode of the transistor N7, and the connection point is the output end OUT of the output circuit module; the source of the transistor N7 is connected to the drain of the transistor N8; the source of the transistor N8 is connected with the grounding voltage GND; the gate of the transistor P9 and the gate of the transistor N8 are both connected to the internal node Q1 of the latch circuit block; the gate of the transistor P10 and the gate of the transistor N7 are connected to the latch circuit moduleThe partial node Q3 is connected.
The working of the DICE-based single event upset resistant magnetic memory reading circuit provided by the embodiment of the invention is divided into two stages: one is a precharge phase; one is the data information reading phase. In these two phases, the word line WL of the mram cell to be read has a logic level "1" and the source line SL has a logic level "0".
When the magnetic memory reading circuit based on DICE single event upset resistance works in a PRE-charging stage, the logic levels of a PRE-charging signal PRE and a read enabling signal RE are both '0', a transistor P1, a transistor P2, a transistor P3 and a transistor P4 in a PRE-charging circuit module are all in a conducting state, a transistor N5 and a transistor N6 in a reading circuit separation module are all in a closing state, and the voltages of an internal node Q1, an internal node Q2, an internal node Q3 and an internal node Q4 of a latch circuit module are all PRE-charged to a supply voltage VDD。
When the magnetic memory reading circuit based on DICE single event upset resistance works in a data information reading stage, the logic levels of a PRE-charge signal PRE and a read enable signal RE are both '1', a transistor P1, a transistor P2, a transistor P3 and a transistor P4 in a PRE-charge circuit module are all in an off state, a transistor N5 and a transistor N6 in a reading circuit separation module are all in an on state, and the voltages of an internal node Q1, an internal node Q2, an internal node Q3 and an internal node Q4 of the latch circuit module depend on the resistance difference between an MTJ0 and an MTJ1 in a magnetic random access memory unit of data information to be read, which is respectively connected with an output end A and an output end B of the latch circuit module; if the resistance value of the MTJ0 in the magnetic random access memory cell of the to-be-read data information connected to the output terminal a of the latch circuit module is greater than the resistance value of the MTJ1 in the magnetic random access memory cell of the to-be-read data information connected to the output terminal B of the latch circuit module, the logic levels of the internal node Q2 and the internal node Q4 of the latch circuit module are both "0", the logic levels of the internal node Q1 and the internal node Q3 of the latch circuit module are both "1", and the logic level of the output terminal OUT of the output circuit module is "0", that is, the data information read by the magnetic memory read circuit based on DICE anti-single event upset is "0"; if the resistance value of the MTJ0 in the magnetic random access memory cell of the to-be-read data information connected to the output terminal a of the latch circuit module is smaller than the resistance value of the MTJ1 in the magnetic random access memory cell of the to-be-read data information connected to the output terminal B of the latch circuit module, the logic levels of the internal node Q2 and the internal node Q4 of the latch circuit module are both "1", the logic levels of the internal node Q1 and the internal node Q3 of the latch circuit module are both "0", and the logic level of the output terminal OUT of the output circuit module is "1", that is, the data information read by the magnetic memory read circuit based on DICE anti-single event upset is "1".
The two working phases are specified below:
when the magnetic memory reading circuit based on DICE single event upset resistance works in a data information reading stage, if the logic levels of an internal node Q1 and an internal node Q3 of a latch circuit module are '1', the logic levels of an internal node Q2 and an internal node Q4 of the latch circuit module are '0', and the logic level of an output end OUT of an output circuit module is '0', the drain electrode of a transistor P6, the drain electrode of a transistor P8, the drain electrode of a transistor N1, the drain electrode of a transistor N3 and the drain electrode of the transistor P10 in the output circuit module in a reverse bias state, and the internal node Q1, the internal node Q2, the internal node Q3, the internal node Q4 and the output end OUT of the output circuit module are radiation sensitive nodes; in this case, the recovery process after each sensitive node is turned over by the ion radiation is as follows:
(1) when the drain of the transistor N1 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q1 of the latch circuit block is pulled low, and is inverted, so that the logic level becomes "0", thereby causing the transistor N4 in the latch circuit block to be turned off and the transistor P6 to be turned on; after the transistor P6 in the latch circuit block is turned on, the logic level of the internal node Q2 of the latch circuit block is pulled high; after the transistor N4 in the latch circuit block is turned off, the internal node Q4 of the latch circuit block is in a high-impedance state, and keeps the logic level "0", thereby causing the transistor N3 in the latch circuit block to keep the off state, and the internal node Q3 of the latch circuit block to keep the logic level "1"; the high level of the internal node Q3 of the latch circuit block turns on the transistor N2 of the latch circuit block, thereby gradually discharging the internal node Q2 of the latch circuit block; the low level of the internal node Q4 of the latch circuit block turns on the transistor P5 of the latch circuit block, thereby gradually charging the internal node Q1 of the latch circuit block; finally, the internal node Q1 and the internal node Q2 of the latch circuit module are respectively restored to the original logic levels '1' and '0'; in the whole process, the internal node Q3 of the latch circuit block keeps the logic level "1", so that the transistor P10 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "0".
(2) When the drain of the transistor P6 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q2 of the latch circuit block is pulled high, and is inverted, so that the logic level becomes "1", thereby causing the transistor P7 in the latch circuit block to be turned off and the transistor N1 to be turned on; after the transistor N1 in the latch circuit block is turned on, the logic level of the internal node Q1 of the latch circuit block is pulled low; after the transistor P7 in the latch circuit block is turned off, the internal node Q3 of the latch circuit block is in a high-impedance state and keeps the logic level "1", so that the transistor P8 in the latch circuit block keeps the off state and the internal node Q4 of the latch circuit block keeps the logic level "0"; the low level of the internal node Q4 of the latch circuit block turns on the transistor P5 of the latch circuit block, thereby gradually charging the internal node Q1 of the latch circuit block; the high level of the internal node Q3 of the latch circuit block turns on the transistor N2 in the latch circuit block, thereby gradually discharging the internal node Q2 of the latch circuit block; finally, the internal node Q2 and the internal node Q1 of the latch circuit module are respectively restored to the original logic levels '0' and '1'; in the whole process, the internal node Q3 of the latch circuit block keeps the logic level "1", so that the transistor P10 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "0".
(3) When the drain of the transistor N3 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q3 of the latch circuit block is pulled low, and is inverted, so that the logic level becomes "0", thereby causing the transistor N2 in the latch circuit block to be turned off and the transistor P8 to be turned on; after the transistor P8 in the latch circuit block is turned on, the logic level of the internal node Q4 of the latch circuit block is pulled high; after the transistor N2 in the latch circuit block is turned off, the internal node Q2 of the latch circuit block is in a high-impedance state, and keeps the logic level "0", thereby causing the transistor N1 in the latch circuit block to keep the off state, and the internal node Q1 of the latch circuit block to keep the logic level "1"; the high level of the internal node Q1 of the latch circuit block turns on the transistor N4 of the latch circuit block, thereby gradually discharging the internal node Q4 of the latch circuit block; the low level of the internal node Q2 of the latch circuit block turns on the transistor P7 of the latch circuit block, thereby gradually charging the internal node Q3 of the latch circuit block; finally, the internal node Q3 and the internal node Q4 of the latch circuit module are respectively restored to the original logic levels '1' and '0'; in the whole process, the internal node Q1 of the latch circuit block keeps the logic level "1", so that the transistor P9 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "0".
(4) When the drain of the transistor P8 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q4 of the latch circuit block is pulled high, and is inverted, so that the logic level becomes "1", thereby causing the transistor P5 in the latch circuit block to be turned off and the transistor N3 to be turned on; after the transistor N3 in the latch circuit block is turned on, the logic level of the internal node Q3 of the latch circuit block is pulled low; after the transistor P5 in the latch circuit block is turned off, the internal node Q1 of the latch circuit block is in a high-impedance state and keeps the logic level "1", so that the transistor P6 in the latch circuit block keeps the off state and the internal node Q2 of the latch circuit block keeps the logic level "0"; the low level of the internal node Q2 of the latch circuit block turns on the transistor P7 of the latch circuit block, thereby gradually charging the internal node Q3 of the latch circuit block; the high level of the internal node Q1 of the latch circuit block turns on the transistor N4 in the latch circuit block, thereby gradually discharging the internal node Q4 of the latch circuit block; finally, the internal node Q4 and the internal node Q3 of the latch circuit module are respectively restored to the original logic levels '0' and '1'; in the whole process, the internal node Q1 of the latch circuit block keeps the logic level "1", so that the transistor P9 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "0".
(5) When the drain of the transistor P10 in the output circuit block is impacted by energetic particles, the voltage of the output end OUT of the output circuit block is pulled high, and is inverted, so that the logic level is changed into '1'; because the latch circuit block is not affected by radiation, the internal node Q1 and the internal node Q3 of the latch circuit block keep the logic level "1", so that the transistor P9 and the transistor P10 in the output circuit block are turned off, the transistor N7 and the transistor N8 are turned on, the output end OUT of the output circuit block is gradually discharged, and finally the output end OUT of the output circuit block returns to the original logic level "0".
When the magnetic memory reading circuit based on DICE single event upset resistance works in a data information reading stage, if the logic levels of an internal node Q1 and an internal node Q3 of a latch circuit module are '0', the logic levels of an internal node Q2 and an internal node Q4 of the latch circuit module are '1', and the logic level of an output end OUT of an output circuit module is '1', the drain electrode of a transistor N2, the drain electrode of a transistor N4, the drain electrode of a transistor P5, the drain electrode of a transistor P7 and the drain electrode of the transistor N7 in the output circuit module in a reverse bias state, and the internal node Q1, the internal node Q2, the internal node Q3, the internal node Q4 and the output end OUT of the output circuit module are radiation sensitive nodes; in this case, the recovery process after each sensitive node is turned over by the ion radiation is as follows:
(1) when the drain of the transistor P5 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q1 of the latch circuit block is pulled high, and is inverted, so that the logic level becomes "1", thereby causing the transistor P6 in the latch circuit block to be turned off and the transistor N4 to be turned on; after the transistor N4 in the latch circuit block is turned on, the logic level of the internal node Q4 of the latch circuit block is pulled low; after the transistor P6 in the latch circuit block is turned off, the internal node Q2 of the latch circuit block is in a high-impedance state and keeps the logic level "1", so that the transistor P7 in the latch circuit block keeps the off state and the internal node Q3 of the latch circuit block keeps the logic level "0"; the low level of the internal node Q3 of the latch circuit block turns on the transistor P8 of the latch circuit block, thereby gradually charging the internal node Q4 of the latch circuit block; the high level of the internal node Q2 of the latch circuit block turns on the transistor N1 in the latch circuit block, thereby gradually discharging the internal node Q1 of the latch circuit block; finally, the internal node Q1 and the internal node Q4 of the latch circuit module are respectively restored to the original logic levels '0' and '1'; in the whole process, the internal node Q3 of the latch circuit block keeps the logic level "0", so that the transistor N7 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "1".
(2) When the drain of the transistor N2 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q2 of the latch circuit block is pulled low, and is inverted, so that the logic level becomes "0", thereby causing the transistor N1 in the latch circuit block to be turned off and the transistor P7 to be turned on; after the transistor P7 in the latch circuit block is turned on, the logic level of the internal node Q3 of the latch circuit block is pulled high; after the transistor N1 in the latch circuit block is turned off, the internal node Q1 of the latch circuit block is in a high-impedance state, and keeps the logic level "0", thereby causing the transistor N4 in the latch circuit block to keep the off state, and the internal node Q4 of the latch circuit block to keep the logic level "1"; the high level of the internal node Q4 of the latch circuit block turns on the transistor N3 of the latch circuit block, thereby gradually discharging the internal node Q3 of the latch circuit block; the low level of the internal node Q1 of the latch circuit block turns on the transistor P6 of the latch circuit block, thereby gradually charging the internal node Q2 of the latch circuit block; finally, the internal node Q2 and the internal node Q3 of the latch circuit module are respectively restored to the original logic levels '1' and '0'; in the whole process, the internal node Q1 of the latch circuit block keeps the logic level "0", so that the transistor N8 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "1".
(3) When the drain of the transistor P7 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q3 of the latch circuit block is pulled high, and is inverted, so that the logic level becomes "1", thereby causing the transistor P8 in the latch circuit block to be turned off and the transistor N2 to be turned on; after the transistor N2 in the latch circuit block is turned on, the logic level of the internal node Q2 of the latch circuit block is pulled low; after the transistor P8 in the latch circuit block is turned off, the internal node Q4 of the latch circuit block is in a high-impedance state and keeps the logic level "1", so that the transistor P5 in the latch circuit block keeps the off state and the internal node Q1 of the latch circuit block keeps the logic level "0"; the low level of the internal node Q1 of the latch circuit block turns on the transistor P6 of the latch circuit block, thereby gradually charging the internal node Q2 of the latch circuit block; the high level of the internal node Q4 of the latch circuit block turns on the transistor N3 in the latch circuit block, thereby gradually discharging the internal node Q3 of the latch circuit block; finally, the internal node Q3 and the internal node Q2 of the latch circuit module are respectively restored to the original logic levels '0' and '1'; in the whole process, the internal node Q1 of the latch circuit block keeps the logic level "0", so that the transistor N8 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "1".
(4) When the drain of the transistor N4 in the latch circuit block is hit by energetic particles, the logic level of the internal node Q4 of the latch circuit block is pulled low, and is inverted, so that the logic level becomes "0", thereby causing the transistor N3 in the latch circuit block to be turned off and the transistor P5 to be turned on; after the transistor P5 in the latch circuit block is turned on, the logic level of the internal node Q1 of the latch circuit block is pulled high; after the transistor N3 in the latch circuit block is turned off, the internal node Q3 of the latch circuit block is in a high-impedance state, and keeps the logic level "0", thereby causing the transistor N2 in the latch circuit block to keep the off state, and the internal node Q2 of the latch circuit block to keep the logic level "1"; the high level of the internal node Q2 of the latch circuit block turns on the transistor N1 of the latch circuit block, thereby gradually discharging the internal node Q1 of the latch circuit block; the low level of the internal node Q3 of the latch circuit block turns on the transistor P8 of the latch circuit block, thereby gradually charging the internal node Q4 of the latch circuit block; finally, the internal node Q4 and the internal node Q1 of the latch circuit module are respectively restored to the original logic levels '1' and '0'; in the whole process, the internal node Q3 of the latch circuit block keeps the logic level "0", so that the transistor N7 in the output circuit block keeps the off state, and the output end OUT of the output circuit block keeps the logic level "1".
(5) When the drain of the transistor N7 in the output circuit block is impacted by high-energy particles, the voltage of the output end OUT of the output circuit block is pulled low, and is inverted, so that the logic level is changed into '0'; because the latch circuit block is not affected by radiation, the internal node Q1 and the internal node Q3 of the latch circuit block keep the logic level "0", so that the transistor P9 and the transistor P10 in the output circuit block are turned on, the transistor N7 and the transistor N8 are turned off, the output end OUT of the output circuit block is gradually charged, and finally the output end OUT of the output circuit block returns to the original logic level "1".
In summary, the magnetic memory read circuit based on DICE single event upset resistance of the present invention has the following characteristics:
1. due to the adoption of the latch circuit module, when one of the radiation sensitive nodes is subjected to ion radiation overturn, the original logic level can be restored, so that the function of single event upset resistance can be realized;
2. because the output circuit module is adopted, the output end of the output circuit module can restore to the original logic level after being overturned by the ion radiation, and the logic level can be kept unchanged after any radiation sensitive node in the latch circuit module is overturned by the ion radiation; thereby realizing the function of single event upset resistance;
3. the magnetic memory reading circuit based on DICE single event upset resistance not only can realize the data information reading function with high speed and low power consumption, but also has the single event upset resistance in the data information reading process;
4. the DICE-based single event upset resistant magnetic memory reading circuit can be realized by a commercial CMOS process with low cost and short design period, and does not need a complex special radiation resistant process with high cost and long design period.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (6)

1. A DICE-based single event upset resistant magnetic memory reading circuit is characterized in that:
the circuit comprises a pre-charging circuit module, a latch circuit module, a reading circuit separation module and an output circuit module;
the input end of the PRE-charging circuit module is connected with a PRE-charging signal PRE; the output end of the pre-charge circuit module is connected with the internal node Q1, the internal node Q2, the internal node Q3 and the internal node Q4 of the latch circuit module;
the output end of the latch circuit module is connected with the input end of the read circuit separation module;
the output end of the read circuit separation module is connected with a bit line BL1 and a bit line BL2 of a magnetic random access memory storage unit of data information to be read;
the input end of the output circuit module is connected with the internal node Q1 and the internal node Q3 of the latch circuit module; and the output end OUT of the output circuit module is the output end of the magnetic memory reading circuit based on DICE single event upset resistance.
2. The DICE single event upset resistant magnetic memory read circuit of claim 1, wherein: the pre-charge circuit module comprises 4 PMOS transistors;
4 PMOS transistors are respectively defined as P1-P4; the source electrode of the transistor P1, the source electrode of the transistor P2, the source electrode of the transistor P3 and the source electrode of the transistor P4 are all connected with a power supply VDD(ii) a The gate of the transistor P1, the gate of the transistor P2, the gate of the transistor P3 and the gate of the transistor P4 are all connected with a precharge signal PRE; the drain of the transistor P1 is connected to the internal node Q1 of the latch circuit block; the drain of the transistor P2 is connected to the internal node Q2 of the latch circuit block; the drain of the transistor P3 is connected to the internal node Q3 of the latch circuit block; the drain of transistor P4 is connected to the latch circuit block internal node Q4.
3. The DICE single event upset resistant magnetic memory read circuit of claim 2, wherein:
the latch circuit module comprises 4 PMOS transistors and 4 NMOS transistors; 4 PMOS transistors are respectively defined as P5-P8; the 4 NMOS transistors are respectively defined as N1-N4; the source electrode of the transistor P5, the source electrode of the transistor P6, the source electrode of the transistor P7 and the source electrode of the transistor P8 are all connected with a power supply VDD(ii) a The drain of the transistor P5 is connected to the gate of the transistor P6, the gate of the transistor N4 and the drain of the transistor N1, at the connection point inside the latch circuit blockNode Q1; the drain electrode of the transistor P6 is connected with the gate electrode of the transistor P7, the gate electrode of the transistor N1 and the drain electrode of the transistor N2, and the connection point is an internal node Q2 of the latch circuit module; the drain electrode of the transistor P7 is connected with the gate electrode of the transistor P8, the gate electrode of the transistor N2 and the drain electrode of the transistor N3, and the connection point is an internal node Q3 of the latch circuit module; the drain electrode of the transistor P8 is connected with the gate electrode of the transistor P5, the gate electrode of the transistor N3 and the drain electrode of the transistor N4, and the connection point is an internal node Q4 of the latch circuit module; the source of the transistor N1 is connected with the source of the transistor N3, and the connection point is the output end A of the latch circuit module; the source of the transistor N2 is connected to the source of the transistor N4, and the connection point is the output end B of the latch circuit module.
4. The DICE single event upset resistant magnetic memory read circuit of claim 3, wherein:
the reading circuit separation module comprises 2 NMOS transistors; 2 NMOS transistors are defined as N5 and N6, respectively; the drain electrode of the transistor N5 is connected with the output end A of the latch circuit module; the drain electrode of the transistor N6 is connected with the output end B of the latch circuit module; the gate of the transistor N5 and the gate of the transistor N6 are both connected with a read enable signal RE; the source of the transistor N5 is connected with the bit line BL1 of the magnetic random access memory storage unit of the data information to be read; the source of transistor N6 is connected to the bit line BL2 of the MRAM memory cell from which data information is to be read.
5. The DICE single event upset resistant magnetic memory read circuit of claim 4, wherein:
the output circuit module comprises 2 PMOS transistors and 2 NMOS transistors; 2 PMOS transistors are defined as P9 and P10, respectively; 2 NMOS transistors are defined as N7 and N8, respectively; the source of the transistor P9 is connected with a power supply VDD(ii) a The drain of the transistor P9 is connected to the source of the transistor P10; the drain electrode of the transistor P10 is connected with the drain electrode of the transistor N7, and the connection point is the output end OUT of the output circuit module; transistor with a metal gate electrodeThe source of the N7 is connected with the drain of the transistor N8; the source of the transistor N8 is connected with the grounding voltage GND; the gate of the transistor P9 and the gate of the transistor N8 are both connected to the internal node Q1 of the latch circuit block; the gate of the transistor P10 and the gate of the transistor N7 are both connected to the internal node Q3 of the latch circuit block.
6. The DICE single event upset resistant magnetic memory read circuit of claim 5, wherein:
the magnetic random access memory storage unit of the data information to be read comprises 2 magnetic tunnel junctions and 2 NMOS transistors; 2 MTJs are defined as MTJ0 and MTJ1, respectively; 2 NMOS transistors are defined as N9 and N10, respectively; the free layer of MTJ0 and the free layer of MTJ1 are connected to bit line BL1 and bit line BL2, respectively, of the MRAM memory cell where data information is to be read; the pinned layer of MTJ0 and the pinned layer of MTJ1 are connected to the drain of transistor N9 and the drain of transistor N10, respectively; the gate of the transistor N9 and the gate of the transistor N10 are both connected to the word line WL; the source of the transistor N9 and the source of the transistor N10 are both connected to a source line SL; the magnetic random access memory storage unit of the data information to be read stores 1-bit data information by utilizing 2 MTJs in complementary resistance states: when the resistance state of MTJ0 is RLAnd the resistance state of MTJ1 is RHWhen the data information is read, the data information stored in the magnetic random access memory storage unit of the data information to be read is 1; when the resistance state of MTJ0 is RHAnd the resistance state of MTJ1 is RLAnd when the data information is read, the data information stored in the magnetic random access memory storage unit of the data information to be read is '0'.
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