CN112041930A

CN112041930A - Operation method for phase change memory cell and related device

Info

Publication number: CN112041930A
Application number: CN201880092772.9A
Authority: CN
Inventors: 何强; 王涛; 董广超; 李欢
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-11-09
Filing date: 2018-11-09
Publication date: 2020-12-04
Also published as: WO2020093387A1

Abstract

A method of operating a phase change memory cell and related apparatus, the phase change memory cell comprising a first electrode (101), a phase change layer (103), and a second electrode (102), the second electrode (102) being grounded, the method comprising: sequentially applying a first pulse and a second pulse to the first electrode (101), wherein the first pulse and the second pulse are respectively used for adjusting the resistance state of the phase change memory cell; wherein the polarity of the first pulse is opposite to the polarity of the second pulse. The method can reduce the resistance value drift of the phase change memory unit, and further improve the data retention capacity of the phase change memory unit.

Description

Operation method for phase change memory cell and related device

Technical Field

The present disclosure relates to the field of memory operations, and more particularly, to a method and apparatus for operating a phase change memory cell.

Background

The phase change memory is a nonvolatile memory and comprises a plurality of phase change memory cells, the resistance value of each phase change memory cell can be changed by changing the state of a phase change material, and the writing, erasing and reading operations of data can be realized by distinguishing the resistance value of each phase change memory cell. The reading operation of the data is realized by measuring the resistance of the phase change memory cell, and the pulse strength applied to the phase change memory cell is very weak and the time is short, so that the phase change of the phase change material is not caused. Both data write and erase operations require a change in the phase of the phase change material to change the resistance of the phase change memory cell. With the increase of erasing times, the resistance of the phase change memory cell will gradually increase, which causes the problem of resistance drift, and the resistance drift will cause data reading error.

Disclosure of Invention

The embodiment of the application provides an operation method and a related device for a phase change memory cell, so as to reduce the occurrence of resistance drift of the phase change memory cell and further improve the data retention capability of the phase change memory cell.

In a first aspect, an embodiment of the present application provides a method for operating a phase change memory cell, where the phase change memory cell includes a first electrode, a phase change layer, and a second electrode, and the second electrode is grounded, and the method includes:

sequentially applying a first pulse and a second pulse to the first electrode, wherein the first pulse and the second pulse can respectively adjust the resistance state of the phase change memory cell; wherein the polarity of the first pulse is opposite to the polarity of the second pulse.

In the first aspect, because the polarities of the first pulse and the second pulse are opposite, each element in the phase change layer cannot be excessively accumulated towards a fixed direction, the accumulation degree of each element on the upper electrode or the lower electrode can be reduced even if the erasing times are continuously increased, and meanwhile, the accumulation degree of the defect state on the upper electrode or the lower electrode of the phase change layer is lower, so that the resistance value drift degree of the phase change memory cell is reduced, and the data retention capability is improved.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the first pulse may be a positive-going pulse, and the second pulse may be a negative-going pulse. Therefore, the polarities of the first pulse and the second pulse are opposite, so that the resistance value drift degree of the phase change memory unit can be reduced, and the data retention capacity is improved.

With reference to the first aspect, in a second possible implementation manner of the first aspect, the first pulse may be a negative-going pulse, and the second pulse may be a positive-going pulse. Therefore, the polarities of the first pulse and the second pulse are opposite, so that the resistance value drift degree of the phase change memory unit can be reduced, and the data retention capacity is improved.

With reference to the first aspect and the foregoing various possible implementations, in a third possible implementation of the first aspect, when the first pulse is a plurality of pulses, amplitudes of the plurality of pulses are different and pulse widths are different, or amplitudes of the plurality of pulses are the same and pulse widths are different, or amplitudes of the plurality of pulses are different and pulse widths are the same, or amplitudes of the plurality of pulses are the same and pulse widths are the same. In the embodiment of the present application, the amplitudes and pulse widths of the plurality of pulses of the first pulse are not limited.

When the second pulse is a plurality of pulses, the plurality of pulses have different amplitudes and different pulse widths, or the plurality of pulses have the same amplitude and different pulse widths, or the plurality of pulses have different amplitudes and the same pulse widths, or the plurality of pulses have the same amplitude and the same pulse width. In the embodiment of the present application, the amplitudes and pulse widths of the plurality of pulses of the second pulse are not limited.

With reference to the first aspect and the various possible implementation manners described above, in a fourth possible implementation manner of the first aspect, the resistance state of the phase change memory cell includes a high resistance state and a low resistance state; the resistance value of the phase change unit corresponding to the high resistance state is larger than that of the phase change unit corresponding to the low resistance state. Binary storage of the phase change memory cell can be realized through the two resistance values.

With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the resistance state of the phase change memory cell includes at least one intermediate resistance state in addition to the high resistance state and the low resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is smaller than that of the phase change unit corresponding to the high resistance state, and the resistance value of the phase change unit corresponding to the intermediate resistance state is larger than that of the phase change unit corresponding to the low resistance state. The multi-value storage of the phase change memory cell can be realized through the three or more resistance value states.

With reference to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the first pulse is used to adjust a resistance state of the phase change memory cell to a first state; the second pulse is used for adjusting the resistance state of the phase change memory cell from the first state to the second state. Optionally, before the operation of applying the pulse to the phase change memory cell is performed to change the resistance state, the current resistance of the phase change memory cell may be detected, and if the current resistance falls within the resistance range corresponding to the required resistance state, the pulse does not need to be applied to the phase change memory cell, so that the efficiency of changing the resistance state may be improved.

With reference to the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner of the first aspect, it is assumed that the first pulse is one pulse and the second pulse is one pulse; and under the condition that the first state is a low-resistance state and the second state is a first target resistance state, the amplitude of the first pulse is smaller than that of the second pulse, and the pulse width of the first pulse is larger than that of the second pulse, wherein the first target resistance state is any one of a high-resistance state and at least one intermediate resistance state. And under the condition that the first state is a high impedance state and the second state is a second target impedance state, the amplitude of the first pulse is larger than that of the second pulse, and the pulse width of the first pulse is smaller than that of the second pulse, wherein the second target impedance state is any one of a low impedance state and at least one intermediate impedance state.

With reference to the fifth possible implementation manner or the sixth possible implementation manner of the first aspect, in an eighth possible implementation manner of the first aspect, the first pulse is M pulses, and the second pulse is N pulses; the method further comprises the following steps: if the resistance value corresponding to the phase change memory cell read after applying the M pulses is in the resistance value range corresponding to the first state, determining to adjust the resistance value state of the phase change memory cell to the first state, wherein M is a positive integer; and if the resistance value corresponding to the phase change memory cell read after applying the N pulses is in the resistance value range corresponding to the second state, determining to adjust the resistance value state of the phase change memory cell to the second state, wherein N is a positive integer. In this manner, the resistance state of the phase change memory cell can be adjusted and determined.

With reference to the first aspect and the various possible implementation manners described above, in a ninth possible implementation manner of the first aspect, the first electrode may be an upper electrode, and the second electrode may be a lower electrode; in this case, the first pulse and the second pulse are sequentially applied to the upper electrode.

With reference to the first aspect and the various possible implementation manners described above, in a ninth possible implementation manner of the first aspect, the first electrode may be a lower electrode, and the second electrode may be an upper electrode. In this case, the first pulse and the second pulse are sequentially applied to the lower electrode.

In a second aspect, an embodiment of the present application provides an operating device for operating a phase change memory cell, where the phase change memory cell includes a first electrode, a phase change layer, and a second electrode, and the second electrode is grounded, including: the pulse applying module is used for sequentially applying a first pulse and a second pulse to the first electrode, and the first pulse and the second pulse are respectively used for adjusting the resistance state of the phase change memory cell; wherein the polarity of the first pulse is opposite to the polarity of the second pulse.

In the second aspect, because the polarities of the first pulse and the second pulse are opposite, each element in the phase change layer cannot be excessively accumulated towards a fixed direction, the accumulation degree of each element on the upper electrode or the lower electrode can be reduced even if the erasing times are continuously increased, and meanwhile, the accumulation degree of the defect state on the upper electrode or the lower electrode of the phase change layer is lower, so that the resistance value drift degree of the phase change memory cell is reduced, and the data retention capability is improved.

Optionally, the operating device may also implement some or all of the possible implementations of the first aspect.

In a third aspect, an embodiment of the present application provides a chip, where the chip includes a controller and a memory, where the memory is used to store a computer program, the controller is used to call and run the computer program from the memory, and the computer program is used to execute part or all of possible implementation manners of the first aspect.

In a fourth aspect, an embodiment of the present application provides a terminal device, where the terminal device includes a processor, a memory, and at least one phase change memory cell, where the phase change memory cell includes a first electrode, a phase change layer, and a second electrode, the second electrode is grounded, the memory is used to store a computer program, the processor is used to call and run the computer program from the memory, and the processor is used to execute part or all of possible implementations of the first aspect.

In a fifth aspect, an embodiment of the present application provides a computer program product, where the computer program product includes: computer program code which, when run on a computer, causes the computer to perform some or all of the possible implementations of the first aspect.

In a sixth aspect, embodiments of the present application provide a computer-readable medium storing program code, which, when run on a computer, causes the computer to perform some or all of the possible implementations of the first aspect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be described below.

FIG. 1 is a schematic diagram of a possible phase change memory cell according to an embodiment of the present disclosure;

FIG. 2a is a diagram illustrating an example of a pulse application method according to an embodiment of the present application;

FIG. 2b is a diagram illustrating another example of pulse application according to an embodiment of the present application;

FIG. 3 provides an exemplary illustration of a pulse form for an embodiment of the present application;

FIG. 4 provides an exemplary illustration of yet another pulse form for an embodiment of the present application;

FIG. 5 provides an exemplary illustration of yet another pulse form for an embodiment of the present application;

FIG. 6 provides an exemplary illustration of yet another pulse form for an embodiment of the present application;

FIG. 7a is an exemplary diagram of yet another pulse form provided by an embodiment of the present application;

FIG. 7b is an exemplary diagram of yet another pulse form provided by an embodiment of the present application;

FIG. 7c is an exemplary diagram of yet another pulse form provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of an operating device according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another operating device provided in the embodiments of the present application;

fig. 10 is a schematic structural diagram of a terminal device according to an embodiment of the present application.

Detailed Description

The following description will be made with reference to the drawings in the embodiments of the present application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a possible phase change memory cell according to an embodiment of the present disclosure. As shown in fig. 1, the phase change memory cell includes an upper electrode 101, a lower electrode 102, and a phase change layer 103.

Wherein the phase change layer 103 comprises a phase change material that is reversibly changeable between a crystalline state and an amorphous state, the difference in resistance of the two states making it useful for storing information. The same substance may exist in states such as solid, liquid, gas, condensate and plasma, all referred to as phases. Phase change memories operate using the difference in resistance of the phase change material between different phases. For example, sulfur-based compounds can be used asBeing a phase change material, e.g. Ge₂Sb ₂Te ₅。

In the amorphous state, the phase change material has short-range atomic energy levels and a low free electron density, so that it has a high resistivity. In the crystalline state, the phase change material has a long distance of atomic energy levels and a high free electron density, thereby having a low resistivity.

In a possible implementation, a pulsed voltage source or a pulsed current source is connected to the phase change memory cell, and the phase change material is caused to change between the crystalline state and the amorphous state upon excitation by an electrical pulse generated by the pulsed voltage source or the pulsed current source. Generally, the resistance value of the phase-change material in the crystalline state is smaller than that in the amorphous state, and the writing, erasing and reading operations of data can be realized by distinguishing the resistance value of the phase-change material.

For example, the pulse voltage source is connected to the phase change memory cell in such a way that the pulse voltage source is connected to the upper electrode 101 and the lower electrode 102 is grounded. If the resistance value of the phase change memory unit is detected to be in the resistance value range corresponding to the crystalline state, the writing operation can be executed on the phase change memory unit, the writing operation is to apply a short and strong voltage pulse to the upper electrode through a pulse voltage source, the local temperature of the phase change layer 103 rises and exceeds the melting point temperature of the phase change material, and after the voltage pulse is finished, the local melting point of the phase change material is rapidly cooled at a higher speed, so that the local amorphous state of the phase change layer 103 is realized, and the phase change memory unit is adjusted to be in the amorphous state. If the resistance value of the phase change memory unit is detected to be in the resistance value range corresponding to the amorphous state, the phase change memory unit can be erased, a long and medium voltage pulse is applied to the upper electrode through a pulse voltage source, so that the local temperature of the phase change layer 103 is raised to be higher than the crystallization temperature and lower than the melting point temperature, the amorphous region of the phase change layer 103 is crystallized, and the crystalline state is adjusted. The reading operation of the data is realized by measuring the resistance value of the phase-change material, and the pulse strength applied to the phase-change memory cell is weak and short in time, so that the phase-change material is not changed.

In practice, it is often right toUnipolar pulses are applied to the electrodes to achieve data writing, erasing and reading operations, and with the increase of erasing times, the resistance value of the phase change memory unit gradually increases, namely the resistance value drifts. The reason is that: phase change material with Ge₂Sb ₂Te ₅For example, Ge element, Sb element, and Te element inside the phase change memory cell migrate to different degrees along the direction of the electric field, wherein the Ge element and the Sb element migrate to the cathode and accumulate, the Te element migrates to the anode and accumulates, and the accumulated elements form a defect state. With reference to the schematic structure of the phase-change memory cell shown in fig. 1, if the lower electrode 102 is grounded and a positive voltage pulse is applied to the upper electrode by a pulse voltage source, such that the upper electrode is an anode and the lower electrode is a cathode, as the number of times of erasing and writing increases, Ge and Sb elements accumulate at the interface between the lower electrode and the phase-change layer, and Te elements accumulate at the interface between the upper electrode and the phase-change layer. With the increase of the erasing times, all elements in the phase change layer can be excessively accumulated towards one direction, the accumulation degree of a defect state on an upper electrode or a lower electrode of the phase change layer is higher, and then the resistance value of the phase change memory unit can be greatly increased, namely resistance value drift occurs, the writing, erasing and reading operations are realized by distinguishing the resistance value, the accuracy of data reading can be influenced after the resistance value drift occurs, and the data retention capability is reduced.

The embodiment of the application can apply the first pulse and the second pulse with opposite polarities to the upper electrode in sequence under the condition that the lower electrode is grounded, the resistance state of the phase change memory unit can be adjusted through the first pulse or the second pulse, in addition, due to the fact that the polarities of the first pulse and the second pulse are opposite, elements in the phase change layer cannot be excessively accumulated towards one direction, the accumulation degree of the elements on the upper electrode or the lower electrode can be reduced even the erasing times are continuously increased, meanwhile, the accumulation degree of the defect states on the upper electrode or the lower electrode of the phase change layer is lower, the resistance drift degree of the phase change memory unit is further reduced, and the data retention capacity is improved.

In the embodiment of the present application, the amplitude and width of the pulse are determined by the factors of the phase change material, the medium, the device structure, etc., and the amplitude and width of the pulse are different according to the factors.

It should be understood that the schematic structural diagram shown in fig. 1 is a possible phase change memory cell applicable to the present application, and the present application does not limit the structure of other phase change memory cells including an upper electrode, a lower electrode, and a phase change layer.

Referring to fig. 2a and fig. 2b, schematic diagrams of possible phase change memory cells shown in fig. 1 are respectively provided as examples of pulse application methods according to embodiments of the present application. The exemplary diagram includes a pulsed signal source 200 and a phase change memory cell. The phase change memory cell of the embodiment of the application comprises a first electrode, a second electrode and a phase change layer.

In one possible implementation, the first electrode is an upper electrode 101 and the second electrode is a lower electrode 102. As shown in fig. 2a, the lower electrode 102 of the phase change memory cell is grounded, and a pulse signal source 200 applies a pulse to the upper electrode 101 of the phase change memory cell.

In yet another possible implementation, the first electrode is the lower electrode 103 and the second electrode is the upper electrode 104. As shown in fig. 2b, the upper electrode 103 of the phase change memory cell is grounded, and a pulse is applied to the lower electrode 104 of the phase change memory cell by the pulse signal source 200.

In the embodiment of the present application, the pulse signal source 200 may be a pulse voltage source or a pulse current source.

The pulsing of the phase change memory cell is implemented in accordance with the connection of fig. 2a or fig. 2 b. In particular, the first pulse and the second pulse may be applied sequentially to the first electrode in fig. 2a or fig. 2 b. The first pulse and the second pulse are used for adjusting the resistance state of the phase change memory cell. Wherein the first pulse and the second pulse have opposite polarities.

Wherein the first pulse comprises one or more pulses and the second pulse comprises one or more pulses. A possible combination of the first pulse and the second pulse applied in this example application is: the first pulse is one pulse and the second pulse is one pulse, or the first pulse is a plurality of pulses and the second pulse is one pulse, or the first pulse is one pulse and the second pulse is a plurality of pulses, or the first pulse is a plurality of pulses and the second pulse is a plurality of pulses.

In addition, because the polarities of the first pulse and the second pulse are opposite, elements in the phase change layer cannot migrate towards one direction, for example, the phase change material is Ge in the form of phase change material₂Sb ₂Te ₅For example, the first pulse is a forward pulse, and at this time, the upper electrode is an anode, the lower electrode is a cathode, the Ge element and the Sb element migrate to the lower electrode, and the Te element migrates to the upper electrode; the second pulse is a negative pulse, at this time, the upper electrode is a cathode, the lower electrode is an anode, the Ge element and the Sb element migrate to the upper electrode, and the Te element migrates to the lower electrode. Thus, when the resistance state of the phase change memory cell is changed many times, the Te element, the Ge element, and the Sb element migrate toward the upper electrode and the lower electrode, respectively, instead of the Ge element and the Sb element migrating only toward the lower electrode and the Te element migrating only toward the upper electrode. It is understood that, since each element is accumulated after being transferred a plurality of times to form a defect state, and the accumulation degree of Te element on the upper electrode after being transferred in different directions is necessarily smaller than the accumulation degree of Te element on the upper electrode after being transferred only in the direction of the upper electrode, the defect state is also reduced with the decrease of the accumulation degree, and the same is true for Ge element and Sb element. Therefore, even if the erasing frequency is increased continuously, the accumulation degree of each element on the upper electrode or the lower electrode is reduced, the accumulation degree of the defect state on the upper electrode or the lower electrode of the phase change layer is lower, the resistance value drift degree of the phase change memory cell is further reduced, and the data retention capability is improved.

In the same way, for the first pulse and the second pulse which are applied to the lower electrode in sequence under the condition that the upper electrode is grounded in the embodiment of the application, the resistance state of the phase change memory unit can be adjusted through the first pulse or the second pulse, in addition, because the polarities of the first pulse and the second pulse are opposite, each element in the phase change layer can not be excessively accumulated towards one direction, the accumulation degree of each element on the upper electrode or the lower electrode can be reduced even if the erasing times are continuously increased, meanwhile, the accumulation degree of the defect state on the upper electrode or the lower electrode of the phase change layer is lower, the resistance drift degree of the phase change memory unit is further reduced, and the data retention capability is improved.

The various forms that the first and second pulses applied comprise are described next.

A. In an alternative pulse form, the first pulse is a pulse and the second pulse is a pulse, the polarity of the two pulses being opposite, for example, the first pulse may be a positive-going pulse and the second pulse may be a negative-going pulse, or the first pulse may be a negative-going pulse and the second pulse may be a positive-going pulse. The first pulse is used for adjusting the resistance state of the phase change memory cell to a first state, and the second pulse is used for adjusting the resistance state of the phase change memory cell from the first state to a second state. Because the polarities of the first pulse and the second pulse are opposite, elements in the phase change layer cannot migrate towards one direction, the accumulation degree of the elements on the upper electrode or the lower electrode can be reduced even if the erasing times are increased continuously, the accumulation degree of the defect states on the upper electrode or the lower electrode of the phase change layer is lower, the resistance value drifting degree of the phase change memory unit is further reduced, and the data retention capacity is improved.

In a scene that the phase change memory cell can realize binary storage, the resistance state of the phase change memory cell comprises a high resistance state and a low resistance state, and the resistance value of the phase change cell corresponding to the high resistance state is larger than that of the phase change cell corresponding to the low resistance state. According to the embodiment of the application, the resistance state of the phase change memory cell can be adjusted through the first pulse and the second pulse, so that binary storage is realized.

In a1 th possible design, the first pulse may be used to adjust the resistance state of the phase change memory cell from a high resistance state to a low resistance state, and the second pulse may be used to adjust the resistance state of the phase change memory cell from the low resistance state to the high resistance state. In this case, the first state is a low resistance state and the second state is a high resistance state. The amplitude of the first pulse is smaller than that of the second pulse, and the pulse width of the first pulse is larger than that of the second pulse. In this possible design, the amplitude of the first pulse ranges from (0.8 volts to 1.5 volts); the pulse width of the first pulse is in a range of (200-400 nanoseconds); the amplitude of the second pulse ranges from (1.6 volts to 4 volts); the second pulse has a pulse width in the range of (20 ns to 100 ns). For example, the first pulse has an amplitude of 1.3 volts and a pulse width of 300 nanoseconds; the second pulse has an amplitude of 3 volts and a pulse width of 30 nanoseconds. The resistance range of the phase change memory cell corresponding to the low resistance state is as follows: (0 ohm-10 kilo ohm), the resistance range of the phase change memory unit corresponding to the high resistance state is (1 megaohm-10 megaohm), and the resistance range corresponding to each resistance state is not limited in the embodiment of the application.

Referring to fig. 3, an exemplary diagram of a pulse form is provided for the embodiments of the present application. As shown in fig. 3, the exemplary diagram is exemplified by the first pulse being a positive-going pulse and the second pulse being a negative-going pulse. The method comprises the following steps: the first pulse can adjust the phase-change material of the phase-change memory unit from an amorphous state to a crystalline state, and the resistance state of the phase-change memory unit after adjustment is a low resistance state; the second pulse can adjust the phase-change material of the phase-change memory unit from a crystalline state to an amorphous state, and the resistance state of the phase-change memory unit after adjustment is a high resistance state. Assuming that the resistance range of the phase change memory cell corresponding to the low resistance state is: (0 ohm-10 kilo ohm), the resistance range of the phase change memory unit corresponding to the high resistance state is (1 megaohm-10 megaohm); the first pulse can be a positive set (set) pulse, the amplitude of the positive set (set) pulse is 1.3 volts, the pulse width of the positive set (set) pulse is 300 nanoseconds, and after the first pulse is applied, the resistance value of the phase change memory cell is detected to be 5 kilo-ohms, and the phase change memory cell is determined to be in a low resistance state currently; the second pulse is a negative reset (reset) pulse, the amplitude of the second pulse is 3 volts, the pulse width of the second pulse is 30 nanoseconds, and after the first pulse is applied, the resistance value of the phase change memory cell is detected to be 8 megaohms, and the phase change memory cell is determined to be in a high-resistance state currently.

In a2 th possible design, a first pulse may be used to adjust the resistance state of the phase change memory cell from a high resistance state to a high resistance state, and a second pulse may be used to adjust the resistance state of the phase change memory cell from a high resistance state to a low resistance state. In this case, the first state is a high resistance state and the second state is a low resistance state. The possible design may refer to the specific description of the a1 possible design that the first state is the low impedance state and the second state is the high impedance state, and specifically, the "first pulse" in the a2 possible design is equivalent to the "second pulse" in the a1 possible design, and the "second pulse" in the a2 possible design is equivalent to the "first pulse" in the a1 possible design; and will not be described in detail herein.

For the a1 and a2 possible designs, for example, the erase operation performed on the phase change memory cell can be specifically realized by applying the first pulse, while the phase change memory cell is maintained in the low resistance state; performing writing operation on the phase change memory unit, wherein if a binary number '0' is specified to correspond to a low resistance state, and a binary number '1' is specified to correspond to a high resistance state, and if the binary number '1' needs to be written, the phase change memory unit can be kept in the high resistance state by applying a second pulse; if a "0" needs to be written, this can be achieved by applying a first pulse to keep the phase change memory cell in the low resistance state.

In view of the a1 possible designs and the a2 possible designs, the resistance ranges of the phase change memory cells corresponding to the high resistance state, the low resistance state, and the at least one intermediate resistance state are not limited in the embodiments of the present application. Optionally, before performing an operation of applying a pulse to the phase change memory cell to change the resistance state, a current resistance of the phase change memory cell may be detected, and if the current resistance falls within a resistance range corresponding to the required resistance state, the pulse does not need to be applied to the phase change memory cell.

In a scene that the phase change memory cell can realize multi-value storage, the resistance state of the phase change memory cell comprises a high resistance state, a low resistance state and at least one intermediate resistance state, and the resistance state of the phase change memory cell also comprises at least one intermediate resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is smaller than that of the phase change unit corresponding to the high resistance state, and the resistance value of the phase change unit corresponding to the intermediate resistance state is larger than that of the phase change unit corresponding to the low resistance state. According to the embodiment of the application, the resistance state of the phase change memory cell can be adjusted through the first pulse and the second pulse, so that multi-value storage is realized.

In a possible design of b1, a first pulse may be used to adjust the resistance state of the phase change memory cell to a low resistance state, and a second pulse may be used to adjust the resistance state of the phase change memory cell from the low resistance state to a first target resistance state. In this case, the first state is a low resistance state, the second state is a first target resistance state, and the first target resistance state is any one of the low resistance state and at least one intermediate resistance state. The amplitude of the first pulse is smaller than that of the second pulse, and the pulse width of the first pulse is larger than that of the second pulse. In this possible design, the amplitude of the first pulse ranges from (0.8 volts to 1.5 volts); the pulse width of the first pulse is in a range of (200-400 nanoseconds); the amplitude of the second pulse ranges from (1.6 volts to 4 volts); the second pulse has a pulse width in the range of (20 ns to 100 ns). For example, the first pulse has an amplitude of 1.3 volts and a pulse width of 300 nanoseconds; the amplitude of the second pulse may be increased within a range of 1.5V to 3.5V, the pulse width is 30 ns, different amplitudes of the second pulse correspond to different resistance states in the first target resistance state, for example, the first target resistance state includes a first intermediate resistance state, a second intermediate resistance state and a high resistance state, the amplitude of the second pulse is 1.5V corresponding to the first intermediate resistance state, the amplitude of the second pulse is 2.5V corresponding to the second intermediate resistance state, and the amplitude of the second pulse is 3.5V corresponding to the high resistance state. The resistance range of the phase change memory cell corresponding to the low resistance state is as follows: the resistance ranges of the phase change memory cells corresponding to the first intermediate resistance state are (50 kilo-ohms-200 kilo-ohms), the resistance ranges of the phase change memory cells corresponding to the second intermediate resistance state are (500 kilo-ohms-700 kilo-ohms), and the resistance ranges of the phase change memory cells corresponding to the high resistance state are (1 megaohm-10 megaohms).

Referring to fig. 4, an exemplary diagram of another pulse form is provided for the embodiments of the present application. As shown in fig. 4, the exemplary diagram is exemplified by the first pulse being a positive-going pulse and the second pulse being a negative-going pulse. Fig. 4 includes a first pulse 400, a second pulse 401, a second pulse 402, and a second pulse 403.

The phase change memory cell suitable for the pulse form of fig. 4 includes a low resistance state, a first intermediate resistance state, a second intermediate resistance state, and a high resistance state, and the resistance values corresponding to the phase change memory cell in the low resistance state, the first intermediate resistance state, the second intermediate resistance state, and the high resistance state are from low to high. The first pulse 400 may be used to adjust the resistance state of the phase change memory cell to a low resistance state, the second pulse 401 may be used to adjust the resistance state of the phase change memory cell to a first intermediate resistance state, the second pulse 402 may be used to adjust the resistance state of the phase change memory cell to a second intermediate resistance state, and the second pulse 403 may be used to adjust the resistance state of the phase change memory cell to a high resistance state.

Optionally, the pulse amplitudes of the second pulse 401, the second pulse 402, and the second pulse 403 are sequentially increased, and the pulse widths of the second pulse 401, the second pulse 402, and the second pulse 403 may be the same. For example, the first pulse 400 is a set pulse having an amplitude of 1.3 volts and a pulse width of 300 nanoseconds; the pulse widths of the second pulse 401, the second pulse 402, and the second pulse 403 are 30 nanoseconds, and the pulse amplitudes of the second pulse 401, the second pulse 402, and the second pulse 403 are increased by 1.5V to 3.5V. For example, assume that the resistance range of the phase change memory cell corresponding to the low resistance state is: (0-10 kilo-ohms), the resistance range of the phase change memory unit corresponding to the first intermediate resistance state is (50-200 kilo-ohms), the resistance range of the phase change memory unit corresponding to the second intermediate resistance state is (500-700 kilo-ohms), and the resistance range of the phase change memory unit corresponding to the high resistance state is (1-10 megohms); the first pulse 400 may be a positive set (set) pulse, the amplitude of which is 1.3 v, the pulse width of which is 300 ns, and after the first pulse is applied, it is determined that the resistance value of the phase change memory cell is 5 kohms, and it is determined that the phase change memory cell is currently in a low resistance state; the second pulse 401 is a negative pulse, the amplitude of the second pulse is 1.5 volts, the pulse width of the second pulse is 30 nanoseconds, and after the second pulse 401 is applied, the resistance value of the phase change memory cell is detected to be 150 kilo-ohms, and the phase change memory cell is determined to be in a first intermediate resistance state at present; the second pulse 402 is a negative pulse, the amplitude of the second pulse is 2.5 volts, the pulse width of the second pulse is 30 nanoseconds, and after the second pulse 402 is applied, the resistance value of the phase change memory cell is detected to be 600 kiloohms, and the phase change memory cell is determined to be in a second intermediate resistance state currently; the second pulse 403 is a negative pulse, the amplitude of the negative pulse is 3.5v, the pulse width of the negative pulse is 30 ns, and after the second pulse 403 is applied, the resistance value of the phase change memory cell is detected to be 8 megohms, and it is determined that the phase change memory cell is currently in the high resistance state.

The phase change memory cell shown in fig. 4 can implement four-value storage, such as 00, 01, 10, 11; one value uniquely corresponds to one resistance state. For example, as shown in fig. 4, the high resistance state corresponds to 00, the first intermediate resistance state corresponds to 01, the second intermediate resistance state corresponds to 10, and the low resistance state corresponds to 11. When the write operation is performed, the pulse signal may be applied according to the pulse amplitude and the pulse width corresponding to each resistance state shown in fig. 4 to change the resistance value of the phase change memory cell, and further change the resistance value state of the phase change memory cell, for example, if data 11 needs to be written, a pulse with an amplitude of 1.3 v and a pulse width of 300 nanoseconds is applied to change the resistance value of the phase change memory cell. When the read operation is executed, the current resistance value of the phase change memory cell can be detected, and if the resistance value of the phase change memory cell is in the value range corresponding to the low resistance state, the data written in the phase change memory cell is determined to be 11.

In a possible design of b2, the first pulse may be used to adjust the resistance state of the phase change memory cell from the high resistance state to a high resistance state, and the second pulse may be used to adjust the resistance state of the phase change memory cell from the high resistance state to a second target resistance state, the second target resistance state being any one of the low resistance state and the at least one intermediate resistance state. In this case, the first state is a high resistance state, and the second state is any one of a low resistance state and at least one intermediate resistance state. The amplitude of the first pulse is larger than that of the second pulse, and the pulse width of the first pulse is smaller than that of the second pulse.

In this possible design, the amplitude of the first pulse ranges from (1.6 volts to 4 volts); the pulse width of the first pulse is in the range of (20-100 nanoseconds); the amplitude range of the second pulse is (0.8-1.5 volts); the second pulse has a pulse width in the range of (200 ns to 400 ns). For example, the first pulse has an amplitude of 3 volts and a pulse width of 30 nanoseconds; the amplitude of the second pulse is 1.3 v, the pulse width of the second pulse increases gradually in a range from 200 ns to 400 ns, different pulse widths of the second pulse correspond to different resistance states in the second target resistance state, for example, the first target resistance state includes a first intermediate resistance state, a second intermediate resistance state and a high resistance state, the pulse width of the second pulse is 200 ns and corresponds to the first intermediate resistance state, the pulse width of the second pulse is 300 ns and corresponds to the second intermediate resistance state, and the pulse width of the second pulse is 400 ns and corresponds to the high resistance state.

Referring to fig. 5, an exemplary diagram of another pulse form is provided for the embodiments of the present application. As shown in fig. 5, the exemplary diagram is exemplified by the first pulse being a positive-going pulse and the second pulse being a negative-going pulse. Fig. 5 includes a first pulse 500, a second pulse 501, a second pulse 502, and a second pulse 503.

The phase change memory cell suitable for the pulse form shown in fig. 5 includes a low resistance state, a first intermediate resistance state, a second intermediate resistance state, and a high resistance state, and the resistance values of the phase change memory cell in the low resistance state, the first intermediate resistance state, the second intermediate resistance state, and the high resistance state are from low to high. The first pulse 500 may be used to adjust the resistance state of the phase change memory cell to a high resistance state, the second pulse 501 may be used to adjust the resistance state of the phase change memory cell to a second intermediate resistance state, the second pulse 502 may be used to adjust the resistance state of the phase change memory cell to a first intermediate resistance state, and the second pulse 503 may be used to adjust the resistance state of the phase change memory cell to a low resistance state.

Optionally, the pulse widths of the second pulse 501, the second pulse 502, and the second pulse 503 are sequentially increased, and the pulse amplitudes of the second pulse 501, the second pulse 502, and the second pulse 503 may be the same. For example, the first pulse 500 is a set pulse having an amplitude of 3 volts and a pulse width of 30 nanoseconds; the amplitudes of the second pulse 501, the second pulse 502 and the second pulse 503 are 1.3 volts, and the pulse widths of the second pulse 501, the second pulse 502 and the second pulse 503 are increased in a range from 200 nanoseconds to 400 nanoseconds. For example, assume that the resistance range of the phase change memory cell corresponding to the low resistance state is: (0-10 kilo-ohms), the resistance range of the phase change memory unit corresponding to the first intermediate resistance state is (50-200 kilo-ohms), the resistance range of the phase change memory unit corresponding to the second intermediate resistance state is (500-700 kilo-ohms), and the resistance range of the phase change memory unit corresponding to the high resistance state is (1-10 megohms); the first pulse 500 may be a forward pulse, the amplitude of which is 3 v, the pulse width of which is 30 ns, and after the first pulse 500 is applied, the resistance value of the phase change memory cell is detected to be 8 megohms, and it is determined that the phase change memory cell is currently in the high resistance state; the second pulse 501 is a negative pulse, the amplitude of the negative pulse is 1.3 volts, the pulse width of the negative pulse is 100 nanoseconds, and after the second pulse 501 is applied, the resistance value of the phase change memory cell is detected to be 550 kilo-ohms, and the phase change memory cell is determined to be in a second intermediate resistance state currently; the second pulse 502 is a negative pulse, the amplitude of the second pulse is 1.3 volts, the pulse width of the second pulse is 200 nanoseconds, and after the second pulse 502 is applied, the resistance value of the phase change memory cell is detected to be 130 kiloohms, and the phase change memory cell is determined to be in a first intermediate resistance state at present; the second pulse 503 is a negative pulse, the amplitude of the second pulse is 1.3 v, the pulse width of the second pulse is 300 ns, and after the second pulse 503 is applied, the resistance value of the phase change memory cell is detected to be 5 kilo-ohms, and the phase change memory cell is determined to be in the low resistance state currently.

The phase change memory cell shown in fig. 5 may implement four-value storage, such as 00, 01, 10, 11; one value uniquely corresponds to one resistance state. The resistance value of the phase change memory cell is changed by setting the amplitude and the pulse width of the applied pulse, and the resistance state of the phase change memory cell is further changed. For example, as shown in fig. 5, the high resistance state corresponds to 11, the first intermediate resistance state corresponds to 01, the second intermediate resistance state corresponds to 10, and the low resistance state corresponds to 00. When the write operation is performed, the resistance value of the phase change memory cell can be changed by applying the pulse signal according to the pulse amplitude and the pulse width corresponding to each resistance state shown in fig. 5, so as to change the resistance value state of the phase change memory cell, for example, if data 11 needs to be written, the resistance value of the phase change memory cell is changed by applying a pulse with an amplitude of 3 volts and a pulse width of 30 nanoseconds. When a read operation is performed, the current resistance value of the phase change memory cell may be detected, and if the resistance value of the phase change memory cell is in the value range corresponding to the high resistance state, it is determined that the data written in the phase change memory cell is 11.

For the b1 and b2 possible designs, specifically, the erasing operation performed on the phase change memory cell may be performed by applying a pulse to make the resistance state of the phase change memory cell be in a preset initial state, where the preset initial state may be a high resistance state or a low resistance state in a binary storage scenario, or may be any one of a plurality of resistance states in a multi-value storage scenario, and the setting of the preset initial state is not limited in the embodiment of the present application.

For the b1 possible designs and the b2 possible designs, the resistance ranges of the phase change memory cells corresponding to the high resistance state, the low resistance state, and the at least one intermediate resistance state are not limited in the embodiments of the present application. Optionally, before performing an erase operation or a write operation on the phase change memory cell to change the resistance state, a current resistance of the phase change memory cell may be detected, and if the current resistance falls within a resistance range corresponding to the required resistance state, no pulse is applied to the phase change memory cell.

For the b1 and b2 possible designs, before performing a write operation to the phase-change memory cell to change the resistance state, an initialization operation, such as the first pulse 400 shown in fig. 4 and the first pulse 500 shown in fig. 5, may be optionally performed on the phase-change memory cell, for example, to adjust the resistance state of the phase-change memory cell to a low resistance state or a high resistance state, and then to adjust the resistance state of the phase-change memory cell by applying a pulse.

B. In yet another alternative pulse form, the first pulse is a plurality of pulses, and the second pulse is a plurality of pulses, which are opposite in polarity, and for example, the first pulse may be a positive-going pulse and the second pulse may be a negative-going pulse, or the first pulse may be a negative-going pulse and the second pulse may be a positive-going pulse. The first pulse is used for adjusting the resistance state of the phase change memory cell to a first state, and the second pulse is used for adjusting the resistance state of the phase change memory cell from the first state to a second state. Because the polarities of the first pulse and the second pulse are opposite, elements in the phase change layer cannot migrate towards one direction, the accumulation degree of the elements on the upper electrode or the lower electrode can be reduced even if the erasing times are increased continuously, the accumulation degree of the defect states on the upper electrode or the lower electrode of the phase change layer is lower, the resistance value drifting degree of the phase change memory unit is further reduced, and the data retention capacity is improved.

In a scene that the phase change memory cell can realize binary storage, the resistance state of the phase change memory cell comprises a high resistance state and a low resistance state, and the resistance value of the phase change cell corresponding to the high resistance state is larger than that of the phase change cell corresponding to the low resistance state. According to the embodiment of the application, the resistance state of the phase change memory cell can be adjusted through the first pulse and the second pulse, so that binary storage is realized. The method comprises the following steps: the first pulse comprises a plurality of pulses which can be used for adjusting the resistance state of the phase change memory unit from a high resistance state to a low resistance state, and the second pulse comprises a plurality of pulses which can be used for adjusting the resistance state of the phase change memory unit from the low resistance state to the high resistance state; alternatively, the first pulse may include a plurality of pulses for adjusting the resistance state of the phase change memory cell from the low resistance state to the high resistance state, and the second pulse may include a plurality of pulses for adjusting the resistance state of the phase change memory cell from the high resistance state to the low resistance state. Here, the amplitudes of the multiple pulses may be the same or different, and the pulse widths of the multiple pulses may be the same or different, which is not limited in this embodiment of the application.

In a scene that the phase change memory cell can realize multi-value storage, the resistance state of the phase change memory cell comprises a high resistance state, a low resistance state and at least one intermediate resistance state, and the resistance state of the phase change memory cell also comprises at least one intermediate resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is smaller than that of the phase change unit corresponding to the high resistance state, and the resistance value of the phase change unit corresponding to the intermediate resistance state is larger than that of the phase change unit corresponding to the low resistance state. According to the embodiment of the application, the resistance state of the phase change memory cell can be adjusted through the first pulse and the second pulse, so that multi-value storage is realized. The method comprises the following steps: the first pulse comprises a plurality of pulses which can be used for adjusting the resistance state of the phase change memory unit to a low resistance state, and the second pulse comprises a plurality of pulses which can be used for adjusting the resistance state of the phase change memory unit from the low resistance state to a first target resistance state; the first target resistance state is any one of a low resistance state and at least one intermediate resistance state; alternatively, the plurality of pulses included in the first pulse may be used to adjust the resistance state of the phase change memory cell to a high resistance state, and the plurality of pulses included in the second pulse may be used to adjust the resistance state of the phase change memory cell from the high resistance state to a second target resistance state, where the second target resistance state is any one of a low resistance state and at least one intermediate resistance state. Here, the amplitudes of the multiple pulses may be the same or different, and the pulse widths of the multiple pulses may be the same or different, which is not limited in this embodiment of the application.

Referring to fig. 6, an exemplary diagram of yet another pulse form is provided for the embodiments of the present application. As shown in fig. 6, the exemplary diagram is exemplified by the first pulse being a positive-going pulse and the second pulse being a negative-going pulse. Wherein the first pulse comprises pulse 601, pulse 602, and pulse 603; the second pulse includes pulse 604, pulse 605, and pulse 606.

Wherein the resistance state of the phase change memory cell can be adjusted to a first state after applying pulse 601, pulse 602, and pulse 603, and can be adjusted to a second state after applying pulse 604, pulse 605, and pulse 606.

For example, compared to fig. 3, the resistance state of the phase change memory cell is also adjusted to the first state, in the example of fig. 3, one pulse with an amplitude of 1.3 v and a pulse width of 300 ns is used for implementation, and fig. 6 may be implemented by three pulses with an amplitude of 1.3 v and a pulse width of 100 ns. Similarly, the resistance state of the phase change memory cell is adjusted to the second state, in the example of fig. 3, one pulse with an amplitude of 3 v and a pulse width of 30 ns is used for implementation, and in fig. 6, three pulses with pulse widths of 30 ns and amplitudes of 2 v are used for implementation.

It should be noted that, in a scenario where the phase change memory cell can implement binary storage or multi-value storage, the mode a is to implement one-time adjustment of the resistance state of the phase change memory cell by only one pulse, and the mode B is to implement one-time adjustment of the resistance state of the phase change memory cell by multiple pulses, so that the resistance state of the phase change memory cell can be changed by multiple pulses when the resistance state of the phase change memory cell is changed by one pulse, which is introduced in the mode a. For example, the first pulse 400 having an amplitude of 1.3 v and a pulse width of 300 ns in the a mode may be replaced with 3 pulses having an amplitude of 1.3 v and a pulse width of 100 ns in the B mode, and a plurality of pulses are sequentially applied to the first electrode; as another example, the first pulse 500 having an amplitude of 3 volts and a pulse width of 30 nanoseconds in the a mode may be replaced with 3 pulses having an amplitude of 2 volts and a pulse width of 30 nanoseconds in the B mode, and a plurality of pulses are sequentially applied to the first electrode. In the embodiment of the present application, in a scenario where the primary resistance state is adjusted by a plurality of pulses, the setting of the amplitudes and the pulse widths of the plurality of pulses is not limited. In the two scenarios, the specific process of performing the erasing operation in the B mode may refer to the description in the a mode, and the difference between the two scenarios is that the number of applied pulses, the amplitude of the pulses, and the pulse width are different, and will not be described herein again.

C. In yet another alternative pulse form, the first pulse is a plurality of pulses, and the second pulse is a plurality of pulses, which are opposite in polarity, and for example, the first pulse may be a positive-going pulse and the second pulse may be a negative-going pulse, or the first pulse may be a negative-going pulse and the second pulse may be a positive-going pulse. The number of the plurality of pulses included in the first pulse and the number of the plurality of pulses included in the second pulse are not limited in the present application. The amplitudes of the multiple pulses may be the same or different, and the pulse widths of the multiple pulses may be the same or different, which is not limited in this application. Because the polarities of the first pulse and the second pulse are opposite, elements in the phase change layer cannot migrate towards one direction, the accumulation degree of the elements on the upper electrode or the lower electrode can be reduced even if the erasing times are increased continuously, the accumulation degree of the defect states on the upper electrode or the lower electrode of the phase change layer is lower, the resistance value drifting degree of the phase change memory unit is further reduced, and the data retention capacity is improved.

In the method C, taking the first pulse as an example, one pulse or a part of pulses in a plurality of pulses included in the first pulse may implement adjusting the resistance state of the phase change memory cell; the second pulse may comprise one or a portion of a plurality of pulses to effect adjustment of the resistance state of the phase change memory cell. Similarly, the second pulse may refer to the description of the first pulse. In a scenario where the phase change memory cell can implement binary storage or multi-valued storage, the specific process of performing the erasing operation in the C mode may refer to the description in the a mode, and is not described herein again.

Next, the pulse form of the first pulse and the second pulse in the C mode will be exemplified, and specifically refer to the description of fig. 7a to 7C.

Referring to fig. 7a, an exemplary diagram of another pulse form is provided for the embodiment of the present application. As shown in fig. 7a, the exemplary diagram is exemplified by the first pulse being a positive-going pulse and the second pulse being a negative-going pulse. Wherein the first pulse comprises pulse 7a01 and pulse 7a 02; the second pulse includes pulse 7a03 and pulse 7a 04. Each pulse in FIG. 7a may be implemented to adjust the resistance state of a phase change memory cell, e.g., pulse 7a01 adjusts the resistance state of a phase change memory cell to a first state and pulse 7a02 adjusts the resistance state of a phase change memory cell from the first state to a second state. The pulse 7a03 adjusts the resistance state of the phase change memory cell to a first state and the pulse 7a04 adjusts the resistance state of the phase change memory cell from the first state to a second state.

Referring to fig. 7b, an exemplary diagram of another pulse form is provided for the embodiment of the present application. As shown in fig. 7b, the exemplary diagram is for example the first pulse is a positive-going pulse and the second pulse is a negative-going pulse. Wherein the first pulse comprises pulse 7b01, pulse 7b02, pulse 7b03, pulse 7b04, pulse 7b05, and pulse 7b 06; the second pulse includes pulse 7b07, pulse 7b08, pulse 7b09, pulse 7b10, pulse 7b11, and pulse 7b 12. Two or more pulses in FIG. 7b effect an adjustment of the resistance state of the phase change memory cell, e.g., pulse 7b01, pulse 7b02, pulse 7b03 adjust the resistance state of the phase change memory cell to the first state, and pulse 7b04, pulse 7b05, and pulse 7b06 adjust the resistance state of the phase change memory cell from the first state to the second state. Similarly, the resistance state of the phase change memory cell is adjusted to the first state by the pulse 7b07, the pulse 7b08 and the pulse 7b09, and the resistance state of the phase change memory cell is adjusted to the second state by the pulse 7b10, the pulse 7b11 and the pulse 7b 12.

Referring to fig. 7c, an exemplary diagram of another pulse form is provided for the embodiment of the present application. As shown in fig. 7c, the exemplary diagram is for example the first pulse is a positive-going pulse and the second pulse is a negative-going pulse. Wherein the first pulse comprises pulse 7c01, pulse 7c02, pulse 7c03, and pulse 7c 04; the second pulse includes pulses 7c05 and 7c06, 7c07, and 7c 08. One of fig. 7c may implement adjusting the resistance state of the phase change memory cell, and the plurality of pulses may also implement adjusting the resistance state of the phase change memory cell, for example, pulse 7c01, pulse 7c02, and pulse 7c03 may implement adjusting the resistance state of the phase change memory cell to the first state, and pulse 7c04 may implement adjusting the resistance state of the phase change memory cell from the first state to the second state. Similarly, the pulses 7c05, 7c06, and 7c07 adjust the resistance state of the phase change memory cell from the first state to the second state, and the pulses 7c08 adjust the resistance state of the phase change memory cell from the first state to the second state.

Fig. 7a to 7b are merely illustrations of pulse forms included in the method C, and the embodiment of the present application does not limit the form of a plurality of pulses included in the first pulse or the second pulse on the premise that the polarities of the first pulse and the second pulse are opposite.

It should be noted that, in a scenario where the phase change memory cell can implement binary storage or multi-value storage, in the C mode, one adjustment of the resistance state of the phase change memory cell can be implemented by one pulse, and one adjustment of the resistance state of the phase change memory cell can be implemented by a plurality of pulses. The mode a is to realize the primary adjustment of the resistance state of the phase change memory cell by only one pulse, and the mode B is to realize the primary adjustment of the resistance state of the phase change memory cell by a plurality of pulses, so that the description in the mode a can be referred to for the case of realizing the primary adjustment of the resistance state by one pulse in the mode C, and the description in the mode B can be referred to for the case of realizing the primary adjustment of the resistance state by a plurality of pulses in the mode C.

In the above B-mode or C-mode, when M pulses are applied to the phase change memory cell to adjust the resistance value state of the phase change memory cell to the first state, if the resistance value of the phase change memory cell read after the M pulses are applied is within the resistance value range corresponding to the first state, it is determined that the resistance value state of the phase change memory cell is adjusted to the first state, and M is a positive integer. Optionally, in the process of applying a plurality of pulses, the resistance value corresponding to the phase change memory cell read after applying the ith pulse may be applied, if the read resistance value is not within the resistance value range corresponding to the first state, the (i +1) th pulse is continuously applied, and if the read resistance value is within the resistance value range corresponding to the first state, the application of the pulse for adjusting the resistance value state of the phase change memory cell to the first state is stopped.

Similarly, under the condition that the phase change memory cell is applied with N pulses to adjust the resistance value state of the phase change memory cell to the second state, if the resistance value corresponding to the phase change memory cell read after the application of the N pulses is within the resistance value range corresponding to the second state, the resistance value state of the phase change memory cell is determined to be adjusted to the second state, and N is a positive integer. Optionally, in the process of applying a plurality of pulses, the resistance value corresponding to the phase change memory cell read after applying the jth pulse may be applied, if the read resistance value is not within the resistance value range corresponding to the second state, the (j +1) th pulse is continuously applied, and if the read resistance value is within the resistance value range corresponding to the second state, the application of the pulse for adjusting the resistance value state of the phase change memory cell to the second state is stopped.

For example, when the resistance state of the phase change memory cell is adjusted to the low resistance state by a plurality of nanosecond pulses with amplitude of 1.3 v and pulse width of 100, it is assumed that the resistance range of the phase change memory cell corresponding to the low resistance state is: (0-10 kilo-ohms). Specifically, after the 1 st pulse with the amplitude of 1.3 v and the pulse width of 100 ns is applied, the resistance value of the phase change memory cell is read to be 550 kilo-ohms, because the resistance value is larger than the resistance value range corresponding to the low resistance state, the 2 nd pulse with the amplitude of 1.3 v and the pulse width of 100 ns is continuously applied, the resistance value of the phase change memory cell is read to be 80 kilo-ohms, because the resistance value is larger than the resistance value range corresponding to the low resistance state, the 3 rd pulse with the amplitude of 1.3 v and the pulse width of 100 ns is continuously applied, the resistance value of the phase change memory cell is read to be 7 kilo-ohms, and because the resistance value of the current phase change memory cell is in the resistance value range corresponding to the low resistance state, the application of the pulse for adjusting the resistance state of the.

In the above-described mode B or mode C, the resistance ranges of the phase change memory cells corresponding to the high resistance state, the low resistance state, and the at least one intermediate resistance state are not limited in this embodiment, and the amplitude and the pulse width of the pulse used to adjust the resistance state of the phase change memory cell may refer to the specific description of the mode a, which is not described herein again.

The first pulse and the second pulse described in the above-mentioned a, B, and C modes include the same number of pulses, but the number of pulses included in the first pulse and the second pulse may be different in the embodiment of the present application.

Referring to fig. 8, fig. 8 is a schematic structural diagram of an operating device according to an embodiment of the present disclosure. The operating device is used to implement the embodiment of fig. 2a to 7 c. As shown in fig. 8, the operation apparatus 800 is used for operating a phase change memory cell, the phase change memory cell includes a first electrode, a phase change layer, and a second electrode, the second electrode is grounded, the operation apparatus 800 includes a pulse applying module 801, and optionally, a determining module 802.

A pulse applying module 801, configured to sequentially apply a first pulse and a second pulse to the first electrode, where the first pulse and the second pulse are respectively used to adjust a resistance state of the phase change memory cell; wherein the polarity of the first pulse is opposite to the polarity of the second pulse.

In one possible implementation manner, the first pulse is a positive-going pulse, and the second pulse is a negative-going pulse;

or, the first pulse is a negative pulse, and the second pulse is a positive pulse.

In a possible implementation manner, when the first pulse is a plurality of pulses, the amplitudes of the plurality of pulses are different and the pulse widths are different, or the amplitudes of the plurality of pulses are the same and the pulse widths are different, or the amplitudes of the plurality of pulses are different and the pulse widths are the same, or the amplitudes of the plurality of pulses are the same and the pulse widths are the same;

when the second pulse is a plurality of pulses, the plurality of pulses have different amplitudes and different pulse widths, or the plurality of pulses have the same amplitude and different pulse widths, or the plurality of pulses have different amplitudes and the same pulse widths, or the plurality of pulses have the same amplitude and the same pulse widths.

In one possible implementation, the resistance state of the phase change memory cell includes a high resistance state and a low resistance state; the resistance value of the phase change unit corresponding to the high resistance state is larger than that of the phase change unit corresponding to the low resistance state.

In one possible implementation, the resistance state of the phase change memory cell further includes at least one intermediate resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is smaller than that of the phase change unit corresponding to the high resistance state, and the resistance value of the phase change unit corresponding to the intermediate resistance state is larger than that of the phase change unit corresponding to the low resistance state.

In one possible implementation manner, the first pulse is used to adjust the resistance state of the phase change memory cell to a first state; the second pulse is used for adjusting the resistance state of the phase change memory cell from the first state to a second state.

In a possible implementation manner, the first pulse is one pulse, and the second pulse is one pulse;

under the condition that the first state is the high impedance state and the second state is a first target impedance state, the amplitude of the first pulse is larger than that of the second pulse, and the pulse width of the first pulse is smaller than that of the second pulse;

under the condition that the first state is the low impedance state and the second state is a second target impedance state, the amplitude of the first pulse is smaller than that of the second pulse, and the pulse width of the first pulse is larger than that of the second pulse;

wherein the first target resistance state is any one of the low resistance state and the at least one intermediate resistance state; the second target resistance state is any one of the high resistance state and the at least one intermediate resistance state.

In a possible implementation manner, the first pulse is M pulses, and the second pulse is N pulses; the device further comprises:

a determining module 802, configured to determine to adjust the resistance state of the phase change memory cell to a first state if the resistance value corresponding to the phase change memory cell read after applying the M pulses is within the resistance value range corresponding to the first state, where M is a positive integer;

the determining module 802 is further configured to determine to adjust the resistance state of the phase change memory cell to the second state if the resistance value corresponding to the phase change memory cell read after applying the N pulses is within the resistance value range corresponding to the second state, where N is a positive integer.

In one possible implementation, the first electrode is an upper electrode, and the second electrode is a lower electrode; or, the first electrode is a lower electrode, and the second electrode is an upper electrode.

At this time, the operation device 800 may implement the operation method for the phase change memory cell described in fig. 2a to 7c, and the detailed process executed by each module may refer to the detailed description of the embodiment shown in fig. 2a to 7c, which is not described herein again.

The operating device 800 shown in fig. 8 described above may be implemented by the operating device 900 shown in fig. 9. As shown in fig. 9, a schematic structural diagram of another operating device is provided for the embodiment of the present application, and the operating device 900 shown in fig. 9 includes: a controller 901 and a transceiver 902, the transceiver 902 being used for supporting the transmission of signals between the operation device 900 and the pulse signal source and/or the phase change memory unit, for example, to implement the function of the pulse applying module 801 in the embodiment shown in fig. 8, the controller 901 may be used to implement the function of the determining module 802 in the embodiment shown in fig. 8. The controller 901 and the transceiver 902 are communicatively connected, for example, by a bus. The operating device 900 may also include a memory 903. The memory 903 is used for storing program codes and data for the operating device 900 to execute, and the controller 901 is used for executing application program codes stored in the memory 903 to realize the various modules of the operating device provided by the embodiment shown in fig. 8.

It should be noted that, in practical applications, the operation device may include one or more controllers, and the structure of the operation device 900 is not limited to the embodiment of the present application.

The controller 901 may be a Central Processing Unit (CPU), a Network Processor (NP), a hardware chip, or any combination thereof. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.

The memory 903 may include volatile memory (volatile memory), such as Random Access Memory (RAM); the memory 903 may also include a non-volatile memory (non-volatile memory), such as a read-only memory (ROM), a flash memory (flash memory), a Hard Disk Drive (HDD), or a solid-state drive (SSD); the memory 903 may also comprise a combination of memories of the kind described above.

Optionally, the controller 901 executes the program codes and data in the memory 903 to perform the following specific operations: sequentially applying a first pulse and a second pulse to the first electrode, wherein the first pulse and the second pulse are respectively used for adjusting the resistance state of the phase change memory cell; wherein the polarity of the first pulse is opposite to the polarity of the second pulse. The first pulse and the second pulse are received through transceiver 902.

In one possible implementation, the first pulse is a positive-going pulse, and the second pulse is a negative-going pulse;

In a possible implementation scheme, when the first pulse is a plurality of pulses, the amplitudes of the plurality of pulses are different and the pulse widths are different, or the amplitudes of the plurality of pulses are the same and the pulse widths are different, or the amplitudes of the plurality of pulses are different and the pulse widths are the same, or the amplitudes of the plurality of pulses are the same and the pulse widths are the same;

In one possible implementation, the first pulse is used to adjust the resistance state of the phase change memory cell to a first state; the second pulse is used for adjusting the resistance state of the phase change memory cell from the first state to a second state.

In one possible implementation, the first pulse is one pulse, and the second pulse is one pulse;

under the condition that the first state is the low impedance state and the second state is a first target impedance state, the amplitude of the first pulse is smaller than that of the second pulse, and the pulse width of the first pulse is larger than that of the second pulse;

under the condition that the first state is the high impedance state and the second state is a second target impedance state, the amplitude of the first pulse is larger than that of the second pulse, and the pulse width of the first pulse is smaller than that of the second pulse;

wherein the first target resistance state is any one of the high resistance state and the at least one intermediate resistance state; the second target resistance state is any one of the low resistance state and the at least one intermediate resistance state.

In one possible implementation, the first pulse is M pulses, and the second pulse is N pulses; the method further comprises the following steps:

if the resistance value corresponding to the phase change memory cell read after applying the M pulses is within the resistance value range corresponding to the first state, the controller 901 determines to adjust the resistance value state of the phase change memory cell to the first state, where M is a positive integer;

if the resistance value corresponding to the phase change memory cell read after applying the N pulses is within the resistance value range corresponding to the second state, the controller 901 determines to adjust the resistance value state of the phase change memory cell to the second state, where N is a positive integer.

In one possible implementation, the first electrode is an upper electrode and the second electrode is a lower electrode;

or, the first electrode is a lower electrode, and the second electrode is an upper electrode.

The detailed processes performed by the controller 901 can be described in detail with reference to the embodiments shown in fig. 2a to fig. 7c, and are not described herein again.

The embodiment of the present application further provides a chip, which includes a processor and a memory, where the memory is used to store a computer program, the processor is used to call and run the computer program from the memory, and the computer program is used to implement the above-mentioned operation method for the phase change memory cell.

In the embodiment of the present application, a computer storage medium may be provided, which may be used to store computer software instructions for the operating device, and which include a program designed for the operating device in the above-described embodiment. The storage medium includes, but is not limited to, flash memory, hard disk, solid state disk.

The embodiment of the present application further provides a computer program product, which when executed by a computing device can execute the above-mentioned method for operating a phase change memory cell.

Please refer to fig. 10, which provides a schematic structural diagram of a terminal device according to an embodiment of the present application. The terminal device 1000 shown in fig. 10 includes a processor 1001, a transceiver 1004, a memory 1003, a controller 1005, an array 1006 of phase change memory cells, and a pulse signal source 1007.

The controller 1005 may be used to implement the function of the determining module 802 in the embodiment shown in fig. 8, and the controller 1005 applies pulses to the phase change memory cell array 1006 through the pulse signal source 1007 to implement the function of the pulse applying module 801 in the embodiment shown in fig. 8.

Processor 1001, controller 1005, array of phase change memory cells 1006, pulse signal source 1007, and transceiver 1002 are communicatively coupled, such as by a bus. The terminal device 1000 may further include a memory 1003. The memory 1003 is used for storing program codes and data for the terminal device 1000 to execute, and the controller 1005 is used for executing the application program codes stored in the memory 1003 to realize the respective modules of the operating device provided by the embodiment shown in fig. 8.

The processor 1001 may be a CPU, NP, hardware chip or any combination thereof. The hardware chip may be an ASIC, PLD, or a combination thereof. The PLD may be a CPLD, an FPGA, a GAL, or any combination thereof.

Memory 1003 may include volatile memory, such as RAM; the memory 1003 may also include non-volatile memory, such as ROM, flash memory, a hard disk, or a solid state disk; the memory 1003 may also include a combination of the above types of memories.

A controller 1005 for controlling a read operation, an erase operation, a write operation, etc. of the phase change memory cell array. The controller may also be a processor, and in combination with the processor 1001 in the terminal device 1000, the functions of the processor 1001 and the controller 1005 are realized later.

Phase change memory cell array 1006 includes a plurality of phase change memory cells, each of which may implement binary storage or multivalue storage, i.e., the phase change memory cells include two or more resistance states.

It should be noted that, in practical applications, the terminal device may include one or more processors, and the structure of the terminal device 1000 does not constitute a limitation to the embodiments of the present application.

The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

It should be understood by those of ordinary skill in the art that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of the processes should be determined by their functions and inherent logic, and should not limit the implementation process of the embodiments of the present application.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

Claims

A method of operating a phase change memory cell comprising a first electrode, a phase change layer, and a second electrode, the second electrode being grounded, the method comprising:

sequentially applying a first pulse and a second pulse to the first electrode, wherein the first pulse and the second pulse are respectively used for adjusting the resistance state of the phase change memory cell;

wherein the polarity of the first pulse is opposite to the polarity of the second pulse.
The method of claim 1,

the first pulse is a positive pulse, and the second pulse is a negative pulse;

or, the first pulse is a negative pulse, and the second pulse is a positive pulse.
The method according to claim 1 or 2,

when the first pulse is a plurality of pulses, the plurality of pulses have different amplitudes and different pulse widths, or the plurality of pulses have the same amplitude and different pulse widths, or the plurality of pulses have different amplitudes and the same pulse widths, or the plurality of pulses have the same amplitude and the same pulse widths;

when the second pulse is a plurality of pulses, the plurality of pulses have different amplitudes and different pulse widths, or the plurality of pulses have the same amplitude and different pulse widths, or the plurality of pulses have different amplitudes and the same pulse widths, or the plurality of pulses have the same amplitude and the same pulse widths.
The method according to any one of claims 1 to 3,

the resistance state of the phase change memory unit comprises a high resistance state and a low resistance state; the resistance value of the phase change unit corresponding to the high resistance state is larger than that of the phase change unit corresponding to the low resistance state.
The method of claim 4,

the resistance state of the phase change memory cell further comprises at least one intermediate resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is smaller than that of the phase change unit corresponding to the high resistance state, and the resistance value of the phase change unit corresponding to the intermediate resistance state is larger than that of the phase change unit corresponding to the low resistance state.
The method of claim 5, wherein the first pulse is used to adjust the resistance state of the phase change memory cell to a first state; the second pulse is used for adjusting the resistance state of the phase change memory cell from the first state to a second state.
The method of claim 6, wherein the first pulse is one pulse and the second pulse is one pulse;

under the condition that the first state is the low impedance state and the second state is a first target impedance state, the amplitude of the first pulse is smaller than that of the second pulse, and the pulse width of the first pulse is larger than that of the second pulse;

under the condition that the first state is the high impedance state and the second state is a second target impedance state, the amplitude of the first pulse is larger than that of the second pulse, and the pulse width of the first pulse is smaller than that of the second pulse;

wherein the first target resistance state is any one of the high resistance state and the at least one intermediate resistance state; the second target resistance state is any one of the low resistance state and the at least one intermediate resistance state.
The method of claim 5 or 6, wherein the first pulse is M pulses and the second pulse is N pulses; the method further comprises the following steps:

if the resistance value corresponding to the phase change memory cell read after the M pulses are applied is in the resistance value range corresponding to the first state, determining to adjust the resistance value state of the phase change memory cell to the first state, wherein M is a positive integer;

and if the resistance value corresponding to the phase change memory cell read after the N pulses are applied is within the resistance value range corresponding to the second state, determining to adjust the resistance value state of the phase change memory cell to the second state, wherein N is a positive integer.
The method according to any one of claims 1 to 8,

the first electrode is an upper electrode, and the second electrode is a lower electrode;

or, the first electrode is a lower electrode, and the second electrode is an upper electrode.
An operating device for operating a phase change memory cell, the phase change memory cell comprising a first electrode, a phase change layer, and a second electrode, the second electrode being grounded, comprising:

the pulse applying module is used for sequentially applying a first pulse and a second pulse to the first electrode, and the first pulse and the second pulse are respectively used for adjusting the resistance state of the phase change memory cell;

wherein the polarity of the first pulse is opposite to the polarity of the second pulse.
The apparatus of claim 10,

the first pulse is a positive pulse, and the second pulse is a negative pulse;

or, the first pulse is a negative pulse, and the second pulse is a positive pulse.
The apparatus of claim 10 or 11,

when the first pulse is a plurality of pulses, the plurality of pulses have different amplitudes and different pulse widths, or the plurality of pulses have the same amplitude and different pulse widths, or the plurality of pulses have different amplitudes and the same pulse widths, or the plurality of pulses have the same amplitude and the same pulse widths;

when the second pulse is a plurality of pulses, the plurality of pulses have different amplitudes and different pulse widths, or the plurality of pulses have the same amplitude and different pulse widths, or the plurality of pulses have different amplitudes and the same pulse widths, or the plurality of pulses have the same amplitude and the same pulse widths.
The apparatus according to any one of claims 10 to 12,

the resistance state of the phase change memory unit comprises a high resistance state and a low resistance state; the resistance value of the phase change unit corresponding to the high resistance state is larger than that of the phase change unit corresponding to the low resistance state.
The apparatus of claim 13,

the resistance state of the phase change memory cell further comprises at least one intermediate resistance state; the resistance value of the phase change unit corresponding to the intermediate resistance state is smaller than that of the phase change unit corresponding to the high resistance state, and the resistance value of the phase change unit corresponding to the intermediate resistance state is larger than that of the phase change unit corresponding to the low resistance state.
The apparatus of claim 14, wherein the first pulse is configured to adjust the resistance state of the phase change memory cell to a first state; the second pulse is used for adjusting the resistance state of the phase change memory cell from the first state to a second state.
The apparatus of claim 15, wherein the first pulse is one pulse and the second pulse is one pulse;

under the condition that the first state is the high impedance state and the second state is a first target impedance state, the amplitude of the first pulse is larger than that of the second pulse, and the pulse width of the first pulse is smaller than that of the second pulse;

under the condition that the first state is the low impedance state and the second state is a second target impedance state, the amplitude of the first pulse is smaller than that of the second pulse, and the pulse width of the first pulse is larger than that of the second pulse;

wherein the first target resistance state is any one of the low resistance state and the at least one intermediate resistance state; the second target resistance state is any one of the high resistance state and the at least one intermediate resistance state.
The apparatus of claim 15, wherein the first pulse is M pulses and the second pulse is N pulses; the device further comprises:

the determining module is used for determining to adjust the resistance value state of the phase change memory cell to a first state if the resistance value corresponding to the phase change memory cell read after the M pulses are applied is within the resistance value range corresponding to the first state, wherein M is a positive integer;

the determining module is further configured to determine to adjust the resistance state of the phase change memory cell to the second state if the resistance value corresponding to the phase change memory cell read after the N pulses are applied is within the resistance value range corresponding to the second state, where N is a positive integer.
The apparatus of any one of claims 10-17,

the first electrode is an upper electrode, and the second electrode is a lower electrode;

or, the first electrode is a lower electrode, and the second electrode is an upper electrode.
A chip, characterized in that it comprises a controller and a memory for storing a computer program, the controller being adapted to call up and run the computer program from the memory, the computer program being adapted to perform the method according to any of claims 1-9.
A terminal device, characterized in that the terminal device comprises a processor, a memory, at least one phase change memory cell, the phase change memory cell comprising a first electrode, a phase change layer and a second electrode, the second electrode being connected to ground, the memory being adapted to store a computer program, the processor being adapted to retrieve and run the computer program from the memory, the processor being adapted to perform the method according to any of claims 1-9.