CN112038358A - Display device - Google Patents
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- CN112038358A CN112038358A CN202011075497.5A CN202011075497A CN112038358A CN 112038358 A CN112038358 A CN 112038358A CN 202011075497 A CN202011075497 A CN 202011075497A CN 112038358 A CN112038358 A CN 112038358A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a display device including: a first substrate; a first insulating layer disposed on the first substrate; the first thin film transistor unit is arranged on the first substrate; the second thin film transistor unit is arranged on the first substrate; and a third thin film transistor unit arranged on the first substrate. The first thin film transistor unit includes: the first semiconductor layer is arranged between the first substrate and the first insulating layer. The second thin film transistor unit includes: a second semiconductor layer disposed on the first insulating layer and the first semiconductor layer. The third thin film transistor unit includes: a third semiconductor layer disposed between the first substrate and the first insulating layer. In addition, the second semiconductor layer is electrically connected with the third semiconductor layer through a metal layer.
Description
This application is a divisional application, the application number of the parent: 201611089421.1, filing date: 2016, 12, 1, name: a display device.
Technical Field
The present invention relates to a display device, and more particularly, to a display device including both a low temperature polysilicon thin film transistor unit and a metal oxide thin film transistor unit.
Background
With the continuous progress of display technology, all display panels are developed to be small, thin and light, so that the mainstream display devices in the market are developed into thin displays such as liquid crystal display panels, organic light emitting diode display panels or inorganic light emitting diode display panels from the conventional cathode ray tubes. Among them, the thin display can be applied to a large number of fields, such as display panels used in daily life, for example, mobile phones, notebook computers, video cameras, music players, mobile navigation devices, and televisions, and most of them are used.
Although liquid crystal display devices or organic light emitting diode display devices are commercially available display devices, and particularly, the technology of liquid crystal display devices is mature, as the display devices are developed and the display quality requirements of consumers for the display devices are increased, the manufacturers are not forced to develop display devices with higher display quality.
The tft structure on the display area may be a polysilicon tft with high carrier mobility or a metal oxide tft with low leakage, and the current display cannot combine the two tfts because the two processes may affect each other, which complicates the overall process of the display device (e.g., requires more cvd processes). In addition, the organic light emitting diode display device includes at least three tft units in a single pixel unit, which results in a smaller light emitting area and a relatively complicated process for manufacturing the tft substrate. In view of the above, there is still a need to improve the process of the thin film transistor substrate so as to manufacture the thin film transistor substrate having both the polysilicon thin film transistor and the metal oxide thin film transistor by a simplified process.
Disclosure of Invention
The present invention provides a display device including both a low temperature polysilicon thin film transistor cell and a metal oxide thin film transistor cell.
In one embodiment of the present invention, a display device includes: a first substrate; a first thin film transistor unit arranged on the first substrate; a second thin film transistor unit arranged on the first substrate; a first capacitor electrode; a second capacitor electrode; and a display medium layer arranged on the first substrate. Wherein the first thin film transistor includes: a first semiconductor layer comprising silicon; and a first electrode electrically connected to the first semiconductor layer. The second thin film transistor includes: a second semiconductor layer comprising metal oxide; and a second electrode electrically connected to the second semiconductor layer. The first capacitor electrode is electrically connected with the first electrode; the second capacitor electrode is electrically connected with the second electrode, and the second capacitor electrode and the first capacitor electrode are overlapped.
In the foregoing embodiment, the first capacitor electrode is electrically connected to the first electrode, and the second capacitor electrode is electrically connected to the second electrode, so that the tft structure of the display device can be simplified.
In another embodiment of the present invention, there is provided a display device including: a first substrate; a second thin film transistor disposed on the first substrate; a third thin film transistor disposed on the first substrate; and a display medium layer arranged on the first substrate. Wherein the second thin film transistor includes: a second gate; and a second semiconductor layer overlapping the second gate, wherein the second semiconductor comprises a metal oxide. The third thin film transistor includes: a third gate; and a third semiconductor layer overlapping the third gate, wherein the third semiconductor comprises a metal oxide. In addition, the second semiconductor layer is electrically connected with the third semiconductor layer.
In the aforementioned embodiments, the second semiconductor layer and the third semiconductor layer both contain metal oxide and are electrically connected to each other, so as to achieve the purpose of simplifying the second and third thin film transistor structures.
Drawings
Fig. 1 is a schematic cross-sectional view of a display device according to embodiment 1 of the present invention.
Fig. 2A and fig. 2B are equivalent circuit diagrams of different circuit designs of a first pixel of a display device according to embodiment 1 of the invention.
Fig. 3 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 1 of the invention.
Fig. 4 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 2 of the invention.
Fig. 5 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 3 of the invention.
Fig. 6 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 4 of the invention.
Fig. 7 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 5 of the invention.
Fig. 8 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 6 of the present invention.
Fig. 9 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 7 of the present invention.
Fig. 10 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 8 of the invention.
Fig. 11 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 9 of the invention.
Fig. 12 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 10 of the present invention.
Fig. 13 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 11 of the present invention.
Fig. 14 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 12 of the present invention.
Fig. 15 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 13 of the present invention.
Fig. 16 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 14 of the present invention.
Fig. 17 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 15 of the present invention.
Fig. 18 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 16 of the present invention.
Fig. 19 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 17 of the present invention.
Fig. 20 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 18 of the present invention.
Fig. 21 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 19 of the present invention.
Fig. 22 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 20 of the invention.
Fig. 23 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 21 of the present invention.
Fig. 24 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 22 of the present invention.
Fig. 25 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 23 of the present invention.
Fig. 26 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 24 of the present invention.
Fig. 27 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 25 of the present invention.
Fig. 28 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 26 of the present invention.
Fig. 29 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 27 of the present invention.
Fig. 30 is a schematic cross-sectional view of a first pixel and a second pixel of a display device according to embodiment 28 of the invention.
Fig. 31 is a schematic cross-sectional view of a first pixel of a display device according to embodiment 29 of the present invention.
Fig. 32 is a schematic cross-sectional view of a first pixel of a display device 30 according to embodiment of the invention.
Description of reference numerals:
11 first substrate
12 buffer layer
122 buffer layer
13b third active layer
132, 135 channel region
133' fourth capacitive electrode
151 first gate
153 second grid
155 first touch signal line
156 second touch signal line
16a bottom second insulating layer
161 fourth insulating layer
171 third electrode
172' first capacitor electrode
173 connecting part
18 first insulating layer
191 a second semiconductor layer
193 second source region
195 second drain region
196 third active region
198 capacitor forming region
201 fourth electrode
202' second capacitive electrode
203 fifth electrode
204, 231, 281 through hole
211 opening (not shown)
221 sixth insulating layer
24 pixel definition layer
26 second display electrode
28 touch electrode
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Moreover, the use of ordinal numbers such as "first," "second," etc., in the specification and in the claims to modify a component of a request does not by itself connote any preceding ordinal number of the request component, nor does it denote the order of a particular request component or sequence of such request components or methods of manufacture, but are used merely to distinguish one request component having a certain name from another request component having a same name.
In the present invention, the term "overlapping arrangement" includes a partially or completely overlapping arrangement. Furthermore, the term "exposed" includes partial or complete exposure.
Example 1
Fig. 1 is a top view and a cross-sectional view of the display device of the present embodiment. Wherein, the display device of this embodiment includes: a first substrate 11; a second substrate 2 disposed opposite to the first substrate 11; and a display medium layer 3 disposed between the first substrate 11 and the second substrate 2. In the present embodiment, the first substrate 11 and the second substrate 2 are made of substrate materials such as glass, plastic, flexible material, and thin film; the display medium 3 may be, but not limited to, a liquid crystal layer, an organic light emitting layer, a diode chip array, etc. In the present embodiment and the following embodiments of the present invention, the display device is an organic light emitting diode display device, and the display medium 3 is an organic light emitting layer. In addition, in other embodiments of the present invention, when the display device is an organic light emitting diode display device or a diode chip array display, the second substrate 2 may be optionally not included.
In the display device of the embodiment, a plurality of pixel units are disposed on the first substrate 11; the equivalent circuit diagram of the circuit design of one of the pixel units, i.e. the first pixel unit, can be illustrated in fig. 2A and 2B. In the equivalent circuit diagram shown in fig. 2A, the first pixel includes: a first thin film transistor unit TFT1 as a switching transistor (switch TFT); a second thin film transistor unit TFT2 functioning as a Driving transistor (Driving TFT); a third thin film transistor unit TFT3 as a Reset transistor (Reset TFT); and a capacitor Cst. In another equivalent circuit diagram shown in fig. 2B, the first pixel further includes: a fourth thin film transistor unit TFT4 as a light Emitting control transistor (Emitting TFT); and another capacitance Cst. In the present embodiment and the following embodiments of the present invention, the first TFT1 may be a low temperature polysilicon TFT or a metal oxide TFT, and is preferably a low temperature polysilicon TFT; the second TFT2 can be a metal oxide TFT for better threshold voltage (Vth) stability; the third TFT3 may be a low temperature polysilicon TFT or a metal oxide TFT; and the fourth TFT4 may be a low temperature polysilicon TFT. In this embodiment and the following embodiments of the present invention, the circuit design of the first pixel unit as shown in fig. 2A is illustrated as an equivalent circuit diagram.
Fig. 3 is a schematic cross-sectional view of a first pixel of the present embodiment. First, a first substrate 11 is provided, and a shielding layer 111 is formed on the first substrate 11, wherein the region where the first semiconductor layer 13a of the first TFT1 is to be formed is defined. The material of the shielding layer 111 can be any material with light shielding property, such as metal, black matrix, etc.; in the present embodiment, the material of the shielding layer 111 is a metal (such as molybdenum metal, chromium metal, titanium metal, or other refractory metals). Next, a buffer layer 12 is formed on the first substrate 11 and the shielding layer 111. The material of the buffer layer 12 may be silicon oxide, silicon nitride, or a stacked structure of silicon nitride and silicon oxide. Then, a first semiconductor layer 13a is disposed on the buffer layer 12 as a first active layer, which is a low-temperature polysilicon layer that converts the amorphous silicon layer into a polysilicon layer through a laser sintering process and a channel doping process. The first semiconductor layer 13a includes a source region 131, a channel region 132 and a drain region 133. Next, a first gate insulating layer 14 is formed on the first semiconductor layer 13a, wherein the material of the first gate insulating layer may be silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide. Forming a first gate 151 and a third gate 152, which may be single-layer or multi-layer, on the first gate insulating layer 14, and made of a metal such as Cu, Ti, or Al, or a metal alloy; the first gate 151 and the third gate 152 are electrically connected to a scan line (not shown). A second insulating layer 16, which may be silicon nitride, silicon oxide or a stacked structure of silicon nitride and silicon oxide, is formed on the first gate insulating layer 14. A first conductive layer including a first electrode 172 and a first capacitor electrode 172' and a third electrode 171, which are made of a metal material such as Cu or Al, are formed on the second insulating layer 16. Thus, the first TFT1 (shown in fig. 2A) of the present embodiment is completed.
Next, a first insulating layer 18 is formed on the first electrode 172, the first capacitor electrode 172' and the third electrode 171, wherein the material of the first insulating layer may be silicon nitride, silicon oxide or a stacked structure of silicon nitride and silicon oxide. A second semiconductor layer 191 and a third semiconductor layer 192 are formed on the first insulating layer 18, wherein the second semiconductor layer 191 and the third semiconductor layer 192 are made of metal oxide, such as zinc oxide based metal oxide, for example: IGZO, ITZO, and the like; in this embodiment and the following embodiments of the present invention, when the material of the second semiconductor layer 191 and the third semiconductor layer 192 is a zinc oxide-based metal oxide, it is IGZO. A second conductive layer including a second electrode 202, a second capacitor electrode 202', and a fourth electrode 201 is formed over the second semiconductor layer 191 and the third semiconductor layer 192, and the second conductive layer further includes a fifth electrode 203. The second conductive layer can be made of a metal material such as Cu or Al. Thus, the second TFT2 (shown in fig. 2A) and the third TFT3 (shown in fig. 2A) of the present embodiment are completed.
Then, a planarization layer 21 is formed on the second conductive layer, and an organic layer 22 is optionally formed on the planarization layer 21. Finally, a first display electrode 23, a pixel defining layer 24, an organic light emitting layer 25 and a second display electrode 26 are sequentially formed on the organic layer 22, and the first display electrode 23, the organic light emitting layer 25 and the second display electrode 26 form the organic light emitting diode unit of the present embodiment; wherein the first display electrode 23 is electrically connected to the second electrode 202 of the second TFT 2. Here, the first display electrode 23 and the second display electrode 26 may be transparent electrodes or semitransparent electrodes. The transparent electrode may be a transparent oxide electrode (TCO electrode), such as an ITO electrode or an IZO electrode; the translucent electrode can be a metal film electrode, such as a magnesium-silver alloy film electrode, a gold film electrode, a platinum film electrode, an aluminum film electrode, and the like. In addition, if necessary, at least one of the first display electrode 23 and the second display electrode 26 may be a composite electrode of a transparent electrode and a translucent electrode, such as: TCO electrode and platinum film electrode. Here, the organic light emitting diode device including the first display electrode 23, the organic light emitting layer 25 and the second display electrode 26 is only used as an example, but the present invention is not limited thereto; other organic light emitting diode elements may be applied to the organic light emitting diode display device of the present invention, for example: organic light emitting diode devices including electron transport layers, electron injection layers, hole transport layers, hole injection layers, and other layers that facilitate electron-hole transport bonding are applicable to the present invention.
Through the foregoing processes, the organic light emitting diode display device of the present embodiment is completed. As shown in fig. 2A and fig. 3, one of the pixels, i.e., the first pixel, of the display device of the present embodiment includes: a first substrate 11; a first thin film transistor cell TFT1 disposed on the first substrate 11; a second thin film transistor unit TFT2 disposed on the first substrate 11; a first capacitor electrode 172'; a second capacitor electrode 202'; and a display medium layer (i.e., an organic light emitting diode unit including the first display electrode 23, the organic light emitting layer 25 and the second display electrode 26) disposed on the first substrate 11. Wherein the first thin film transistor unit TFT1 includes: a first semiconductor layer 13a comprising silicon; and a first electrode 172 electrically connected to the first semiconductor layer 13 a. The second thin film transistor unit TFT2 includes: a second semiconductor layer 191 comprising metal oxide; and a second electrode 202 electrically connected to the second semiconductor layer 191 of the second semiconductor layer. In addition, in the display device of the embodiment, the first capacitor electrode 172 'is electrically connected to the first electrode 172, the second capacitor electrode 202' is electrically connected to the second electrode 202, and the first capacitor electrode 172 'and the second capacitor electrode 202' are overlapped to form a first capacitor Cst 1.
As shown in fig. 2A and fig. 3, in the display device of the present embodiment, the first capacitor electrode 172 'is connected to the first electrode 172, and the second capacitor electrode 202' is connected to the second electrode 202. In addition, the first capacitor Cst1 is formed by overlapping the first capacitor electrode 172 'and the second capacitor electrode 202', and the size of the first capacitor Cst1 (i.e. the capacitor Cst shown in fig. 2A) can be controlled by controlling the thickness of the first insulating layer 18.
In addition, as shown in fig. 3, in the display device of the present embodiment, the first electrode 172 of the first TFT1 is overlapped with the second semiconductor layer 191, so that a portion of the first electrode 172 can be used as a second gate electrode of the second TFT 2.
As shown in fig. 2A and fig. 3, in the display device of the present embodiment, the first electrode 172 of the first TFT1 is used as the second gate of the second TFT2, so that the first TFT1 and the second TFT2 can be electrically connected, the processes of the first TFT1 and the second TFT2 can be simplified, and the area occupied by the first TFT1 and the second TFT2 on the first substrate 11 can be reduced to improve the aperture ratio.
In addition, the display device of the present embodiment further includes a third TFT3 disposed on the first substrate 11 and including: a third semiconductor layer 192 comprising a metal oxide (e.g., IGZO layer); and a second extension electrode 202 ″ and a fifth electrode 203 disposed on the third semiconductor layer 192 and electrically connected to the third semiconductor layer 192. Wherein the second extension electrode 202 "is connected to the second capacitive electrode 202'.
As shown in fig. 2A and fig. 3, in the display device of the present embodiment, the second electrode 202, the second extension electrode 202 ″ and the second capacitor electrode 202' are integrally formed to simultaneously serve as electrodes of the second TFT2 and the third TFT3, so as to be electrically connected to each other.
Example 2
Fig. 4 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 1, except that the first conductive layer (including the first electrode 172 and the first capacitor electrode 172') on the second insulating layer 16 further includes a connecting portion 173 electrically connected to the third gate 152. Although the first electrode 172 or the first capacitor electrode 172 'of the first conductive layer is not directly connected to the third gate 152 in the cross-sectional view shown in fig. 4, the first electrode 171 or the first capacitor electrode 172 may be directly connected to the connection portion 173 in other regions of the display device, so as to achieve the purpose of electrically connecting the first electrode 172 or the first extension electrode 172' to the third gate 152. By electrically connecting the first electrode 172 or the first extension electrode 172' of the first TFT1 and the third gate 152 of the third TFT3, the charging capability of the third TFT3 can be further improved.
Example 3
Fig. 5 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 2, except that a third capacitor electrode 154 is formed at the same time as the first gate electrode 151 and the third gate electrode 152 are formed. Therefore, in the present embodiment, the display device further includes a third conductive layer including the first gate 151 and the third capacitor electrode 154. The second insulating layer 16 is disposed between the third capacitor electrode 154 and the first conductive layer (including the first electrode 172 and the first capacitor electrode 172 '), and the third capacitor electrode 154 and the first capacitor electrode 172' of the first conductive layer are overlapped to form a second capacitor Cst 2. The second capacitor electrode 202' is electrically connected to the third capacitor electrode 154 through a via hole to provide a voltage to the third capacitor electrode 154. Therefore, as shown in fig. 2A and fig. 5, in the present embodiment, the display device further includes a second capacitor Cst2, the second capacitor Cst2 has a third capacitor electrode 154, and the first thin film transistor TFT1 further includes a first gate electrode 151, the first gate electrode 151 corresponds to the first semiconductor layer 13a, and a first gate insulating layer 14 is disposed between the first gate electrode 151 and the first semiconductor layer 13 a; the third capacitor electrode 154 and the first gate 151 are directly disposed on the same surface of the first gate insulating layer 14 and directly contact with the same surface, so that the third capacitor electrode 154 and the first gate 151 can be located on the same plane. In addition, the third TFT3 further includes a third gate 152, wherein the third capacitor electrode 154 and the third gate 152 are directly disposed on the same surface of the first gate insulating layer 14 and directly contact with the same surface, so that the third capacitor electrode 154 and the third gate 152 can be located on the same plane.
Therefore, in the embodiment, the display device further includes a second capacitor Cst2 formed by the overlapping arrangement of the third capacitor electrode 154 and the first capacitor electrode 172 ', in addition to the first capacitor Cst1 formed by the overlapping arrangement of the first capacitor electrode 172 ' and the second capacitor electrode 202 '.
Example 4
Fig. 6 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of the present embodiment is similar to embodiment 3 except that the drain region 133 of the first semiconductor layer 13a is extended so that the drain region 133 of the first semiconductor layer 13a is disposed to overlap with the third capacitor electrode 154; therefore, the region extended from the drain region 133 of the first semiconductor layer 13a can be used as a fourth capacitor electrode 133'. Therefore, in the display device of the present invention, the third insulating layer (i.e., the first gate insulating layer 14) is disposed between the third capacitor electrode 154 and the first semiconductor layer 13a, wherein the fourth capacitor electrode 133' in the region where the drain region 133 of the first semiconductor layer 13a extends is further overlapped with the third capacitor electrode 154 to form a third capacitor Cst 3. Therefore, the display device of the present embodiment may further include a third capacitor Cst3, wherein the third capacitor Cst3 includes a fourth capacitor electrode 133', and the material of the fourth capacitor electrode 133 is the same as the material of the first semiconductor layer 13a and is electrically connected to each other.
Therefore, in this embodiment, the display device further includes a third capacitor Cst3 formed by overlapping the third capacitor electrode 154 and the fourth capacitor electrode 133', in addition to the first capacitor Cst1 and the second capacitor Cst2 in embodiment 3.
Example 5
Fig. 7 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of the present embodiment is similar to embodiment 1 except for the following points. As shown in fig. 2A and 7, in the display device of embodiment 1, the third TFT3 is a metal oxide TFT, and in this embodiment, the third TFT3 is a low temperature polysilicon TFT. In the process, the shielding layer 112 is formed simultaneously with the shielding layer 111 and in a region where the third semiconductor layer 13b of the third TFT unit TFT3 is to be formed. The third semiconductor layer 13b of the third TFT3, which includes a source region 134, a channel region 135 and a drain region 136, is also formed at the same time as the first semiconductor layer 13a of the first TFT 1. When the first conductive layer is formed, a third source 174 and a third drain 175 are also formed, and the third source 174 and the third drain 175 are electrically connected to the source region 134 and the drain region 136 of the third semiconductor layer 13b, respectively. In addition, the second capacitor electrode 202' is also electrically connected to the third source 174 through the via hole.
Example 6
Fig. 8 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to that of embodiment 5, except that a third capacitor electrode 154 is formed at the same time as the first gate electrode 151 and the third gate electrode 152 are formed. The second insulating layer 16 is disposed between the third capacitor electrode 154 and the first conductive layer (including the first electrode 172 and the first capacitor electrode 172 '), and the third capacitor electrode 154 and the first capacitor electrode 172' of the first conductive layer are overlapped to form a second capacitor Cst 2. The second capacitor electrode 202' is electrically connected to the third capacitor electrode 154 through a via hole to provide a voltage to the third capacitor electrode 154. The detailed design of the second capacitor Cst2 is the same as that of embodiment 3, and therefore, the detailed description thereof is omitted.
Example 7
Fig. 9 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of the present embodiment is similar to embodiment 6 except that the drain region 133 of the first semiconductor layer 13a is extended so that the drain region 133 of the first semiconductor layer 13a is disposed to overlap with the third capacitor electrode 154; therefore, the region extended from the drain region 133 of the first semiconductor layer 13a can be used as a fourth capacitor electrode 133'. Therefore, in the display device of the present invention, the third insulating layer (i.e., the first gate insulating layer 14) is disposed between the third capacitor electrode 154 and the first semiconductor layer 13a, wherein the fourth capacitor electrode 133' in the region where the drain region 133 of the first semiconductor layer 13a extends is further overlapped with the third capacitor electrode 154 to form a third capacitor Cst 3. The detailed design of the third capacitor Cst3 is the same as that of embodiment 3, and therefore, the detailed description thereof is omitted.
Example 8
Fig. 10 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The equivalent circuit diagram of the circuit design of the tft unit in the first pixel of this embodiment is the same as that shown in fig. 2A, and therefore, the details thereof are not repeated herein.
As shown in fig. 2A and fig. 10, first, a first substrate 11 is provided, and shielding layers 111, 112, and 113 are formed on the first substrate 11 in regions where active layers of thin film transistors are to be formed. Next, a buffer layer 12 is formed on the first substrate 11 and the shielding layers 111, 112, and 113. Then, a first semiconductor layer 13a, which is a low temperature polysilicon layer and includes a source region 131, a channel region 132 and a drain region 133, is disposed on the buffer layer 12. Next, a first gate insulating layer 14 is formed on the first semiconductor layer 13 a. Forming a second semiconductor layer, which is a metal oxide layer including a second source region 193, a second active region 194, and a second drain region 195, on the first gate insulating layer 14, wherein the second thin film transistor unit TFT2 and the third thin film transistor unit TFT3 are formed in advance; and a third semiconductor layer, which is also a metal oxide layer, including a third source region 195', a third active region 196, and a third drain region 197. Wherein the second semiconductor layer is connected with the third semiconductor layer. Then, a second gate insulating layer 181 (made of silicon oxide), a first gate 151, a second gate 153 and a third gate 152 are sequentially formed on the channel region 132, the second active region 194 and the third active region 196 of the first semiconductor layer 13 a; a second insulating layer 16 made of silicon nitride is formed on the second source region 193, the second drain region 195, the third source region 195', the third drain region 197, the first gate 151, the second gate 153 and the third gate 152. Then, a third electrode 171 electrically connected to the source region 131 of the first semiconductor layer 13a and a first electrode 172 electrically connected to the drain region 133 are formed; a second electrode 201 electrically connected to the second source region 193, a second electrode 202 electrically connected to the second drain region 195 and the third source region 195', and a fifth electrode 203 electrically connected to the third drain region 197 are also formed. In the present embodiment, a connection electrode 203a is further formed between the third drain region 197 and the fifth electrode 203; however, the connecting electrode 203a is selectively disposed, and in other embodiments of the present invention, the display device may not include the connecting electrode 203a, depending on the design. Through the above processes, the first TFT1, the second TFT2 and the third TFT3 of the present embodiment are completed.
Finally, as in embodiment 1, a planarization layer 21 is formed on the third electrode 171, the first electrode 172, the first capacitor electrode 172', the fourth electrode 201, the second electrode 202, and the fifth electrode 203, and then a first display electrode 23, a pixel defining layer 24, an organic light emitting layer 25, and a second display electrode 26 are sequentially formed to form the organic light emitting diode unit of this embodiment; wherein the first display electrode 23 is electrically connected to the second electrode 202 of the second TFT 2.
Through the foregoing processes, the organic light emitting diode display device of the present embodiment is completed. As shown in fig. 2A and 10, the display device of the present embodiment includes: a first substrate 11; (ii) a A second thin film transistor unit TFT2 disposed on the first substrate 11; a third TFT3 disposed on the first substrate 11; and a display medium layer including a first display electrode 23, an organic light emitting layer 25 and a second display electrode 26 disposed on the first substrate 11. Wherein the second thin film transistor unit TFT2 includes: a second gate 153; and a second semiconductor layer (including a second source region 193, a second active region 194 and a second drain region 195), wherein the second active region 194 of the second semiconductor layer overlaps the second gate 153, and wherein the second semiconductor comprises a metal oxide. The third thin film transistor unit TFT3 includes: a third gate 152; and a third semiconductor layer (including a third source region 195', a third active region 196, and a third drain region 197), the third active region 196 of the third semiconductor layer overlapping the third gate 152, wherein the third semiconductor layer comprises metal oxide, and the second semiconductor layer and the third semiconductor layer are electrically connected to each other by being connected. In addition, the display device of the present embodiment further includes: a shielding layer 111 disposed between the first semiconductor layer 13a and the first substrate 11 and overlapping the first semiconductor layer 13 a; and a shielding layer 112, 113 overlapping the second semiconductor layer including the second active region 194 and the third active region 196, respectively.
As shown in fig. 2A and 10, in the display device of the present embodiment, the second semiconductor layer (including the second source region 193, the second active region 194, and the second drain region 195) is connected to the third semiconductor layer (including the third source region 195 ', the third active region 196, and the third drain region 197), and the second insulating layer 16 made of silicon nitride is formed above the second source region 193, the second drain region 195, the third source region 195', and the third drain region 197, so that the silicon nitride can supplement hydrogen to these regions to improve the conductivity of these regions; accordingly, the second source region 193, the second active region 194, and the second drain region 195 of the second TFT2, and the third source region 195', the third active region 196, and the third drain region 197 of the third TFT3 are simultaneously formed using a single metal oxide layer.
Although the first capacitor electrode 172 'is not directly connected to the second gate electrode 153 in the cross-sectional view shown in fig. 10, the first capacitor electrode 172' may be directly connected to the second gate electrode 153 in other regions of the display device, so as to electrically connect the first TFT1 and the second TFT 2.
In addition, in the display device of the present embodiment, the display medium layer includes an organic light emitting diode unit, which at least includes the first display electrode 23, the organic light emitting layer 25 and the second display electrode 26. The organic light emitting diode unit is disposed above the second TFT2 and electrically connected to the second TFT2, and more specifically, electrically connected to the second drain and the second extension electrode 202 on the third source region 195.
Furthermore, the display device of the present embodiment further includes a first TFT1 and a planarization layer 21. The first thin film transistor unit TFT1 is disposed on the first substrate 11 and includes: a first semiconductor layer 13a comprising silicon; and a first electrode 172 electrically connected to the first semiconductor layer 13. In addition, the planarization layer 21 is disposed between the first conductive layer and the organic light emitting diode unit, and the first capacitor electrode 172' of the first conductive layer and the first display electrode 23 of the organic light emitting diode unit are overlapped to form a fourth capacitor Cst 4.
Example 9
Fig. 11 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of the present embodiment is similar to embodiment 8 except for the following points. In the present embodiment, the second gate insulating layer 181 is not disposed on the channel region 132 of the first semiconductor layer 13 a. The first gate insulating layer 14 is provided only on the first thin film transistor region. In addition, the second gate insulating layer 181 is disposed on a portion of the second source region 193, the second drain region 195, the third source region 195', and the third drain region 197 in addition to the second active region 194 and the third active region 196; in other words, the second gate insulating layer 181 is disposed on almost the entire metal oxide layer except for the regions connected to the third electrode 201, the second electrode 202, and the fifth electrode 203. Furthermore, the connection electrode 203a is not disposed between the third drain region 197 and the fifth electrode 203.
Example 10
Fig. 12 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of the present embodiment is similar to embodiment 8 except for the following points. In this embodiment, the shielding layer 113 is disposed on the second tft disposing region and also overlaps the first capacitor electrode 172' of the first conductive layer. Since the shielding layer 113 is made of metal, it can be used as a fifth capacitor electrode, and forms a sixth capacitor Cst6 with the first capacitor electrode 172'. Here, the buffer layer 12 disposed between the shielding layer 113 and the second drain region 195 and the third source region 195 'of the metal oxide layer further has a contact hole 121, and the second drain region 195 and the third source region 195' are electrically connected to the shielding layer 113 through the contact hole 121 to provide a voltage to the shielding layer 113. Therefore, the display device of the present embodiment further includes a buffer layer 12 disposed between the shielding layer 113 and the second semiconductor layer (the second source region 193, the second active region 194, and the second drain region 195) and the third semiconductor layer (the third source region 195 ', the third active region 196, and the third drain region 197), wherein the buffer layer 12 has a contact hole 121, and the second drain region 195 of the second semiconductor layer and the third source region 195' of the third semiconductor layer are electrically connected to the shielding layer 113 through the contact hole 121.
Example 11
Fig. 13 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 9 except for the following points. In this embodiment, the shielding layer 113 is disposed on the second tft disposing region and also overlaps the first capacitor electrode 172' of the first conductive layer. Since the shielding layer 113 is made of metal, a sixth capacitor Cst6 can be formed with the first capacitor electrode 172'. Here, the buffer layer 12 disposed between the shielding layer 113 and the second drain region 195 and the third source region 195 'of the metal oxide layer further has a contact hole 121, and the second drain region 195 and the third source region 195' are electrically connected to the shielding layer 113 through the contact hole 121 to provide a voltage to the shielding layer 113.
Example 12
Fig. 14 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 8 except that a fourth insulating layer 161 is formed on the first tft region after the first gate electrode 151 is formed, and then a second insulating layer 16 and other subsequent layers are formed as in embodiment 8. Here, the material of the fourth insulating layer 161 is silicon oxide.
Example 13
Fig. 15 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 8 in that the first gate insulating layer 14 is provided only on the first thin film transistor region.
Example 14
Fig. 16 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The process of the first thin film transistor unit of the display device of this embodiment is similar to that of embodiment 8, and therefore, the description thereof is omitted. The main difference between this embodiment and embodiment 8 lies in the preparation of the second and third thin film transistor units.
As shown in fig. 16, after the third electrode 171, the first electrode 172 and the first capacitor electrode 172' are formed, a buffer layer 122 is further formed. Forming a second semiconductor layer including a second source region 193, a second active region 194, and a second drain region 195 on the buffer layer 122; a third semiconductor layer is formed on the buffer layer 122, which includes a third source region 195', a third active region 196, and a third drain region 197. Forming a second gate insulating layer 181 on the second semiconductor layer and the third semiconductor layer; a second gate 153 and a third gate 152 are formed on the second gate insulating layer 181. Next, a fifth insulating layer 162 is formed on the second gate electrode 153 and the third gate electrode 152, and then the fourth electrode 201, the second electrode 202, and the fifth electrode 203 are formed, thereby completing the fabrication of the second and third thin film transistor units. Finally, after the planarization layer 21 is formed, an organic light emitting diode unit is fabricated according to the process similar to that of embodiment 8, thereby completing the fabrication of the organic light emitting diode display device of this embodiment.
In the present embodiment, a capacitor forming region 198 is formed at the same time as the second semiconductor layer and the third semiconductor layer, wherein the capacitor forming region 198 overlaps with the first capacitor electrode 172 'of the first conductive layer to form a seventh capacitor Cst7 with the first capacitor electrode 172'. In addition, the second gate 153 is electrically connected to the first electrode 172, and the second gate 153 overlaps the capacitor forming region 198 to form an eighth capacitor Cst 8. Here, although the cross-sectional view shown in fig. 16 shows that the second gate 153 is disconnected and the fourth electrode 201 is inserted therebetween, the second gate 153 is not disconnected and is electrically connected to the first electrode 172 in other regions of the display device of the embodiment, so as to achieve the purpose of electrically connecting the first TFT1 and the second TFT 2. Furthermore, the second gate 153 and the first display electrode 23 of the oled unit may form a ninth capacitor Cst 9.
Example 15
Fig. 17 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 9 except for the following points. In the present embodiment, the metal oxide layer further includes a capacitor forming region 198, and the second gate insulating layer 181 is further disposed on the capacitor forming region 198. In addition, the first capacitor electrode 172' of the first conductive layer and the second gate 153 may be electrically connected to each other through the capacitor forming region 198. Herein, the planarization layer 21 and the second insulating layer 16 are disposed between the capacitor forming region 198 and the first display electrode 23 of the oled unit, and the capacitor forming region 198 overlaps the first display electrode 23 to form a tenth capacitor Cst 10.
Example 16
Fig. 18 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The process of the first thin film transistor unit of the display device of this embodiment is similar to that of embodiment 1, and therefore, the description thereof is omitted. The main difference between this embodiment and embodiment 1 lies in the preparation of the second and third thin film transistor units.
In this embodiment, the design of the second and third tft units is similar to that of embodiment 8, and the second source region 193, the second active region 194 and the second drain region 195 of the second tft unit, and the third source region 195', the third active region 196 and the third drain region 197 of the third tft unit are formed at the same time through a single metal oxide layer. In other words, the display device of the present embodiment further includes a third TFT3 (as shown in fig. 2A), wherein the third TFT3 includes a third semiconductor layer including a third source region 195 ', a third active region 1966 and a third drain region 197, and the second semiconductor layer (including the second source region 193, the second active region 194 and the second drain region 19) and the third semiconductor layer (including the third source region 195', the third active region 196 and the third drain region 197) both include metal oxide and are electrically connected to each other. The fourth electrode 201 of the second conductive layer is disposed on the second source region 193, and the fifth electrode 203 is disposed on the third drain region 197.
In addition, the planarization layer 21 further includes an opening 211 to expose the second drain region 195 and the third source region 195'; a sixth insulating layer 221 is also formed on the planarization layer 21 and in the opening 211. Here, the material of the planarization layer 21 is silicon oxide, and the material of the sixth insulating layer 221 is silicon nitride. Here, the planarization layer 21 is also an insulating layer, which is located on the second semiconductor layer and the third semiconductor layer, and the planarization layer 21 (insulating layer) has a first portion (region where the opening 211 is not formed) and a second portion (opening 211), and the thickness of the first portion is greater than that of the second portion. In addition, the sixth insulating layer 221 contacts the second drain region 195 and the second source region 195 ', increasing the hydrogen content of the second drain region 195 and the third source region 195', and increasing the conductivity thereof.
As in embodiment 1, in the display device of this embodiment, the first capacitor Cst1 is formed by overlapping the first capacitor electrode 172' and the second drain region 195 with the third source region 195 (which can also be regarded as the second capacitor electrode of the second thin film transistor).
Example 17
Fig. 19 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The process of the first thin film transistor unit of the display device of this embodiment is similar to that of embodiment 5, and therefore, the description thereof is omitted. The main difference between this embodiment and embodiment 5 lies in the preparation of the second thin film transistor unit.
In this embodiment, the design of the second thin film transistor unit is similar to that of embodiment 8, and the second source region 193, the second active region 194 and the second drain region 195 of the second thin film transistor unit are formed at the same time mainly through a single metal oxide layer; therefore, the second tft can be the second drain region 195 as the second electrode 202 and the second capacitor electrode 202' in embodiment 5 (as shown in fig. 7). In the present embodiment, the planarization layer 21 further includes an opening 211 to expose the second drain region 195; a sixth insulating layer 221 is also formed on the planarization layer 21 and in the opening 211. Here, the material of the planarization layer 21 is silicon oxide, the material of the sixth insulating layer 221 is silicon nitride, and the sixth insulating layer contacts the second drain region 195, so as to increase the hydrogen content of the second drain region 195 and improve the conductivity thereof.
Example 18
Fig. 20 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The equivalent circuit diagram of the circuit design of the tft unit in the first pixel of this embodiment is the same as that shown in fig. 2A, and therefore, the details thereof are not repeated herein.
As shown in fig. 2A and fig. 20, first, a first substrate 11 is provided, and a shielding layer 111 is formed on a region of the first substrate 11 where an active layer of a thin film transistor is to be formed. Next, a buffer layer 12 is formed on the first substrate 11 and the shielding layer 111. Then, a first semiconductor layer 13a, which is a low temperature polysilicon layer and includes a source region 131, a channel region 132 and a drain region 133, is disposed on the buffer layer 12. Next, a first gate insulating layer 14 is formed on the first semiconductor layer 13a, and a first gate 151, a second gate 153 and a third gate 152 are formed on the first gate insulating layer 14. Then, a second insulating layer 16 is formed on the first gate 151, the second gate 153 and the third gate 152, wherein the second insulating layer 16 includes a bottom second insulating layer 16a and a top second insulating layer 16 b. After the third electrode 171, the first electrode 172 and a first capacitor electrode 172' are formed on the second insulating layer 16, the first thin film transistor of the present embodiment is completed.
In addition, a second semiconductor layer 191 and a third semiconductor layer 192 are formed on the second insulating layer 16, and the materials thereof may be zinc oxide based metal oxide, for example: IGZO, ITZO, and the like. Then, a second conductive layer including a fourth electrode 201, a second electrode 202 and a second capacitor electrode 202' is formed on the second semiconductor layer 191 and the third semiconductor layer 192, and the second conductive layer further includes a second extension electrode 202 ″ and a fifth electrode 203. Then, a sixth insulating layer 221 and a planarization layer 21 are sequentially formed on the second conductive layer. Finally, the organic light emitting diode unit of this embodiment is formed in the same manner as in embodiment 1, thereby completing the fabrication of the display device of this embodiment.
In the present embodiment, the first electrode 172 is electrically connected to the second gate 153. Therefore, in the present embodiment, the second gate 153 may be overlapped with the second capacitor electrode 202' to form the first capacitor Cst 1. In addition, the first capacitor electrode 172' of the first conductive layer is also disposed to overlap the first display electrode 23 of the organic light emitting diode unit to form a fourth capacitor Cst 4. In addition, the second conductive layer serves as an electrode of the third thin film transistor unit in addition to the second thin film transistor unit.
Example 19
Fig. 21 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 18 except for the following points. In this embodiment, a shielding layer 113 is further disposed on the first substrate 11, and is made of metal; and the drain region 133 of the first semiconductor layer 13a is also extended so that the drain region 133 of the first semiconductor layer 13a is disposed to overlap with the third capacitance electrode 154. The second capacitor electrode 202 'is electrically connected to the shielding layer 113 through the via hole, such that the second capacitor electrode 202' provides a voltage to the shielding layer 113, and thus the region extended from the drain region 133 of the first semiconductor layer 13a and the shielding layer 113 form a fifth capacitor Cst 5. Here, the design of the first semiconductor layer 13a is the same as that in embodiment 4 and fig. 6, and therefore, the description thereof is omitted.
Example 20
Fig. 22 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 18 except that the second gate electrode 153 and the third gate electrode 152 are disposed at different positions. In the present embodiment, the second gate 153 and the third gate 152 are disposed between the bottom second insulating layer 16a and the top second insulating layer 16 b.
Example 21
Fig. 23 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of the embodiment is similar to that of embodiment 20 except for the following points. In the present embodiment, a third capacitor electrode 154 is formed at the same time as the first gate electrode 151 is formed. The second capacitor electrode 202 'and the third capacitor electrode 154 can be electrically connected through the via hole, so that the second capacitor electrode 202' can provide a voltage to the third capacitor electrode 154; the second gate 153 and the third capacitor electrode 154 form a second capacitor Cst 2. The design of the third capacitor electrode 154 is the same as that in embodiment 3 and fig. 5, and therefore, the description thereof is omitted.
In addition, the drain region 133 of the first semiconductor layer 13a is also extended so that the region extended by the drain region 133 of the first semiconductor layer 13a can be overlapped with the third capacitor electrode 154; therefore, the region extended from the drain region 133 of the first semiconductor layer 13a can be used as a fourth capacitor electrode 133', and can form a third capacitor Cst3 with the third capacitor electrode 154. The design of the fourth capacitor electrode 133' is the same as that in embodiment 4 and fig. 6, and therefore, the description thereof is omitted. Furthermore, in the embodiment, in the area where the first extension electrode 172 is not disposed on the second gate 153, the second gate 153 may also be disposed to overlap the first display electrode 23 of the oled unit to form a fourth capacitor Cst 4.
Example 22
Fig. 24 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of the embodiment is similar to that of embodiment 20 except for the following points. In the present embodiment, after the bottom second insulating layer 16a is formed, the third electrode 171, the first electrode 172 and the first capacitor electrode 172' of the first thin film transistor are formed first, and then the top second insulating layer 16b is formed; and the first capacitor electrode 172 'is also disposed corresponding to the second semiconductor layer 191 of the second thin film transistor, so that a portion of the first capacitor electrode 172' can also be used as the second gate of the second thin film transistor unit.
Example 23
Fig. 25 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 22 except that a third capacitor electrode 154 is formed at the same time as the first gate electrode 151 is formed. The second capacitor electrode 202 'can be electrically connected to the third capacitor electrode 154 through the via hole, such that the second capacitor electrode 202' can provide a voltage to the third capacitor electrode 154; the first capacitor electrode 172' (also serving as the second gate electrode of the second tft unit) and the third capacitor electrode 154 form a second capacitor Cst 2. The design of the third capacitor electrode 154 is the same as that in embodiment 3 and fig. 5, and therefore, the description thereof is omitted.
In addition, the drain region 133 of the first semiconductor layer 13a is also extended so that the region extended by the drain region 133 of the first semiconductor layer 13a can be overlapped with the third capacitor electrode 154; therefore, the region extended from the drain region 133 of the first semiconductor layer 13a can be used as a fourth capacitor electrode 133', and can form a third capacitor Cst3 with the third capacitor electrode 154. Therefore, the third capacitor Cst3 includes a fourth capacitor electrode 133 ', and a fourth capacitor electrode 133' is made of the same material as the first semiconductor layer 13a and is electrically connected to each other. The design of the fourth capacitor electrode 133' is the same as that in embodiment 4 and fig. 6, and therefore, the description thereof is omitted. In addition, the display device of the embodiment further includes a first capacitor Cst1, the first capacitor Cst1 has a first capacitor electrode 172 'and a second capacitor electrode 202', the first capacitor electrode 172 'is electrically connected to the first semiconductor layer 13a, and the second capacitor electrode 202' is electrically connected to the second semiconductor layer 191 and the third semiconductor layer 192.
In the present invention, the display device manufactured in the foregoing embodiment can be used in combination with a touch panel as a touch display device. Next, embodiments 24 to 30 will provide possible implementations of the touch display device of the present invention.
Example 24
Fig. 26 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The equivalent circuit diagram of the circuit design of the tft unit in the first pixel of this embodiment is the same as that shown in fig. 2A, and therefore, the details thereof are not repeated herein.
As shown in fig. 2A and fig. 26, first, a first substrate 11 is provided, and a shielding layer 111 is formed on a region of the first substrate 11 where an active layer of a thin film transistor is to be formed. Next, a buffer layer 12 is formed on the first substrate 11 and the shielding layer 111. Then, a first semiconductor layer 13a, which is a low temperature polysilicon layer and includes a source region 131, a channel region 132 and a drain region 133, is disposed on the buffer layer 12. Next, a first gate insulating layer 14 is formed on the first semiconductor layer 13a, and a first gate 151 and a first touch signal line 155 are formed on the first gate insulating layer 14. Then, a bottom second insulating layer 16a is formed, and a third electrode 171, a first electrode 172, a first capacitor electrode 172' and a third gate 152 are formed on the bottom second insulating layer 16 a. Thus, the first thin film transistor of the present embodiment is completed.
Next, a top second insulating layer 16b is formed on the third electrode 171, the first electrode 172, the first capacitor electrode 172' and the third gate 152, and a second semiconductor layer 191 and a third semiconductor layer 192 are formed on the top second insulating layer 16b, wherein the materials may be zno-based metal oxides, for example: IGZO, ITZO, and the like. Then, a second conductive layer including a fourth electrode 201, a second electrode 202 and a second capacitor electrode 202' is formed on the second semiconductor layer 191 and the third semiconductor layer 192, and the second conductive layer further includes a second extension electrode 202 ″ and a fifth electrode 203. Then, a sixth insulating layer 221 and a planarization layer 21 are sequentially formed on the second conductive layer. Finally, the organic light emitting diode unit of this embodiment is formed in the same manner as in embodiment 1, thereby completing the fabrication of the display device of this embodiment.
As shown in fig. 2A and fig. 26, in the present embodiment, the third gate 152 is electrically connected to the first gate 151, so as to achieve the purpose of electrically connecting the first thin film transistor unit and the third thin film transistor unit. In addition, the second TFT2 and the third TFT3 can be electrically connected to each other through the second conductive layer. Further, the first and second capacitance electrodes 172 'and 202' are disposed to overlap to form a first capacitance Cst 1.
As shown in fig. 26, after the fabrication of the organic light emitting diode unit is completed, an encapsulation layer 27 is further formed on the organic light emitting diode unit, and a touch electrode 28 is further formed on the encapsulation layer 27, so that the fabrication of the touch display device of the embodiment is completed. The touch electrode 28 can be electrically connected to the first touch signal line 155 through the through holes 204, 231, 281. The through hole 281 can achieve the purpose of conducting the touch electrode 28 and the first touch signal line 155 by filling metal or conductive ink.
Therefore, compared to the previous embodiments, the display device of the present embodiment is a touch display device, and further includes a touch electrode 28 and a touch signal line (i.e., the first touch signal line 155), wherein the touch electrode 28 is disposed above the display medium (i.e., the oled unit), the touch signal line (i.e., the first touch signal line 155) is disposed between the display medium layer and the touch signal line (i.e., the first touch signal line 155), and the touch electrode 28 is electrically connected to the touch signal line (i.e., the first touch signal line 155) through the through holes 204, 231, 281.
Example 25
Fig. 27 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to that of embodiment 24, except that a second touch signal line 156 is formed on the third electrode 171, the first electrode 172, the first capacitor electrode 172', and the third gate 152, and is electrically connected to the first touch signal line 155 through a via hole. Therefore, the second touch signal line 156 is made of the same material as the first conductive layer including the third electrode 171, the first electrode 172, the first capacitor electrode 172', and the third gate 152.
Example 26
Fig. 28 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of the present embodiment is similar to embodiment 24, except that the first touch signal line 155 is formed simultaneously with the third electrode 171, the first electrode 172, the first capacitor electrode 172' and the third gate 152, and the touch display device of the present embodiment does not include the through hole 204 (as shown in fig. 26). Therefore, the first touch signal line 155 is made of the same material as the first conductive layer including the third electrode 171, the first electrode 172, the first capacitor electrode 172' and the third gate 152.
Example 27
Fig. 29 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 24 except for the following points. In the present embodiment, the first touch signal line 155 is formed simultaneously with the third electrode 171, the first electrode 172, the first capacitor electrode 172' and the third gate 152. Therefore, the first touch signal line 155 is made of the same material as the first conductive layer including the third electrode 171, the first electrode 172, the first capacitor electrode 172' and the third gate 152. In addition, in the present embodiment, the second semiconductor layer 191 and the third semiconductor layer 192 are connected to each other to form a same metal oxide layer.
Example 28
Fig. 30 is a schematic cross-sectional view of a first pixel and a second pixel of the display device of the present embodiment. The display device of the present embodiment is similar to embodiment 27 except for the following points.
In the present embodiment, the third capacitor electrode 154 is formed at the same time as the first gate 151 is formed, and the third capacitor electrode 154 and the first capacitor electrode 172' are overlapped to form a capacitor. In addition, in the embodiment, the shielding layer 111 is a metal layer, and the shielding layer 111 is electrically connected to the first touch signal line 155 through at least one via 1551.
Furthermore, the display device of the present embodiment further includes a second pixel Px2 in addition to the first pixel Px 1; the structure of the tft element in the second pixel Px2 is the same as that of the first pixel Px1, and therefore, the description thereof is omitted. In the embodiment, the second pixel Px2 is disposed adjacent to the first pixel Px1, and the shielding layer 111 of the first pixel Px1 is electrically connected to the shielding layer 111 of the second pixel Px 2. In more detail, the shielding layer 111 of the first pixel Px1 and the shielding layer 111 of the second pixel Px2 are electrically connected through the first touch signal line 155. In addition, the shielding layer 111 between the first semiconductor layer 13a and the first substrate 11 can also be used as a touch signal line.
Example 29
Fig. 31 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. The display device of this embodiment is similar to embodiment 24 except for the following points. In the present embodiment, the organic light emitting diode unit is a bottom emission organic light emitting diode unit; the organic light emitting layer 25 of the organic light emitting diode does not overlap the first, second and third thin film transistor units. Therefore, in the present embodiment, the touch electrodes (including the driving touch electrode 281 and the sensing touch electrode 282) are disposed on the first substrate 11; more specifically, the driving touch electrode 281 and the sensing touch electrode 282 are disposed on two sides of the first substrate 11. In addition, the first touch signal line 155 disposed between the organic light emitting diode unit and the first substrate 11 is electrically connected to the driving touch electrode 281 and the sensing touch electrode 282 through the through hole 1551.
Example 30
Fig. 32 is a schematic cross-sectional view of a first pixel of the display device of the present embodiment. Similar to embodiment 29, the shielding layer 111 is not directly disposed on the first substrate 11, but disposed on the driving touch electrode 281.
The display device or the touch display device manufactured in the foregoing embodiment of the invention can be applied to any electronic device that needs a display screen and is known in the art, such as a display, a mobile phone, a notebook computer, a video camera, a music player, a mobile navigation device, a television, and other electronic devices that need to display images.
The above-described embodiments are merely exemplary for convenience in explanation, and the scope of the claims of the present invention should be determined by the claims rather than by the limitations of the above-described embodiments.
Claims (9)
1. A display device, comprising:
a first substrate;
a first insulating layer disposed on the first substrate;
a first thin film transistor unit disposed on the first substrate, the first thin film transistor unit including:
a first semiconductor layer disposed between the first substrate and the first insulating layer;
a second thin film transistor unit disposed on the first substrate, the second thin film transistor unit including:
a second semiconductor layer disposed on the first insulating layer and the first semiconductor layer; and
a third thin film transistor unit disposed on the first substrate, the third thin film transistor unit including:
a third semiconductor layer disposed between the first substrate and the first insulating layer;
the second semiconductor layer is electrically connected with the third semiconductor layer through a metal layer.
2. The display device according to claim 1, further comprising a shielding layer disposed between the first semiconductor layer and the first substrate, wherein the shielding layer overlaps the second semiconductor layer.
3. The display device according to claim 1, wherein the first semiconductor layer and the third semiconductor layer are provided in the same layer.
4. The display device according to claim 1, wherein the first thin film transistor unit includes a first gate electrode; and the third thin film transistor unit comprises a third grid, and the first grid and the third grid are arranged on the first insulating layer.
5. The display device according to claim 4, further comprising a second insulating layer disposed on the first gate electrode and the third gate electrode.
6. The display device according to claim 1, wherein the third semiconductor layer comprises silicon and the second semiconductor layer comprises a metal oxide.
7. The display device of claim 6, wherein the first semiconductor layer comprises silicon.
8. The display device of claim 1, wherein the first semiconductor layer comprises silicon and the second semiconductor layer comprises a metal oxide.
9. The display device of claim 1, wherein the first semiconductor layer comprises silicon and the third semiconductor layer comprises silicon.
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| US62/358,177 | 2016-07-05 | ||
| CN201611089421.1A CN107403804B (en) | 2016-05-17 | 2016-12-01 | Display device |
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| CN108831892B (en) | 2018-06-14 | 2020-01-14 | 京东方科技集团股份有限公司 | Display back plate, manufacturing method thereof, display panel and display device |
| US10705636B2 (en) | 2018-06-21 | 2020-07-07 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display device |
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| CN109473461A (en) * | 2018-10-18 | 2019-03-15 | 深圳市华星光电半导体显示技术有限公司 | Oled panel and preparation method thereof |
| CN109148491B (en) * | 2018-11-01 | 2021-03-16 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
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| CN112750861A (en) * | 2019-10-29 | 2021-05-04 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
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