CN112035302B

CN112035302B - Real-time monitoring and analyzing method, device and system for bus data

Info

Publication number: CN112035302B
Application number: CN202010870798.0A
Authority: CN
Inventors: 陈才; 范里政; 刘付东
Original assignee: Tianjin Feiteng Information Technology Co ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2020-08-26
Filing date: 2020-08-26
Publication date: 2021-04-09
Anticipated expiration: 2040-08-26
Also published as: CN112035302A

Abstract

The invention discloses a real-time monitoring and analyzing method, a device and a system of bus data, wherein the method comprises the steps of collecting the bus data; decoding the acquired bus data; writing the data obtained by decoding into a cache; the cached data is taken out and sent to an upper computer, and when the bus data is collected, a clock used for sampling is a clock sent to the Slave device by the Master device on the bus or a clock used by both the Master device and the Slave device; the device comprises a logic device and a PC interface conversion circuit which is used for being connected with an upper computer, wherein the logic device comprises an acquisition input end which is used for being connected to a bus between Master equipment and Slave equipment so as to acquire bus data. The invention can realize long-time continuous monitoring of the bus, can automatically convert data transmitted in the bus, does not need to manually participate in analyzing waveform content, does not depend on the detector per se in monitoring time, and has stronger practicability and popularity.

Description

Real-time monitoring and analyzing method, device and system for bus data

Technical Field

The invention relates to a bus data monitoring technology of a computer interface bus communication part, in particular to a real-time monitoring and analyzing method, a device and a system of bus data.

Background

In the field of computers, Buses (BUS) are used to transfer information from one module to another. The lines connected from one point to another may be referred to collectively as a BUS (BUS). The buses of a computer are various and can be generally divided into a high-speed bus and a low-speed bus, for example, the high-speed bus includes: PCIe bus, DDR interface bus, gigabit network interface bus, and the like; the low speed bus includes SPI interface bus, IIC bus, JTAG bus, LPC bus, UART bus, etc. The buses can realize interconnection of two or more devices and realize data receiving and transmitting among the devices.

When data is transmitted on a line, once an accident occurs, the three parts on the whole transmission system are suspected, and the three parts are respectively: sender, transmission line, receiver. To clarify the root cause of the problem, we often use the following: the probe is connected to the bus by using an oscilloscope or a logic analyzer, and then the waveform on the line is captured on the screen of the oscilloscope or the logic analyzer to be analyzed. So as to determine whether the request sent by the sender has a problem, or the receiver has a problem in analyzing the data, or the instability of the transmission system causes the data to lose information in the transmission process. Such a method can clearly and truly reflect various phenomena on the transmission system, but has obvious disadvantages. Because the oscilloscope needs to truly restore the original appearance of the signal to be measured, a higher sampling frequency needs to be used for sampling the signal to be measured. The larger the number of sampling times per unit time, the larger the amount of data generated, the larger the required memory capacity, and the faster the memory interface speed is required. The cost of memory that typically meets the above requirements is extremely high, so the memory for oscilloscope data is typically not made very large, but rather is in the form of a FIFO, as shown in fig. 1, that continually replaces the original data with new data. Or a single trigger mode is used, data with a fixed time length is captured once and then processed, and the data is sent to be displayed after the processing is finished. The principle of the logic analyzer is almost the same as that of the oscilloscope, only the measured signals are distinguished by '0' and '1' in the data sampling process, and the data quantity is reduced to a certain extent. Such a reduction is not sufficient to continuously record the bus state. There is also a probability of missing erroneous data. The single trigger takes the form shown in fig. 2, where the circle positions simulate an anomaly signal. However, many times problems on the bus do not necessarily occur frequently, and most likely only once a day or two. When the problem is faced, the wrong field cannot be captured, and the problem cannot be eliminated at all. Therefore, it is important to record the bus status and data continuously for a long time. However, how to monitor the bus status and data is still a key technical problem to be solved.

Disclosure of Invention

The technical problems to be solved by the invention are as follows: the invention can realize long-time continuous monitoring of the bus, can automatically convert data transmitted in the bus, does not need to manually participate in analyzing waveform contents, does not depend on a detector per se in monitoring time, and has stronger practicability and popularity.

In order to solve the technical problems, the invention adopts the technical scheme that:

a real-time monitoring and analyzing method of bus data comprises the following steps:

1) collecting bus data;

2) decoding the acquired bus data;

3) writing the data obtained by decoding into a cache;

4) and taking out the cached data and sending the data to an upper computer.

Optionally, when the bus data is acquired in step 1), the clock used for sampling is a clock sent by the Master device on the bus to the Slave device, or a clock used by both the Master device and the Slave device.

Optionally, only edge sampling is performed when the bus data is acquired in step 1).

Optionally, when the bus data is collected in step 1), the collected bus is an LPC bus, and the signals connected to the LPC bus include a clock signal CLK, a data FRAME signal FRAME, and a composite command address data signal LAD [3:0], where the clock signal CLK is used as a sampling clock.

Optionally, only the read-write information, the address Addr, the synchronous beat Sync and the Data of the CT/DIR beat obtained by sampling are retained when the collected bus Data is decoded in step 2).

Optionally, when the collected bus data is decoded in step 2), the processing step for the read operation includes:

2.1) the state machine leaves idle state when data comes;

2.2) filtering out the START beat of the bus;

2.3) judging whether the access mode is I/O access according to the read-write information of the CT/DIR beat, if not, discarding the envelope data transmitted this time, ending and exiting; if the access is I/O access, the read-write information of the CT/DIR beat is well stored, and the next step is executed;

2.4) storing the information of the address Addr into a register;

2.5) filtering TAR beat information after the address Addr;

2.6) waiting for the synchronous beat Sync, if the synchronous beat Sync is received, saving the result of the synchronous beat Sync into a register, and if the synchronous beat Sync is a synchronous error, returning to the step 2.6) to wait for the synchronous beat Sync; if the synchronous beat Sync is successful in synchronization, executing the next step;

2.7) saving the Data into a register, and the state machine returns to idle state again to wait for the next Data.

Optionally, step 3) writes the decoded Data into a cache, specifically, the decoded Data is written into a large-bit-width register in a combinational logic manner, the bit width of the large-bit-width register is not less than the sum of the read-write information of the CT/DIR beat, the address Addr, the synchronization beat Sync and the bit width of the Data, and if the written next address is equal to the value of the read address, it is determined that the writing overflows, an error is reported, and the process exits.

Optionally, the detailed step of step 4) extracting the cached data and sending the data to the upper computer includes: reading the cache and taking out the cached data in a mode of taking bits with a specified size as a data packet, if the read cache address is equal to the written cache address, judging that the data in the cache is empty, waiting for specified time or directly jumping to execute reading the cache again; otherwise, marking a start bit and a stop bit at the head and tail of the data which is taken out of the cache, then converting the sorted data into a data sending device, sending the data into an external interface circuit by using a carrier wave through the data sending device, and then sending the data to an upper computer through the external interface circuit.

In addition, the invention also provides a real-time monitoring and analyzing device of bus data, which comprises a logic device and a PC interface conversion circuit connected with an upper computer, wherein the logic device comprises a collection input end connected to a bus between Master equipment and Slave equipment to collect bus data, and the logic device comprises:

the data analysis decoding module is used for decoding the acquired bus data;

the decoding data integration module is used for writing the data obtained by decoding into a cache;

the cache data management module is used for managing the access of cache data;

and the cache data reading module is used for taking out the cached data and sending the cached data to the PC interface conversion circuit.

In addition, the invention also provides a real-time monitoring and analyzing system of the bus data, which comprises an upper computer and the real-time monitoring and analyzing device of the bus data, wherein the real-time monitoring and analyzing device of the bus data and the upper computer are connected with each other.

Compared with the prior art, the method of the invention has the following advantages

1. Compared with the short-time accurate monitoring of the traditional oscilloscope, the invention can realize long-time continuous monitoring of the bus.

2. Compared with the traditional oscilloscope in which the waveform and the data directly need to be artificially converted, the method can automatically convert the data transmitted in the bus without manually participating in analyzing the waveform content.

3. Compared with the traditional oscilloscope logic analyzer, the invention can realize continuous sampling storage of the tested bus, and the monitoring time does not depend on the detector and is only related to the hard disk capacity of the connected upper computer.

4. Compared with the traditional logic analyzer, the data of the invention is compressed, the bandwidth of the notebook computer interface which needs to be occupied is smaller, and the practicability and the popularity are stronger.

The real-time monitoring and analyzing device and the system of the bus data are devices corresponding to the real-time monitoring and analyzing method of the bus data, so the real-time monitoring and analyzing device and the system of the bus data also have the advantages of the real-time monitoring and analyzing method of the bus data, and compared with the traditional oscilloscope which is huge and heavy in size, the real-time monitoring and analyzing device of the bus data is small in size, convenient to carry about by a user and convenient to debug equipment on site.

Drawings

Fig. 1 is a schematic diagram of a memory in the form of FIFO for storing data in a conventional oscilloscope.

Fig. 2 is a schematic diagram of a conventional single-trigger manner.

FIG. 3 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a sampling clock and a sampling principle in an embodiment of the present invention.

Fig. 5 is a waveform diagram of rising edge sampling according to an embodiment of the present invention.

Fig. 6 is a clock timing diagram of a read operation in the LPC bus according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of a basic structure of an apparatus according to an embodiment of the present invention.

Fig. 8 is a schematic view illustrating a decoding principle of the data parsing decoding module according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating data filtering of the data parsing and decoding module according to an embodiment of the present invention.

Fig. 10 is a schematic diagram illustrating an integration principle of the decoding data integration module according to an embodiment of the present invention.

Fig. 11 is a schematic diagram illustrating a principle of fetching data in a cache by a cache data management module according to an embodiment of the present invention.

Fig. 12 is a schematic diagram illustrating a data reading principle of the cache data reading module according to an embodiment of the present invention.

Fig. 13 is a demonstration result of data acquired by the upper computer in the embodiment of the present invention.

Fig. 14 is a schematic view of the overall working flow of the apparatus according to the embodiment of the present invention.

FIG. 15 is a schematic diagram illustrating the overall data flow of the apparatus according to the embodiment of the present invention.

Detailed Description

In order to make the using method, technical solution and advantages of this embodiment more clear, the following will fully describe the technical implementation of this embodiment by using the data snooped on the LPC bus as an example and by using a specific implementation method in conjunction with the drawings in this embodiment. Of course, the described embodiments are only a part of the embodiments, and it does not mean that the undescribed embodiments such as SPI, IIC, PCIe, are not within the scope of the embodiments. LPC (Low Pin count) is a computer bus protocol based on the Intel standard. The bus is used for replacing an ISA bus protocol of the old generation and is used for connecting a south bridge with Super I/O chips, FLASH BIOS, EC and other low-bandwidth devices. The expansion of the interface and the initialization of each functional part and peripheral of the CPU are realized. The major advantage of LPC is that it uses fewer pins to perform the ISA function.

As shown in fig. 3, the method for real-time monitoring and analyzing bus data of the present embodiment includes:

1) collecting bus data;

2) decoding the acquired bus data;

3) writing the data obtained by decoding into a cache;

4) and taking out the cached data and sending the data to an upper computer.

Conventional oscilloscopes typically use a higher sampling rate to sample the signal under test in order to more realistically recover the signal. In so doing, the amount of generated data is very large. In order to solve the above problem, in this embodiment, when the bus data is acquired in step 1), a clock used for sampling is a clock sent by a Master device (Master device) on the bus to a Slave device (Slave device), or a clock used by both the Master device and the Slave device. See fig. 4, where the sampling clock t_sRepresenting the clock sent by the Master device (Master device) on the bus to the Slave device (Slave device), or the clock used by the Master device and the Slave device together, by sampling the clock t_sThe sampling is carried out, so that the data volume generated by the sampling mode used by the method of the embodiment is greatly reduced compared with the high-speed sampling mode of the traditional oscilloscope on the premise of ensuring no data distortion, the data obtained by sampling of the Slave equipment can be reflected more truly, and the requirements of the system on the storage performance and the storage capacity are reduced.

In this embodiment, only edge sampling is performed when bus data is acquired in step 1). By means of edge sampling, shielding processing (such as ACK, SATR and STOP signal data of an IIC bus) is carried out on a non-sampling protocol overhead part in the FPGA when no data exists, so that the data needing to be processed and the stored data are fewer, and the FPGA-based data monitoring system is suitable for the purpose of long-time monitoring. As shown in fig. 5, the edge sampling in this embodiment is specifically rising edge sampling, and falling edge sampling may also be adopted. Compared with the traditional oscilloscope which uses a high-speed storage module inside a machine to store data, the data storage of the embodiment uses a hard disk on an upper computer (PC) as a storage medium of the data. The two storage media have great difference in unit capacity cost, so that the product is easier to popularize, and more expenses can be saved for users.

In this embodiment, when the bus data is collected in step 1), the collected bus is an LPC bus, and the signals connected to the LPC bus include a clock signal CLK, a data FRAME signal FRAME, and a composite command address data signal LAD [3:0], where the clock signal CLK is used as a sampling clock. The LPC bus has a total of 13 signal lines, of which there are 7 candidate signals and 6 candidate signals. The necessary signals are LCLK, LRESET #, LFRAME #, LAD [3:0], respectively. The selectable signal profiles are LDRQ #, SERIRQ, CLKRUN #, LPME #, LPCPD #, and LSMI #. Since the selectable signal does not affect the function of interface communication, the data amount is reduced by collecting the selectable signal when the bus data is collected in step 1) of this embodiment. In this embodiment, a programmable logic device such as an FPGA or a CPLD is connected between the master and the slave of the LPC bus. The signals of the bus needed to be accessed to the programmable logic device include CLK, FRAME, LAD [3:0 ]. Then, data acquisition, decoding, data caching, interface conversion and other parts are integrated in the programmable logic device, wherein the interface conversion part is used for converting the interface into a PC interface standard. And then, connecting the board card of the programmable logic device with a PC, performing corresponding integration processing on the data again by using software at the PC end, storing the data in a hard disk of the PC, and displaying the data.

There are also many access modes for LPC, such as Memory, DMA, I/O, etc. Although each access pattern is more or less different, it is still generally consistent structurally. Therefore, the present embodiment will take the extraction of the I/O access type as an example to describe a specific implementation process of the present embodiment. The block diagram of the I/O access mode read timing sequence of the LPC bus is shown in fig. 6. Referring to fig. 6, in this embodiment, when decoding the acquired bus Data in step 2), only the read-write information, the address Addr, the synchronization beat Sync, and the Data of the CT/DIR beat obtained by sampling are retained.

In this embodiment, when the collected bus data is decoded in step 2), the processing step for the read operation includes:

2.1) the state machine leaves idle state when data comes;

2.2) filtering out the START beat of the bus;

2.4) storing the information of the address Addr into a register;

2.5) filtering TAR beat information after the address Addr;

In this embodiment, the step 3) writes the decoded Data into the cache, specifically, the decoded Data is written into a register with a large bit width in a combinational logic manner, the bit width of the register with the large bit width is not less than the sum of the read-write information of the CT/DIR beat, the address Addr, the synchronization beat Sync, and the bit width of the Data, and if the written next address is equal to the value of the read address, it is determined that the writing overflows, an error is reported, and the process exits.

In this embodiment, the detailed step of taking out the cached data and sending the cached data to the upper computer in step 4) includes: reading the cache and taking out the cached data in a mode of taking bits with a specified size as a data packet, if the read cache address is equal to the written cache address, judging that the data in the cache is empty, waiting for specified time or directly jumping to execute reading the cache again; otherwise, marking a start bit and a stop bit at the head and tail of the data which is taken out of the cache, then converting the sorted data into a data sending device, sending the data into an external interface circuit by using a carrier wave through the data sending device, and then sending the data to an upper computer through the external interface circuit.

As shown in fig. 7, this embodiment further provides a real-time monitoring and analyzing apparatus for bus data, which includes a logic device 1 and a PC interface conversion circuit 2 connected to an upper computer, where the logic device 1 includes a collection input terminal connected to a bus between a Master device and a Slave device to collect bus data, and the logic device 1 includes:

the data analysis decoding module is used for decoding the acquired bus data;

the cache data management module is used for managing the access of cache data;

and the cache data reading module is used for taking out the cached data and sending the cached data to the PC interface conversion circuit 2.

In the embodiment, the logic device 1 is realized by adopting an FPGA chip, the data is collected, compressed and analyzed in the single FPGA chip, and an upper computer (PC) is adopted as a display processing part of the data. The oscilloscope adopted by the traditional method integrates the display part and the data acquisition part into a shell. This embodiment therefore has a significant advantage in terms of volume over conventional oscilloscopes.

Taking LPC as an example, the implementation method of the real-time monitoring and analyzing device for bus data in this embodiment is as follows:

the first step is as follows: the pins of the logic device 1 are connected to the LPC interface of the system under test, with CLK, FRAME, LAD signals respectively. And determines that the above-described pins have all been set to the input mode internally of the logic device 1.

The second step is that: an LPC data analysis decoding module is constructed in the logic device 1, and the module has the main function of decoding the data content when the data is transmitted in the bus. The read operation (read operation) of the I/O by the data parsing and decoding module will be described in detail below. Referring to fig. 8, the data parsing and decoding module firstly filters a Start beat of a bus, and then monitors whether an access mode is an I/O access, if not, the envelope data transmitted this time may be discarded, and if the access mode is the I/O access, the read-write information is stored, the address information is stored in a register by going downward, and after the TAR beat information is filtered, the result of the bus synchronization beat is stored in a register. If synchronization in the synchronization beat is wrong, the original waiting state is also returned. If the synchronization is successful. Then go further down to save the data information into a register and then the state machine goes back to Idle again, waiting for the next field of data to arrive. In fig. 8, the register reg1 has a bit width of 8 bits, and its bit7 is a read/write flag bit, and a "0" indicates a read operation and a "1" indicates a write operation. Its bit0 indicates the synchronous state, 0 indicates the synchronization between the master and slave is normal, and 1 is abnormal. Register reg2 is 16 bits wide and the address to be read and written by the IO. The bit width of the register reg3 is 8 bits, and the data read and written by the IO.

Referring to fig. 9, the Data acquired by the Data parsing and decoding module is a black filled portion (CT/DIR beat, address Addr, synchronization beat Sync, Data), and the discarded Data is a white filled portion (Start beat, TAR beat).

And thirdly, after the data analysis and decoding module finishes data collection, integrating the data by a decoding data integration module and then writing the data into a cache of the logic device. The specific implementation method is that the data with different bit widths are written into a register with a large bit width by adopting a combinational logic mode. In a specific implementation process, as shown in fig. 10, in this embodiment, the read-write information generated in the CT/DIR beat is stored in the 7 th bit of a register with a 32-bit width. And the Sync result information generated by the Sync is written to the 0 th bit. Address information generated by the Addr beat is stored in the 31 st bit to the 16 th bit. Data-generated information is stored in the 15 th to 8 th bits. And then written into the cache using sequential logic.

And fourthly, realizing the writing and reading control of the cache data through a cache data management module. Since the bit width of the decoded data is 32 bits, the clock for generating the data is 33MHz of the clock of the LPC, but the clock for reading the data is not 33MHz nor 32 bits wide, a buffer is added here to prevent the loss of the data. The size of the cache is 32 x 8 bits, and the size can be reasonably adjusted according to the design of the cache. In the write position of the buffer, a design for preventing overflow is added, and the same read port also adds a design for marking that the buffer is empty. The design of anti-overflow is simple, when the next address written is equal to the value of the address read, it is overflow. And the reading null operation is that the data in the cache is null if the read address is equal to the written address, and the operation guides whether the next cache fetching operation is performed or not.

Fifthly, the data in the buffer is taken out through the buffer data reading module, as shown in fig. 11, in this embodiment, 8 bits are transmitted to the data sending module as one data packet, for example, 0 th to 7 th bits (bits 0 to 7) are transmitted to the data sending module as one data packet. And the data is taken out according to whether the buffer memory fed back in the fourth step is empty or not, and the data is read. The inputs to the module are set to 32 bits wide for consistency with the cached memory structure. A single operation reads 32-bit data, and splits the data into 4 8-bit data inside the module, which are sequentially transmitted to the subsequent transmitting module.

And sixthly, the data sending module sends the 8-bit data to the PC through the PC interface conversion circuit 2. There are many schemes for implementing this function, such as directly implementing CYUSB2014 (USB 2.0 to GPIF), CYUSB3014 (USB 3.1 to GPIF) by laplace, or using serdes (serial/parallel converters) in FPGA. However, the above-mentioned several ways are not only too complicated, but also have no condition in the current design case, so that the connection relationship between the FPGA and the PC is described only by using a simple and common interface, such as UART, for simply showing the whole structure of the present embodiment. As shown in fig. 12, when the data sending module receives the 8-bit data taken out from the buffer, the transmitting device is started, and the Start bit Start and the Stop bit Stop are first included at the head and the tail of the data. And then, converting the sorted data into a data interface, and sending the data to an interface circuit outside the FPGA by using a carrier wave. The carrier signal here will depend on the amount of data of the front-end acquisition signal.

Seventhly, since the PC interface conversion circuit 2 uses the CYUSB3014 of laplace, the PC interface conversion circuit 2 directly transmits the parallel signal to the PC through the USB3.0 interface. If the FPGA with serdes inside is used, the FPGA can be directly connected with a PC through a cable. If UART is used, a USB-to-UART chip such as PL2303, CP2102 or CH340 is used to realize the connection between PC and circuit board.

And eighthly, calling a serial port driver in the PC, displaying the data transmitted from the UART, performing processing such as line splitting, interval adding, sequence arranging and the like, and storing the data in a disk. In the following figures, the first 00 and the last 00 represent the beginning and end of a single transmission, which are PC identifiers and may not be used, and "0F 00" represents Reg3 depicted in the graph in the third step, and "4E" represents Reg2, and "00" carried after 4E "represents Reg 1. The demonstration results are shown in fig. 13. The overall process of the method for implementing the real-time monitoring and analyzing device for bus data in this embodiment has been basically described. The implementation method of the real-time monitoring and analyzing device for bus data in this embodiment is summarized as fig. 14. Fig. 15 is a schematic view of the overall data transmission flow direction when the device of this embodiment is applied to an LPC interface communication system, and it can be known from fig. 14 and fig. 15 that, on the premise of not affecting the normal data transmission between the interface host and the interface slave, the device of this embodiment implements acquisition, screening, storage and output of normal data through an FPGA chip, and transmits the normal data to a PC software module that has not been hit through the PC interface conversion circuit 2, implements data display through the PC software module, and stores the normal data by using a hard disk or other external memory.

The LPC interface communication system comprises a host, a slave and a communication bus. The device comprises a logic device 1 and a PC interface conversion circuit 2 connected with an upper computer, wherein the logic device 1 is connected with a communication bus, and the PC interface conversion circuit 2 is connected with a PC (upper computer) and keeps communication with software running on the upper computer. The logic device 1 further includes an LPC decoder, a data integration module, a buffer and buffer management module, a buffer data reading module, and a data transmission module. The PC interface circuit is a USB to serial circuit, but the aforementioned CYUSB3014 USB to parallel circuit may also be used. The FPGA chip corresponding to the logic device 1 and the PC interface conversion circuit 2 are in the same circuit board and are collectively called as a bus monitoring device.

In the logic device 1: the data analysis decoding module is responsible for monitoring the state of the LPC bus, intercepting data when the bus has data, and abandoning protocol overhead data which is irrelevant to a user. The decoding data integration module is responsible for reintegrating the decoded data so as to make the data conform to the storage interface of the subsequent cache module. The buffer data management module is also called as an elastic buffer, and the effect of the buffer data management module is that the clock input by the LPC interface and the interface rate of the LPC interface are not matched with the working clock of the subsequent PC interface circuit. And avoiding the packet loss caused by burst data on LPC and opening up a buffer module. The buffer data reading module is manufactured for matching the data input interface of the subsequent UART module and the working frequency of the buffer data reading module. In addition, the logic device 1 further includes a data transmission module, which is used to convert data into a protocol conforming to the PC interface circuit, and implement communication between the PFGA and the PC interface circuit. The PC interface conversion circuit 2 is for realizing direct communication between the FPGA and the PC, and naturally, if the FPGA carries serdes and can realize the USB interface protocol, the FPGA can be integrated into the FPGA. The PC software in the upper computer mainly integrates and processes data from the FPGA correspondingly, displays the data and stores the data in a disk of the upper computer so as to realize a long-time bus monitoring function. The device of the embodiment adopts the slave clock as the sampling clock, so that the data acquisition amount can be reduced on the premise of ensuring no data distortion, and the bus data analysis part directly invalidates the data of the protocol overhead part, so that the data amount can be further reduced. Moreover, the analysis of the bus protocol is performed in the FPGA, so that the resource overhead of the PC and the communication bandwidth requirement between the PC and the monitoring device are reduced. The device of the embodiment adopts a hard disk of a PC as a storage medium for analyzing data, and realizes long-term real-time monitoring of the interface bus.

In addition, this embodiment also provides a real-time monitoring and analyzing system of bus data, including host computer and the real-time monitoring and analyzing device of aforementioned bus data, the real-time monitoring and analyzing device of bus data, host computer interconnect.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.

Claims

1. A real-time monitoring and analyzing method for bus data is characterized by comprising the following steps:

1) collecting bus data;

2) decoding the acquired bus data;

3) writing the data obtained by decoding into a cache;

4) taking out the cached data and sending the data to an upper computer;

when the collected bus data is decoded in the step 2), the processing step aiming at the read operation comprises the following steps:

2.1) the state machine leaves idle state when data comes;

2.2) filtering out the START beat of the bus;

2.4) storing the information of the address Addr into a register;

2.5) filtering TAR beat information after the address Addr;

2. The method for real-time monitoring and analyzing of bus data according to claim 1, wherein when the bus data is collected in step 1), a clock used for sampling is a clock sent to the Slave device by a Master device on the bus, or a clock used by both the Master device and the Slave device.

3. The method for real-time monitoring and analyzing of bus data according to claim 2, wherein only edge sampling is performed when the bus data is collected in step 1).

4. The method for real-time monitoring and analyzing of bus data according to claim 1, wherein when the bus data is collected in step 1), the collected bus is an LPC bus, and the signals connected to the LPC bus include a clock signal CLK, a data FRAME signal FRAME, and a complex command address data signal LAD [3:0], wherein the clock signal CLK is used as a sampling clock.

5. The method for real-time monitoring and analyzing of bus Data according to claim 4, wherein the bus Data obtained by the step 2) is decoded while only the read-write information, the address Addr, the synchronous beat Sync and the Data of the CT/DIR beat obtained by sampling are retained.

6. The real-time monitoring and analyzing method for bus Data according to claim 5, wherein the step 3) writes the decoded Data into a cache, specifically, the decoded Data is written into a register with a large bit width in a combinational logic manner, the bit width of the register with the large bit width is not less than the sum of the bit width of the read-write information of the CT/DIR beat, the address Addr, the synchronization beat Sync and the Data, and if the written next address is equal to the value of the read address, it is determined that the write overflows, an error is reported and the process exits.

7. The real-time monitoring and analyzing method for the bus data according to claim 1, wherein the detailed step of taking out the cached data and sending the data to the upper computer in the step 4) comprises the following steps: reading the cache and taking out the cached data in a mode of taking bits with a specified size as a data packet, if the read cache address is equal to the written cache address, judging that the data in the cache is empty, waiting for specified time or directly jumping to execute reading the cache again; otherwise, marking a start bit and a stop bit at the head and tail of the data which is taken out of the cache, then converting the sorted data into a data sending device, sending the data into an external interface circuit by using a carrier wave through the data sending device, and then sending the data to an upper computer through the external interface circuit.

8. The utility model provides a real-time supervision analytical equipment of bus data, characterized by, includes logic device (1) and is used for the PC interface converting circuit (2) that links to each other with the host computer, logic device (1) is including being used for being connected to the collection input on the bus between Master equipment, Slave equipment in order to gather bus data, logic device (1) includes:

the data analysis decoding module is used for decoding the acquired bus data;

the cache data management module is used for managing the access of cache data;

the cache data reading module is used for taking out the cached data and sending the cached data to the PC interface conversion circuit (2);

when the data analysis decoding module decodes the acquired bus data, the processing steps aiming at the read operation comprise:

2.1) the state machine leaves idle state when data comes;

2.2) filtering out the START beat of the bus;

2.4) storing the information of the address Addr into a register;

2.5) filtering TAR beat information after the address Addr;

9. A real-time monitoring and analyzing system for bus data, comprising an upper computer and the real-time monitoring and analyzing device for bus data according to claim 8, wherein the real-time monitoring and analyzing device for bus data and the upper computer are connected with each other.