CN112034767B

CN112034767B - Antenna distributed intelligent experimental island electrical topology identification system and antenna parameter measurement and control method thereof

Info

Publication number: CN112034767B
Application number: CN202010975661.1A
Authority: CN
Inventors: 杨倩; 钱微; 兰翰扬
Original assignee: Chongqing University of Technology
Current assignee: Chongqing University of Technology
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2024-06-11
Anticipated expiration: 2040-09-16
Also published as: CN112034767A

Abstract

The invention discloses an antenna distributed intelligent experimental island electrical topology identification system and an antenna parameter measurement and control method thereof. The antenna parameter measurement and control method is based on the intelligent measurement and control topology of the antenna, takes the received power, the bit error rate and the recognition rate as the basis, optimizes and adjusts the Q value, the transmitting power, the center frequency and the harmonic suppression of the antenna in a three-closed loop and cyclic iteration mode by screening and adjusting parameters, and improves the receiving quality of signals and the response speed of a system.

Description

Antenna distributed intelligent experimental island electrical topology identification system and antenna parameter measurement and control method thereof

Technical Field

The invention relates to the technical field of electrical topology identification systems, in particular to an intelligent experimental island electrical topology identification system and an antenna parameter measurement and control method thereof.

Background

At present, an electrical experiment cannot remotely monitor and record the operation process of electrical topological connection and related data; the correctness of the connection topology cannot be automatically calculated and checked according to the electrical schematic diagram; digital twins of an experiment cannot be constructed and run.

Disclosure of Invention

In view of the above, the invention aims to provide an antenna distributed intelligent experimental island electric topology identification system so as to solve the problem that the existing electric experiments cannot remotely monitor and record the operation process and related data of electric topology connection; the correctness of the connection topology cannot be automatically calculated and checked according to the electrical schematic diagram; technical problems such as inability to construct and run digital twins of an experiment; meanwhile, the problems of distributed and flexible deployment of intelligent tag impedance sampling sockets, automatic switching of multiple antennas, intelligent impedance matching and multipoint time-sharing sampling of RFID tags are solved.

The invention relates to an antenna distributed intelligent experimental island electrical topology identification system, which comprises an Ethernet switch, a host, a signal intelligent processing terminal, an antenna intelligent measurement and control topology, an overlapped plug and an intelligent tag impedance sampling socket, wherein the antenna intelligent measurement and control topology is arranged on the signal intelligent processing terminal;

the stacked plug comprises a plug front part, a plug conductor core, a plug rear part and a plug shell;

The front part of the plug comprises a tubular front insulating sheath, a straight groove body arranged on the outer side surface of the front insulating sheath and an impedance connecting sheet A arranged in the straight groove body, wherein the impedance connecting sheet A is provided with an elastic bulge part protruding out of the straight groove body and a plugging end part protruding out of the rear end of the insulating sheath;

the plug conductor core comprises an experimental signal conductor, a conductive spring sleeve, an assembly fixing ring and a connecting wire; the experimental signal conductor is of a tubular structure with a closed front end, the assembly fixing ring is arranged in the middle of the experimental signal conductor, the conductive spring sleeve is fixed on the outer surface of the front half section of the experimental signal conductor, and one end of the connecting wire is welded on the outer surface of the rear half section of the experimental signal conductor;

The rear part of the plug comprises a rear insulating sheath, an intelligent tag antenna coil, an impedance connecting sheet B, a circuit board, an impedance connecting wire and a connecting lug, wherein the circuit board is provided with an intelligent tag and impedance, the intelligent tag antenna coil is arranged on the outer surface of the rear insulating sheath, a straight groove which is in plug-in fit with a straight groove body on the outer side surface of the front insulating sheath is formed in the inner hole surface of the rear half section of the rear insulating sheath, the rear half section of the impedance connecting sheet B is arranged in the straight groove, and a jack for installing the front half section of the impedance connecting sheet B is formed in the front half section of the rear insulating sheath; the outer side surface of the insulating sheath is provided with a connecting plate for fixing the circuit board, the outer side surface of the insulating sheath is also provided with a mounting hole for fixing a connecting lug, the connecting lug is connected with the impedance connecting sheet B, one end of the impedance connecting wire is connected with the impedance connecting sheet B through the mounting hole, and the other end of the impedance connecting wire is connected with the impedance deployed on the circuit board; the intelligent tag antenna coil is connected with an intelligent tag arranged on the circuit board, and intelligent tag information is read when the tag is close to the signal intelligent processing terminal; the intelligent tag is used for calibrating the electrical connection topology and recording the electrical connection event, and information in the intelligent tag is modified by the host;

The front part of the plug is inserted into the plug shell, the front half part of the front insulating sheath extends out of the plug shell, and the elastic bulge part on the impedance connecting sheet A on the front insulating sheath is positioned outside the plug shell; the front half section of the plug conductor core is inserted into the inner hole of the front insulating sheath, and the plug conductor core is fixed in the front insulating sheath through the assembly fixing ring; the rear part of the plug is inserted into the plug shell, and the insertion end part of the impedance connection sheet A is inserted into the insertion hole on the rear insulating sheath and is pressed on the impedance connection sheet B; the second half section of the plug conductor core is inserted into the inner hole of the rear insulating sheath;

When the back plug-in plug is inserted on the front plug-in plug, the straight groove body on the front insulation sheath of the back plug-in plug is inserted in the straight groove on the back insulation sheath of the front plug-in plug, and the elastic bulge part on the impedance connection sheet A of the back plug-in plug is pressed on the impedance connection sheet B of the front plug-in plug, so that the impedance deployed on the circuit board of the front plug-in plug and the impedance deployed on the circuit board of the back plug-in plug form a parallel connection relation; the front half section of the experimental signal conductor of the last stacked plug is inserted into the rear half section of the experimental signal conductor of the previous stacked plug;

The intelligent tag impedance sampling socket comprises a socket body, wherein a trigger signal button, an experimental signal socket hole, a ring groove-shaped impedance sampling profile and an antenna for reading an intelligent tag are arranged at the upper end of the socket body, the experimental signal socket hole and the impedance sampling profile are coaxially arranged, an experimental signal plug sleeve is formed between the experimental signal socket hole and the impedance sampling profile, and an impedance sampling sheet is arranged in the impedance sampling profile; the lower end of the socket body is provided with an experimental signal connection terminal, an impedance sampling terminal connected with an impedance sampling sheet, a trigger button signal terminal connected with a trigger signal button and an antenna terminal connected with an antenna;

when the plug-in type plug is inserted into the intelligent tag impedance sampling socket, a front insulating sheath of the plug-in type plug is inserted into the impedance sampling profile, an elastic bulge on an impedance connection sheet A is pressed on the impedance sampling sheet, the front half section of a plug conductor core is inserted into an experimental signal socket hole, the front end of the plug conductor core is connected with the rear end of an experimental signal connection terminal, and the experimental signal connection terminal, the impedance sampling terminal and a trigger button signal terminal are respectively connected with a signal intelligent processing terminal through wires;

The antenna intelligent measurement and control topology comprises an antenna access control topology, an impedance matching array topology, a transmitting frequency adjustment topology and a harmonic suppression topology, wherein the antenna access control topology is used for enabling an antenna on an intelligent tag impedance sampling socket to be accessed into a signal intelligent processing terminal in a time-sharing mode, the impedance matching array topology is used for optimizing antenna resonant frequency, reducing noise and adjusting Q value, and the transmitting frequency adjustment topology is used for changing the central frequency of antenna transmitting; the harmonic suppression topology is used for suppressing harmonic components of the antenna;

the intelligent signal processing terminals are at least one, and each intelligent signal processing terminal is connected with a plurality of intelligent tag impedance sampling sockets; the signal intelligent processing terminal is connected with the Ethernet switch, or the signal intelligent processing terminal is connected with the host; the signal intelligent processing terminal is used for collecting impedance data, collecting and processing button trigger signals, collecting intelligent label information, storing corresponding data and receiving and transmitting network communication data;

The host is connected with the Ethernet switch and is used for receiving and transmitting information of the signal intelligent processing terminal, calculating experimental electrical topology after connection, comparing principle topology, writing intelligent label information, displaying information and serving network communication.

Further, the host comprises a first data address control bus, a first SPI bus, a first power module, a tag read-write module, a first data and program storage module, a first Ethernet bus interface module, a first USB interface conversion module, a display module, a keyboard module and a first singlechip minimum system, wherein the first data address control bus consists of a data bus, an address bus and a control bus;

The first power supply module is connected with the power bus;

the label read-write module, the first data and program storage module, the first Ethernet bus interface module, the first USB interface conversion module, the display module, the keyboard module and the first singlechip minimum system are respectively connected with the first data address control bus, the first SPI bus and the first power bus.

Further, the minimum system of the first singlechip is an MSP430 minimum system adopting an MSP430F5529 singlechip, and the tag read-write module is a 7960RFID tag read-write module adopting a TRF7960 chip; the first data and program storage module comprises an MX25L6436 data and program storage module adopting an MX25L6436 chip and an MX35LFGE data and program storage module adopting an MX35LFGE chip; the first Ethernet bus interface module is a CH395 Ethernet bus interface module adopting a CH395 chip; the display module is a display module adopting an RA8876 chip; the keyboard module adopts a keyboard module of a CH451 chip.

Further, the signal intelligent processing terminal comprises a second data address control bus, a second SPI bus, a second power module, an antenna matching and tag identification topology, a second data and program storage module, a second Ethernet bus interface module, a second USB interface conversion module, a JATG monitoring interface module, a button trigger signal interface, an encoding signal interface circuit, a button address calculation module, a plug impedance interface, a plug impedance sampling calculation topology and a second singlechip minimum system, wherein the second data address control bus is composed of a data bus, an address bus and a control bus;

The second power module is connected with the second power bus;

the second singlechip minimum system is connected with the second data address control bus and the second SPI bus;

the antenna matching and tag identification topology, the second data and program storage module, the second Ethernet bus interface module, the second USB interface conversion module and the JATG monitoring interface module are respectively connected with the second SPI bus and the second power bus;

The plug impedance interface is connected with the plug impedance sampling calculation topology, and the plug impedance sampling calculation topology is connected with the second data address control bus, so that a plug impedance sampling interface circuit is formed;

The button trigger signal interface is connected with the coding signal interface circuit, the coding signal interface circuit is connected with the button address calculation module, and the button address calculation module is connected with the second data address control bus, so that a button trigger sampling interface circuit is formed;

The antenna access control topology, the impedance matching array topology, the emission frequency adjustment topology and the harmonic suppression topology of the antenna intelligent measurement and control topology are measured and controlled by a second single chip microcomputer minimum system.

Further, the antenna access control topology is composed of a multipath analog switch or a multipath analog multiplexer and part of I/O of the minimum system of the second singlechip, and is used for time-sharing accessing the antennas on different intelligent tag impedance sampling sockets to the antenna matching and tag identification topology, and only accessing the antenna inductance coil of one socket at a time;

The impedance matching array topology is formed by connecting a digital variable capacitor and a digital variable resistor in series and parallel, and is respectively connected into an antenna matching and tag identification topology by an antenna intelligent measurement and control topology under the measurement and control of a second singlechip minimum system.

The transmitting frequency adjustment topology is formed by forming an array by digital variable capacitors in series-parallel connection, and the antenna intelligent measurement and control topology is connected into the antenna matching and tag identification topology under the measurement and control of the second singlechip minimum system.

The harmonic suppression topology is formed by forming an array by digital variable capacitors in series-parallel connection, and the antenna intelligent measurement and control topology is connected into the antenna matching and tag identification topology under the measurement and control of a second singlechip minimum system.

Further, the minimum system of the second singlechip is an MSP430 minimum system adopting an MSP430F5529 singlechip, and the antenna matching and tag identification topology is a TRF7960 antenna matching and tag identification topology adopting a TRF7960 chip; the second data and program storage module comprises an MX25L6436 data and program storage module adopting an MX25L6436 chip and an MX35LFGE data and program storage module adopting an MX35LFGE chip; the second Ethernet bus interface module is a CH395 Ethernet bus interface module adopting a CH395 chip; the coded signal interface circuit is a coded signal interface circuit adopting an LS148D priority encoder; the button address calculation module is a 74AC11008 button address calculation module adopting a 74AC11008 chip.

The invention discloses an antenna parameter measurement and control method of an antenna distributed intelligent experimental island electrical topology identification system, which comprises the following steps:

(1) The minimum system of the second singlechip polls and detects the impedance value of the plug connected to the socket, calculates the total impedance of the plug connected to the corresponding socket, and determines the number of overlapped plugs and whether a new plug is connected;

(2) When a new plug is connected, an antenna corresponding to the socket is connected to the antenna intelligent measurement and control topology under the control of the minimum system of the second singlechip, otherwise, the total impedance value of the plug connected to the socket is continuously polled;

(3) The second single-chip microcomputer minimum system inquires whether a history record exists in a plug of a corresponding socket, and if so, the second single-chip microcomputer minimum system directly adjusts the intelligent measurement and control topological parameters of the antenna according to the history record and updates the corresponding record; if no history record exists, initializing intelligent measurement and control topological parameters of the antenna according to theoretical calculation and debugging records, determining the transmitting power of the antenna according to the new plug number, and controlling a tag read-write module to read intelligent tags;

(4) The second singlechip minimum system reads the receiving power value of the antenna from the RSSI in the tag reading and writing module, calculates the ratio of the transmitting power to the receiving power, and compares the set value with the history record;

(5) The second single chip microcomputer minimum system judges whether the receiving and transmitting power ratio is optimal according to the comparison result, if not, the transmitting frequency is determined according to the comparison result, the step length and the direction are changed to adjust the transmitting frequency, and the step (4) is returned; if the receiving-transmitting power ratio is optimal, performing the next step;

(6) Further adjusting and optimizing a resistance parameter R and a capacitance parameter C of the antenna, reading a receiving power value of the antenna from the RSSI in the tag reading and writing module, calculating a ratio of transmitting power to receiving power, and comparing a set value with a history record;

(7) Judging whether the transceiving power ratio is optimal or not by the second singlechip minimum system according to the comparison result, returning to the step (6) if the transceiving power ratio is not optimal, and carrying out the next step if the transceiving power ratio is optimal;

(8) The second singlechip minimum system reads standard codes, plug label information, CRC (cyclic redundancy check) information, a start frame and an end frame from a register of a label read-write module, and calculates an error rate;

(9) Judging whether the error rate is lower than a set value, if the error rate is higher than the set value, adjusting harmonic suppression parameters to return to the step (8), and if the error rate is lower than the set value, performing the next step;

(10) And the second singlechip minimum system updates the related record through reading and calculating.

The invention has the beneficial effects that:

1. According to the antenna distributed intelligent experimental island electrical topology identification system, the antenna is positioned on the intelligent tag impedance sampling socket, and the socket can be distributed and flexibly deployed according to the system requirements of the experimental island; the antenna intelligent measurement and control topology is integrally arranged on the signal intelligent processing terminal, and is the basis of multi-antenna automatic switching, impedance intelligent matching and multi-point time-sharing sampling RFID labels. The signal intelligent processing terminal intelligently measures and controls different antennas to obtain information of different labels rapidly and accurately; the plug stacking quantity is obtained by processing the parallel impedance of the stacked plug, and the electrical connection topology can be calibrated and the electrical connection event can be recorded through the intelligent tag; the intelligent label impedance sampling socket can utilize a button trigger signal on the intelligent label impedance sampling socket to calibrate experimental electrical topology and determine connection relation. The antenna distributed intelligent experimental island electric topology identification system can solve the technical problems that the current electric experiment cannot remotely monitor and record the operation process and related data of electric topology connection, cannot automatically calculate and check the correctness of the connection topology according to an electric schematic diagram, cannot construct and run digital twins of the experiment, and the like.

2. In order to adapt to the uncertainty of access antenna parameters and the change of antenna coupling effects caused by the change of plug access quantity, which are caused by the scattered deployment of sockets in the antenna distributed intelligent experimental island electrical topology identification system, the invention increases the intelligent measurement and control topology of the antenna so as to improve the antenna coupling effects. The antenna parameter measurement and control method is based on the intelligent measurement and control topology of the antenna, takes the received power, the bit error rate and the recognition rate as the basis, optimizes and adjusts the Q value, the transmitting power, the center frequency and the harmonic suppression of the antenna in a three-closed loop and cyclic iteration mode by screening and adjusting parameters, and improves the receiving quality of signals and the response speed of a system.

Drawings

FIG. 1 is a schematic diagram of an antenna distributed intelligent experimental island electrical topology identification system;

FIG. 2 is a schematic diagram of a host;

FIG. 3 is a schematic diagram of an interface circuit of a host MSP430F5529 single-chip microcomputer;

FIG. 4 is a schematic diagram of an interface of a host 7960RFID tag read-write module;

FIG. 5 is a schematic circuit diagram of the Ethernet interface of the host CH 395;

FIG. 6 is a schematic diagram of an interface circuit of the host PL2303 GLUSB;

FIG. 7 is an interface diagram of the RA8876 display module of the host;

FIG. 8 is an interface diagram of a keyboard module CH451 chip of the host;

FIG. 9 is an interface diagram of a data and program storage module of a host;

FIG. 10 is a schematic diagram of the SPI bus of the host;

FIG. 11 is a schematic diagram of a signal intelligent processing terminal;

FIG. 12 is a TRF7960 antenna matching and tag identification topology;

FIG. 13 is an antenna smart access topology;

FIG. 14 is a schematic diagram of the signal intelligent processing terminal NE555 multivibrator inverter interface circuit;

FIG. 15 is a schematic diagram of a signal intelligent processing terminal ADG408 multiplexing interface circuit;

FIG. 16 is a schematic diagram of a signal interface circuit of a signal intelligent processing terminal trigger button;

FIG. 17 is a schematic diagram of an Ethernet bus interface module CH395 chip interface circuit of a signal intelligent processing terminal;

FIG. 18 is a schematic diagram of the PL2303GL chip interface circuit of the signal intelligent processing terminal;

fig. 19 is a schematic diagram of an interface circuit of the signal intelligent processing terminal MSP430F 5529.

FIG. 20 is a schematic diagram of an SPI bus of a signal intelligent processing terminal;

FIG. 21 is an interface diagram of a data and program storage module of the main signal intelligent processing terminal;

FIG. 22 is a schematic diagram of a smart tag impedance sampling receptacle;

FIG. 23 is another schematic view of a smart tag impedance sampling receptacle;

Fig. 24 is a schematic diagram of an assembled structure of the stacked plug;

FIG. 25 is a schematic view of the front of a plug;

FIG. 26 is a schematic view of a plug electrical conductor core;

FIG. 27 is a schematic view of the rear of the plug;

FIG. 28 is another view of a rear portion of the plug;

fig. 29 is a flowchart of an antenna parameter measurement and control method.

Detailed Description

The invention is further described below with reference to the drawings and examples.

The antenna distributed intelligent experimental island electrical topology identification system in the embodiment comprises an Ethernet switch 1, a host computer 2, a signal intelligent processing terminal 3, an intelligent tag impedance sampling socket 4 and an overlap plug 5, and also comprises an antenna intelligent measurement and control topology 6, wherein the antenna intelligent measurement and control topology is arranged on the signal intelligent processing terminal.

The stacked plug includes a plug front 51, a plug conductor core 52, a plug rear 53, and a plug housing 54.

The plug front 51 comprises a tubular front insulating sheath 511, a straight groove 512 arranged on the outer side surface of the front insulating sheath, and an impedance connection sheet A513 arranged in the straight groove, wherein the impedance connection sheet A is provided with an elastic bulge 5131 protruding out of the straight groove and a plugging end 5132 extending out of the rear end of the insulating sheath.

The plug conductor core 52 comprises an experimental signal conductor 521, a conductive spring sleeve 522, an assembly fixing ring 523 and a connecting wire 524; the experimental signal conductor is of a tubular structure with a closed front end, the assembly fixing ring is arranged in the middle of the experimental signal conductor, the conductive spring sleeve is fixed on the outer surface of the front half section of the experimental signal conductor, and one end of the connecting wire is welded on the outer surface of the rear half section of the experimental signal conductor. The plug conductor cores of the different stacked plugs can be connected by connecting wires 524.

The plug rear part 53 comprises a rear insulating sheath 531, an intelligent tag antenna coil 532, an impedance connecting sheet B533, a circuit board 534 provided with an intelligent tag and impedance, an impedance connecting lead 535 and a connecting lug 536, wherein the intelligent tag antenna coil is arranged on the outer surface of the rear insulating sheath, a straight groove which is in plug-in fit with a straight groove body on the outer side surface of the front insulating sheath is formed in the inner hole surface of the rear half section of the rear insulating sheath, the rear half section of the impedance connecting sheet B is arranged in the straight groove, and a jack 537 for installing the front half section of the impedance connecting sheet B is formed in the front half section of the rear insulating sheath; the intelligent tag antenna comprises an insulating sheath, wherein a connecting plate for fixing a circuit board is arranged on the outer side face of the insulating sheath, a mounting hole for fixing a connecting lug is further arranged on the outer side face of the insulating sheath, the connecting lug is connected with an impedance connecting piece B, one end of an impedance connecting wire is connected with the impedance connecting piece B through the mounting hole, the other end of the impedance connecting wire is connected with impedance deployed on the circuit board, an intelligent tag antenna coil is connected with an intelligent tag deployed on the circuit board, the intelligent tag in the embodiment is an RFID tag, and intelligent tag information is read when the tag is close to a signal intelligent processing terminal; the intelligent label is used for calibrating the electric connection topology and recording electric connection events, and information in the intelligent label is modified through the host.

The front part of the plug is inserted into the plug shell, the front half part of the front insulating sheath extends out of the plug shell, and the elastic bulge part on the impedance connecting sheet A on the front insulating sheath is positioned outside the plug shell; the front half section of the plug conductor core is inserted into the inner hole of the front insulating sheath, and the plug conductor core is fixed in the front insulating sheath through the assembly fixing ring; the rear part of the plug is inserted into the plug shell, and the insertion end part of the impedance connection sheet A is inserted into the insertion hole on the rear insulating sheath and is pressed on the impedance connection sheet B; the second half section of the plug conductor core is inserted into the inner hole of the rear insulating sheath.

When the back plug-in plug is inserted on the front plug-in plug, the straight groove body on the front insulation sheath of the back plug-in plug is inserted in the straight groove on the back insulation sheath of the front plug-in plug, the elastic bulge part on the impedance connection sheet A of the back plug-in plug is pressed on the impedance connection sheet B of the front plug-in plug, so that the impedance deployed on the circuit board of the front plug-in plug and the impedance deployed on the circuit board of the back plug-in plug form a parallel connection relation, and the size of the parallel impedance reflects the number of plug-in plugs; the front half section of the experimental signal conductor of the last stacked plug is inserted into the rear half section of the experimental signal conductor of the previous stacked plug.

The intelligent tag impedance sampling socket 4 comprises a socket body 41, wherein a trigger signal button 42, an experimental signal socket hole 43, a ring groove-shaped impedance sampling profile 44 and an antenna 45 for reading an intelligent tag are arranged at the upper end of the socket body, the experimental signal socket hole and the impedance sampling profile are coaxially arranged, an experimental signal plug sleeve 46 is formed between the experimental signal socket hole and the impedance sampling profile, and an impedance sampling sheet 47 is arranged in the impedance sampling profile; the lower end of the socket body is provided with an experimental signal connection terminal 48, an impedance sampling terminal 49 connected with an impedance sampling sheet, a trigger button signal terminal 410 connected with a trigger signal button, and an antenna terminal 411 connected with an antenna.

When the plug-in type plug is inserted on the intelligent tag impedance sampling socket, the front insulating sheath of the plug-in type plug is inserted in the impedance sampling profile, the elastic protruding part on the impedance connecting sheet A is pressed on the impedance sampling sheet, the front half section of the plug conductor core is inserted in the experimental signal socket hole, the front end of the plug conductor core is connected with the rear end of the experimental signal connecting terminal, and the experimental signal connecting terminal, the impedance sampling terminal and the trigger button signal terminal are connected with the signal intelligent processing terminal through wires respectively.

The antenna intelligent measurement and control topology comprises an antenna access control topology, an impedance matching array topology, a transmitting frequency adjustment topology and a harmonic suppression topology, wherein the antenna access control topology is used for enabling an antenna on an intelligent tag impedance sampling socket to be accessed into a signal intelligent processing terminal in a time-sharing mode, the impedance matching array topology is used for optimizing antenna resonant frequency, reducing noise and adjusting Q value, and the transmitting frequency adjustment topology is used for changing the central frequency of antenna transmitting; the harmonic rejection topology is used to reject harmonic components of the antenna.

The intelligent signal processing terminals are at least one, the specific number of the intelligent signal processing terminals can be determined according to the size of the intelligent experimental island, and each intelligent signal processing terminal is connected with a plurality of intelligent tag impedance sampling sockets.

Each signal intelligent processing terminal is connected with the Ethernet switch and is used for collecting impedance data, collecting processing button trigger signals, collecting intelligent label information, storing corresponding data and receiving and transmitting network communication data. Of course, in different embodiments, the signal intelligent processing terminal may also be connected to the host through a field bus.

The host computers are connected with the Ethernet switch, and are used for receiving and transmitting information of the signal intelligent processing terminal and other network equipment, calculating experimental electrical topology after connection, comparing principle topology, intelligent label information writing, information display and network communication service.

In this embodiment, the host 2 includes a first data address control bus 21, a first SPI bus 22, a first power bus 23, a first power module 24, a tag reader/writer module 25, a first data and program storage module 26, a first ethernet bus interface module 27, a first USB interface conversion module 28, a display module 29, a keyboard module 210, and a first single chip microcomputer minimum system 211, which are all composed of a data bus, an address bus, and a control bus. The first power supply module is connected with the power bus; the label read-write module, the first data and program storage module, the first Ethernet bus interface module, the first USB interface conversion module, the display module, the keyboard module and the first singlechip minimum system are respectively connected with the first data address control bus, the first SPI bus and the first power bus.

In this embodiment, the minimum system of the first singlechip is an MSP430 minimum system of an MSP430F5529 singlechip, and the tag read-write module is a 7960RFID tag read-write module of a TRF7960 chip; the first data and program storage module includes MX25L6436 data and program storage module 261 using MX25L6436 chip and MX35LFGE data and program storage module 262 using MX35LFGE chip; the first Ethernet bus interface module is a CH395 Ethernet bus interface module adopting a CH395 chip; the display module is a display module adopting an RA8876 chip; the keyboard module adopts a keyboard module of a CH451 chip. Of course, the specific composition of the host may take other forms known in the art.

Specifically, the 7960RFID tag read-write module consists of a TRF7960 chip and an antenna matching circuit, and has a center frequency of 13.58MHz. SPI interfaces U7-MOSI, U7-MISO and U7-SCLK of TRF7960 are respectively connected with SPI bus interfaces U20-SOMI, U20-SIMO and U20-MSCLK of MSP430 minimum system; SPI bus communication is gated over the U7-SS to U20 connection. 7960RFID tag read-write module is used for smart tag read-write under the control of MSP430 min system 1C.

Specifically, RA8876 shows that SPI buses U21-SOSI, U21-SISO, U21-SCLK of the module are respectively connected with SPI buses U20-SOMI, U20-SIMO, U20-MSCLK of the minimum system of MSP 430; the connection of U21-SS to U20 is used to gate SPI. The display module is used for displaying information such as the intelligent card, the equipment storage data, the equipment working state, the equipment working mode setting and the like.

Specifically, the keyboard module adopts a CH451 chip and 4*4 keyboard modules, and is respectively connected with SPI buses U20-SOMI, U20-SIMO and U20-MSCLK of the minimum system of the MSP430 through SPI buses U22-SOSI, U22-SISO and U22-SCLK of the CH451 chip; the connection of U22-SS to U20 is used to gate SPI. The keyboard is used for inputting intelligent label information, setting working mode parameters of the host, calling storage information of the host, diagnosing faults of the host and the like.

Specifically, the first CH395 Ethernet bus interface module consists of a CH395Q chip and a peripheral circuit; an SPI bus or a serial port is selected to be used through a jumper wire; SPI bus interfaces U10-SDI, U10-SDO and U10-SCK are respectively connected with SPI buses U20-SOMI, U20-SIMO and U20-MSCLK of the MSP430 minimum system 1C; the connection of U10-SS to U20 is used to gate SPI; the CH395 ethernet bus interface module is configured to receive the data from the signal intelligent processing terminal 20 and send information and calculation results to the network device.

Specifically, the first USB interface conversion module includes a USB interface of the MSP430F5529 single chip microcomputer and a USB interface constructed by PL2303GL chips. The U8-TXD and U8-RXD of the PL2303GL chip are respectively connected with U20-UCA1RXD and U20-UCA1TXD of the MSP430F 5529. The UBS interface is used for connecting a local operation terminal with a debugging terminal, and the terminal can perform operations such as function setting, data reading and writing and the like on the host computer of the electric intelligent experimental island system.

Specifically, the MX25L6436 data and program storage module are respectively connected with SPI buses U20-SOMI, U20-SIMO and U20-MSCLK of the minimum system 1C of the MSP430 through SPI buses U11-SOSI, U11-SISO and U11-SCLK thereof; the connection of U11-SS to U20 is used for SPI gating. U11-WSP# is connected to U20, and U11-HOLD is connected to U20 for control. The MX35LFGE data and the program storage module are respectively connected with SPI buses U20-SOMI, U20-SIMO and U20-MSCLK of the minimum system 1C of the MSP430 through SPI buses U12-SOSI, U12-SISO and U12-SCLK; the connection of U12-SS to U20 is used for SPI gating; the connection of U11-WSP# with U20, U11-HOLD with U20 is used for control.

The signal intelligent processing terminal 3 includes a second data address control bus 31, a second SPI bus 32, a second power bus 33, a second power module 34, an antenna matching and tag identification topology 35, a second data and program storage module 36, a second ethernet bus interface module 37, a second USB interface conversion module 38, JATG monitoring interface module 39, a button trigger signal interface 310, an encoded signal interface circuit 311, a button address calculation module 312, a plug impedance interface 313, a plug impedance sampling calculation topology 314, and a second single chip microcomputer minimum system 315, which are comprised of a data bus, an address bus, and a control bus. The second power module is connected with the second power bus; the antenna matching and tag identification topology, the second data and program storage module, the second Ethernet bus interface module, the second USB interface conversion module and the JATG monitoring interface module are respectively connected with the second SPI bus and the second power bus.

The plug impedance interface is connected with the plug impedance sampling calculation topology, and the plug impedance sampling calculation topology is connected with the second data address control bus, so that a plug impedance sampling interface circuit is formed. In a specific implementation, the impedance sampling interface circuit may be a capacitance sampling circuit or a resistance sampling circuit, etc. When the plug impedance sampling interface circuit is a resistance sampling circuit, the plug impedance interface is a plug resistance interface, and the plug impedance sampling calculation topology comprises an adder module connected with the plug resistance interface and a multiplexer connected with the adder module, wherein the multiplexer and the data address control bus; when the plug impedance sampling interface circuit is a capacitance sampling circuit, the plug impedance interface is a plug capacitance interface, and the plug impedance sampling calculation topology comprises a multivibrator connected with a second data address control bus.

The button trigger signal interface is connected with the coding signal interface circuit, the coding signal interface circuit is connected with the button address calculation module, and the button address calculation module is connected with the second data address control bus, so that the button trigger sampling interface circuit is formed.

The antenna access control topology, the impedance matching array topology, the emission frequency adjustment topology and the harmonic suppression topology of the antenna intelligent measurement and control topology are measured and controlled by a second singlechip minimum system, and the method comprises the following steps of:

The antenna access control topology is composed of a multiplexing analog multiplexer and part of I/O of the minimum system of the second singlechip, and of course, the multiplexing analog multiplexer can also be replaced by a multiplexing analog switch, and the multiplexing analog multiplexer in the embodiment is an ADG731 multiplexing analog multiplexer, which is used for time-sharing access of antennas on different intelligent tag impedance sampling sockets to the antenna matching and tag identification topology, and only an antenna inductance coil of one socket is accessed at a time.

The digital variable capacitor in this embodiment is an adjustable capacitor MAX1474, and the digital variable resistor is an adjustable potentiometer MAX5388. The adjustable capacitor MAX1474 array adjusts the resonant frequency of the antenna, reduces noise and transmits the center frequency; the array of adjustable potentiometers MAX5388 adjusts the Q value.

The impedance matching array topology, the transmission frequency adjustment topology and the harmonic suppression topology are shown as dashed rectangle boxes in fig. 12, and the respective access terminals are shown as U7-1, U7-2, U7-3, U7-4, U7-5 and U7-6 in fig. 13, such as U7-1 access U7-1CP, U7-1CM, U7-2 access U7-2CP, U7-2CM, U7-3 access U7-3CP, U7-3CM, U7-4 access U7-4CP, U7-4CM, U7-5 access U7-5LB, U7-5WA, U7-6 access U7-6LB and U7-6WA.

In this embodiment, the minimum system of the second singlechip is an MSP430 minimum system of an MSP430F5529 singlechip, the antenna matching and tag identification topology is a TRF7960 antenna matching and tag identification topology of a TRF7960 chip, and the TRF7960 antenna matching and tag identification topology is connected to the MSP430 through an SPI bus; the second data and program storage module includes MX25L6436 data and program storage module 361 using MX25L6436 chip and MX35LFGE data and program storage module 362 using MX35LFGE chip; the second Ethernet bus interface module is a CH395 Ethernet bus interface module adopting a CH395 chip; the coded signal interface circuit is a coded signal interface circuit adopting an LS148D priority encoder; the button address calculation module is a 74AC11008 button address calculation module adopting a 74AC11008 chip.

Specifically, the button trigger signal processing of the signal intelligent processing terminal is encoded by a 16-bit encoding circuit formed by inputting 16 paths of switching signals U4148-0 to U4148-7 and U5148-0 to U5148-7 to two LS148D through a button trigger signal interface; the processing result is calculated by a 74AC11008 button address calculation module and then is transmitted to the MSP430F5529 through U6-YA, U6-YB, U6-YC and U6-GS; this is done in concert through the data address control bus. Finally, the action buttons are identified by MSP430 minimum system calculations.

Specifically, the second CH395 Ethernet bus interface module of the signal intelligent processing terminal consists of a CH395Q chip and a peripheral circuit; an SPI bus or a serial port is selected to be used through a jumper wire; SPI bus interfaces U10-SDI, U10-SDO and U10-SCK are respectively connected with SPI buses U20-SOMI, U20-SIMO and U20-MSCLK of the MSP430 minimum system of the signal intelligent processing terminal; the connection of U10-SS to U20 is used to gate the SPI bus. The second CH395 ethernet bus interface module is configured to receive and transmit terminal data, transmit information to a network device, and calculate a result.

Specifically, the second USB interface conversion module of the signal intelligent processing terminal is converted into a serial port through the PL2303GL chip and is connected with the MSP430F5529 to form a USB interface, wherein U8-TXD and U8-RXD of the PL2303GL chip are respectively connected with U20-UCA1RXD and U20-UCA1TXD of the MSP430F 5529. The second USB interface conversion module is used for connecting a local operation terminal with a debugging terminal, and the terminal can perform operations such as function setting, data reading and writing and the like on the signal intelligent processing terminal.

Specifically, the MX25L6436 data and program storage module of the signal intelligent processing terminal are respectively connected with SPI buses U20-SOMI, U20-SIMO and U20-MSCLK of the minimum system of the MSP430 through SPI buses U11-SOSI, U11-SISO and U11-SCLK thereof; the connection of U11-SS to U20 is used for SPI gating. U11-WSP# is connected to U20, and U11-HOLD is connected to U20 for control. The MX35LFGE data and program storage module of the signal intelligent processing terminal are respectively connected with SPI buses U20-SOMI, U20-SIMO and U20-MSCLK of the minimum system of the MSP430 through SPI buses U12-SOSI, U12-SISO and U12-SCLK thereof; the connection of U12-SS to U20 is used for SPI gating; the connection of U11-WSP# with U20, U11-HOLD with U20 is used for control.

The antenna parameter measurement and control method of the antenna distributed intelligent experimental island electrical topology identification system in the embodiment comprises the following steps:

(8) The second singlechip minimum system reads standard codes, plug label information, CRC (cyclic redundancy check) information, a start frame and an end frame from a register of a label read-write module, and calculates an error rate; the standard code is a fixed-length and fixed-format code sequence set for calculating the error rate and researching the error code rule, the code sequence is placed in the RFID information tag to form the standard code, and the standard code is compared with a standard code sample stored in the host after the card is read to research the error code rule;

In the electrical topology identification system of the antenna distributed intelligent experimental island, the antenna is positioned on the intelligent tag impedance sampling socket, and the socket can be distributed and flexibly deployed according to the system requirements of the experimental island; the antenna intelligent measurement and control topology is integrally arranged on the signal intelligent processing terminal, and is the basis of multi-antenna automatic switching, impedance intelligent matching and multi-point time-sharing sampling RFID labels. The signal intelligent processing terminal intelligently measures and controls different antennas to obtain information of different labels rapidly and accurately; the plug stacking quantity is obtained by processing the parallel impedance of the stacked plug, and the electrical connection topology can be calibrated and the electrical connection event can be recorded through the intelligent tag; the intelligent label impedance sampling socket can utilize a button trigger signal on the intelligent label impedance sampling socket to calibrate experimental electrical topology and determine connection relation. The electric topology identification system of the antenna distributed intelligent experimental island can solve the technical problems that the current electric experiment cannot remotely monitor and record the operation process and related data of electric topology connection, cannot automatically calculate and check the correctness of the connection topology according to an electric schematic diagram, cannot construct and run digital twins of the experiment and the like.

In order to adapt to the uncertainty of the parameters of the access antenna and the change of the coupling effect of the antenna caused by the change of the number of the access plugs, which are caused by the scattered deployment of the sockets in the electrical topology identification system of the antenna distributed intelligent experimental island, the intelligent measurement and control topology of the antenna is added in the embodiment to improve the coupling effect of the antenna. The antenna parameter measurement and control method in the embodiment is based on the intelligent measurement and control topology of the antenna, and is based on the received power, the error rate and the identification rate, and the Q value, the transmitting power, the center frequency and the harmonic suppression of the antenna are optimally adjusted in a three-closed loop and cyclic iteration mode by screening and adjusting parameters, so that the signal receiving quality and the system response speed are improved.

Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.

Claims

1. Antenna distributed intelligent experimental island electric topology identification system, its characterized in that: the system comprises an Ethernet switch, a host, a signal intelligent processing terminal, an antenna intelligent measurement and control topology, an overlapped plug and an intelligent tag impedance sampling socket, wherein the antenna intelligent measurement and control topology is arranged on the signal intelligent processing terminal;

the host is connected with the Ethernet switch and is used for receiving and transmitting information of the signal intelligent processing terminal, calculating experimental electrical topology after connection, comparing principle topology, writing intelligent label information, displaying information and serving network communication;

The host comprises a first data address control bus, a first SPI bus, a first power module, a tag read-write module, a first data and program storage module, a first Ethernet bus interface module, a first USB interface conversion module, a display module, a keyboard module and a first singlechip minimum system, wherein the first data address control bus consists of a data bus, an address bus and a control bus;

The first power supply module is connected with the power bus;

The label read-write module, the first data and program storage module, the first Ethernet bus interface module, the first USB interface conversion module, the display module, the keyboard module and the first singlechip minimum system are respectively connected with the first data address control bus, the first SPI bus and the first power bus;

The signal intelligent processing terminal comprises a second data address control bus, a second SPI bus, a second power module, an antenna matching and tag identification topology, a second data and program storage module, a second Ethernet bus interface module, a second USB interface conversion module, a JATG monitoring interface module, a button trigger signal interface, an encoding signal interface circuit, a button address calculation module, a plug impedance interface, a plug impedance sampling calculation topology and a second singlechip minimum system, wherein the second data address control bus consists of a data bus, an address bus and a control bus;

The second power module is connected with the second power bus;

The antenna access control topology, the impedance matching array topology, the emission frequency adjustment topology and the harmonic suppression topology of the antenna intelligent measurement and control topology are measured and controlled by a second singlechip minimum system;

the antenna access control topology is composed of a multipath analog switch or a multipath analog multiplexer and part of I/O of a second singlechip minimum system, and is used for time-sharing accessing the antennas on different intelligent tag impedance sampling sockets to the antenna matching and tag identification topology, and only accessing an antenna inductance coil of one socket at a time;

The impedance matching array topology is formed by connecting a digital variable capacitor and a digital variable resistor in series and parallel, and is respectively connected into an antenna matching and tag identification topology by an antenna intelligent measurement and control topology under the measurement and control of a second singlechip minimum system;

the transmitting frequency adjustment topology is formed by forming an array by digital variable capacitors in series-parallel connection, and the antenna intelligent measurement and control topology is connected into the antenna matching and tag identification topology under the measurement and control of a second singlechip minimum system;

2. The antenna distributed intelligent experimental island electrical topology identification system of claim 1, wherein: the first singlechip minimum system is an MSP430 minimum system adopting an MSP430F5529 singlechip, and the tag read-write module is a 7960RFID tag read-write module adopting a TRF7960 chip; the first data and program storage module comprises an MX25L6436 data and program storage module adopting an MX25L6436 chip and an MX35LFGE data and program storage module adopting an MX35LFGE chip; the first Ethernet bus interface module is a CH395 Ethernet bus interface module adopting a CH395 chip; the display module is a display module adopting an RA8876 chip; the keyboard module adopts a keyboard module of a CH451 chip.

3. The antenna distributed intelligent experimental island electrical topology identification system of claim 1, wherein: the second singlechip minimum system is an MSP430 minimum system adopting an MSP430F5529 singlechip, and the antenna matching and tag identification topology is a TRF7960 antenna matching and tag identification topology adopting a TRF7960 chip; the second data and program storage module comprises an MX25L6436 data and program storage module adopting an MX25L6436 chip and an MX35LFGE data and program storage module adopting an MX35LFGE chip; the second Ethernet bus interface module is a CH395 Ethernet bus interface module adopting a CH395 chip; the coded signal interface circuit is a coded signal interface circuit adopting an LS148D priority encoder; the button address calculation module is a 74AC11008 button address calculation module adopting a 74AC11008 chip.

4. An antenna parameter measurement and control method of an antenna distributed intelligent experimental island electrical topology identification system is characterized by comprising the following steps of: the method comprises the following steps: