CN110750401A - Method for testing chip transmission capability - Google Patents
Method for testing chip transmission capability Download PDFInfo
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- CN110750401A CN110750401A CN201910931367.8A CN201910931367A CN110750401A CN 110750401 A CN110750401 A CN 110750401A CN 201910931367 A CN201910931367 A CN 201910931367A CN 110750401 A CN110750401 A CN 110750401A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
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- Microelectronics & Electronic Packaging (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a method for testing chip transmission capacity, which adopts extension board cascade composed of a PCB board card, an extension line arranged on the PCB board card and golden fingers arranged at two ends of the extension line to prolong a signal transmission path, the extension board with known length specification is connected between a chip signal sending end and a chip signal receiving end in cascade until a critical extension board combination ensuring successful signal transmission between the chip signal sending end and the chip signal receiving end is determined, and a signal transmission test result between the chip signal sending end and the chip signal receiving end is obtained by calculating according to the length specification of each extension board in the critical extension board combination and the signal attenuation value of each extension board, the PCB board card and the extension line are adopted to replace a cable to prolong the signal transmission path, so that extension units with smaller granularity can be obtained, and the accuracy of chip transmission capacity test is improved, and the adapter card is not needed to be adopted for cascade connection, so that the error caused by the adapter card is eliminated, and the test precision is further improved.
Description
Technical Field
The invention relates to the technical field of board card testing, in particular to a method for testing chip transmission capacity.
Background
In recent years, with the market demand for high-speed transmission of 10G, 25G, or even 100G, the signal rate in transmission systems has become higher, and the transmission capability of the signal generator-chip has been required to be improved. It is very important for designers of transmission systems to find out the transmission capability of the chip in advance, otherwise, excessive attenuation of transmitted signals may be caused, so that the opposite-end chip cannot accurately receive information, and transmission fails.
Fig. 1 is a schematic diagram of a chip transmission capability testing apparatus in the prior art. As shown in fig. 1, in a conventional chip transmission capability test process, a signal at a chip signal transmitting end is led out by an SMA connector 102 through an adapter plate 101, and then a cable 103 with different lengths is connected to extend a transmission path and then connected to the adapter plate 101 at a chip signal receiving end, so as to test the transmission capability of the chip. However, the cable 103 is limited to 1m/2m/3m/5m, and the transmission capability range of the chip can only be measured approximately, and cannot be measured very accurately. Moreover, the cable 103 cascade needs to be realized through the adapter board 101, and the uncertain attenuation at the adapter board 101 causes extra errors and also causes the problem of low test accuracy.
How to improve the accuracy of the chip transmission capability test is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method for testing chip transmission capability, which can obtain a more accurate test result of the chip transmission capability.
In order to solve the above technical problems, the present invention provides a method for testing chip transmission capability, comprising:
cascading extension plates with known length specifications between a chip signal sending end and a chip signal receiving end until a critical extension plate combination ensuring successful signal transmission between the chip signal sending end and the chip signal receiving end is determined;
calculating to obtain a signal transmission test result between the chip signal sending end and the chip signal receiving end according to the length specification of each extension plate in the critical extension plate combination and the signal attenuation value of each extension plate;
the extension board is composed of a PCB board card, an extension line arranged on the PCB board card and golden fingers arranged at two ends of the extension line.
Optionally, the extension board with a known length specification is cascaded and connected between the chip signal sending end and the chip signal receiving end until a critical extension board combination for ensuring successful signal transmission between the chip signal sending end and the chip signal receiving end is determined, and the method specifically includes:
cascading a plurality of first extension plates with the largest length specification until signal transmission between the chip signal sending end and the chip signal receiving end fails;
replacing one first extension plate with a second extension plate with a length specification smaller than that of the first extension plate until signal transmission between the chip signal sending end and the chip signal receiving end fails;
judging whether an extension plate with a length specification smaller than that of the second extension plate exists or not;
if so, taking the second extension plate as the first extension plate, and entering the step of replacing one first extension plate with a second extension plate with a length specification smaller than that of the first extension plate until the signal transmission between the chip signal sending end and the chip signal receiving end fails;
if not, determining the critical extension plate combination according to the current extension plate combination.
Optionally, the extension board with a known length specification is cascaded and connected between the chip signal sending end and the chip signal receiving end until determining a critical extension board combination for successful signal transmission between the chip signal sending end and the chip signal receiving end, and the method specifically includes:
acquiring an estimated attenuation value between the chip signal sending end and the chip signal receiving end;
setting an initial extension plate combination according to the estimated attenuation value;
replacing an extension plate of the initial extension plate combination until the critical extension plate combination is obtained.
Optionally, the length specification of the extension board includes 20inch, 10inch, 5inch, 2inch and 1inch, and the signal attenuation values are 10dB, 5dB, 2.5dB, 1dB and 0.5dB, respectively.
Optionally, the extension board with a known length specification is cascaded between the chip signal sending end and the chip signal receiving end, specifically:
and connecting the extension plate between the chip signal sending end and the chip signal receiving end in a cascade mode through the golden finger grooves.
Optionally, the extension board with a known length specification is cascaded between the chip signal sending end and the chip signal receiving end, specifically:
and connecting the extension board between the chip signal sending end and the chip signal receiving end in a cascading manner through a splint connector.
Optionally, the PCB board is specifically a flexible PCB board.
Optionally, the gold finger at one end of the extension plate is in a bent female form.
Optionally, each extension board is further provided with a power supply circuit for communicating with an adjacent extension board.
The method for testing the transmission capability of the chip provided by the invention adopts the extension board cascade consisting of the PCB board card, the extension line arranged on the PCB board card and the golden fingers arranged at the two ends of the extension line to prolong the signal transmission path, the extension board with known length specification is connected between the chip signal sending end and the chip signal receiving end in cascade until the critical extension board combination ensuring the successful signal transmission between the chip signal sending end and the chip signal receiving end is determined, the signal transmission test result between the chip signal sending end and the chip signal receiving end is obtained by calculating according to the length specification of each extension board in the critical extension board combination and the signal attenuation value of each extension board, the PCB board card and the extension line are adopted to replace the cable to prolong the signal transmission path, the extension unit with smaller granularity can be obtained, and the accuracy of the chip transmission capability is improved compared with the adoption of the cable extension, meanwhile, the adapter card is not required to be adopted for cascade connection, so that errors caused by the adapter card are eliminated, and the test precision is further improved.
Drawings
In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a chip transmission capability testing apparatus in the prior art;
fig. 2 is a flowchart of a method for testing chip transmission capability according to an embodiment of the present invention;
fig. 3(a) is a schematic structural view of a first extension board according to an embodiment of the present invention;
fig. 3(b) is a schematic structural view of a second extension board according to an embodiment of the present invention;
fig. 3(c) is a schematic structural view of a third extension board according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a specific implementation manner of step S201 in fig. 2 according to an embodiment of the present invention;
fig. 5 is a flowchart of another specific implementation manner of step S201 in fig. 2 according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a method for testing the chip transmission capability, which can obtain more accurate test results of the chip transmission capability.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 2 is a flowchart of a method for testing chip transmission capability according to an embodiment of the present invention; fig. 3(a) is a schematic structural view of a first extension board according to an embodiment of the present invention; fig. 3(b) is a schematic structural view of a second extension board according to an embodiment of the present invention; fig. 3(c) is a schematic structural view of a third extension board according to an embodiment of the present invention.
As shown in fig. 2, the method for testing chip transmission capability according to the embodiment of the present invention includes:
s201: and connecting extension plates with known length specifications between the chip signal sending end and the chip signal receiving end in a cascading manner until a critical extension plate combination which ensures successful signal transmission between the chip signal sending end and the chip signal receiving end is determined.
The extension board is composed of a PCB board card, an extension line arranged on the PCB board card and golden fingers arranged at two ends of the extension line.
In the extension board structure provided by the embodiment of the present invention, as shown in fig. 3(a), 3(b) and 3(c), the extension board 301 is disposed on the PCB board 302, and the gold fingers 303 are soldered to two ends of the extension board 301 and extend outward from the edge of the PCB board 302.
The golden finger 303 can be connected into the golden finger 303 groove and the board clamping connector, so that the extension board with the known length specification is connected between the chip signal sending end and the chip signal receiving end in a cascading mode, and the golden finger 303 groove connection or the board clamping connector connection can be adopted. In addition, a chip signal sending end and a chip signal receiving end for testing the chip transmission capability are usually respectively arranged on the sending end chip and the receiving end chip, and usually, a golden finger 303 groove or a clamping plate connector is also arranged on a board card where the chips are arranged, so that the chip signal sending end and the chip signal receiving end are both suitable for being connected with the extension plate provided by the embodiment of the invention, and an adapter plate does not need to be additionally arranged. The signal attenuation value of the gold finger 303 slot or the splint connector can be quantitatively measured, and compared with the adapter card provided with the SMA connector in the prior art, the signal attenuation value at the connecting part can be more accurately measured and put into calculation.
The PCB board 302 may be a rigid PCB board 302 or a flexible PCB board 302. In embodiments of the present invention, the use of a flexible PCB card 302 is preferred because of the potentially large number of extension boards that may be required.
In addition, in order to reduce the occupation of space in one direction, the golden finger 303 at one end of the extension plate is designed into a bent female form.
Fig. 3(b) shows a schematic plane of the extension board when the extension line 301 is short (e.g. 1inch), but when the extension line 301 is long, the routing manner of the extension line 301 can be flexibly set, for example, the extension line 301 can be arranged in the form shown in fig. 3(c) to avoid the extension board group length being too long.
It should be noted that the extension board provided by the embodiment of the present invention is also advantageous in that it is convenient to lay the power supply line. If the test scheme of the chip transmission capability in the prior art is adopted, the sending end chip and the receiving end chip need to be respectively provided with a power supply module, and more space is occupied. The extension board provided by the embodiment of the invention adopts the PCB 302 as the carrier of the extension line 301, the PCB 302 can be laid with a power supply circuit, and the sending end chip and the receiving end chip can be powered by one power supply module, so that the test space is saved. Therefore, in the method for testing the chip transmission capability provided by the embodiment of the invention, each extension board can be further provided with a power supply circuit for communicating with the adjacent extension board.
By adopting the extension board provided by the embodiment of the invention, extension boards with different length specifications are preset and tested to obtain the signal attenuation values of each extension board and a connector (a golden finger 303 slot or a splint connector), and then one or more extension boards are cascaded between a chip signal sending end and a chip signal receiving end until a critical extension board combination with the longest signal transmission path for ensuring successful signal transmission is obtained.
S202: and calculating according to the length specification of each extension plate in the critical extension plate combination and the signal attenuation value of each extension plate to obtain a signal transmission test result between the chip signal sending end and the chip signal receiving end.
Different signal transmission path lengths are formed by combining extension boards with different length specifications, the signal attenuation values of the extension boards and the connectors are known, and after a critical extension board combination is obtained, a signal transmission test result between a chip signal sending end and a chip signal receiving end can be obtained by calculating according to the length specification of each extension board in the critical extension board combination and the signal attenuation value of each extension board.
The method for testing the chip transmission capability provided by the embodiment of the invention adopts the extension board cascade consisting of the PCB board card, the extension line arranged on the PCB board card and the golden fingers arranged at the two ends of the extension line to prolong the signal transmission path, the extension board with known length specification is connected between the chip signal sending end and the chip signal receiving end in cascade until the critical extension board combination ensuring the successful signal transmission between the chip signal sending end and the chip signal receiving end is determined, the signal transmission test result between the chip signal sending end and the chip signal receiving end is obtained by calculating according to the length specification of each extension board in the critical extension board combination and the signal attenuation value of each extension board, the PCB board card and the extension line are adopted to replace the cable to prolong the signal transmission path, the extension unit with smaller granularity can be obtained, and the accuracy of the chip transmission capability test is improved compared with the adoption of the cable extension, meanwhile, the adapter card is not required to be adopted for cascade connection, so that errors caused by the adapter card are eliminated, and the test precision is further improved.
Fig. 4 is a flowchart illustrating a specific implementation manner of step S201 in fig. 2 according to an embodiment of the present invention.
As shown in fig. 4, on the basis of the foregoing embodiment, in the method for testing chip transmission capability provided in the embodiment of the present invention, step S201 may specifically include:
s401: and cascading a plurality of first extension plates with the largest length specification until the signal transmission between the chip signal sending end and the chip signal receiving end fails.
S402: and replacing a first extension plate with a second extension plate with a length specification smaller than that of the first extension plate until the signal transmission between the chip signal sending end and the chip signal receiving end fails.
S403: judging whether an extension plate with a length specification smaller than that of the second extension plate exists or not; if yes, go to step S404; if not, the process proceeds to step S405.
S404: step S402 is performed by using the second extension board as the first extension board;
s405: and determining the critical extension plate combination according to the current extension plate combination.
In specific implementation, if extension boards with length specifications of 20inch, 10inch, 5inch, 2inch and 1inch are designed in advance, the length specifications are respectively marked as extension board No. 1, extension board No. 2, extension board No. 3, extension board No. 4 and extension board No. 5 corresponding to signal attenuation values of 10dB, 5dB, 2.5dB, 1dB and 0.5 dB. Based on the above steps, a plurality of extension boards No. 1 are firstly connected between the chip signal sending end and the chip signal receiving end until one of the extension boards No. 1 is taken out, and the signal transmission is successful, and the signal transmission is failed when the extension board No. 1 is connected. And replacing the extension plate No. 1 with the extension plate No. 2, replacing the extension plate No. 2 with the extension plate No. 3 if the signal transmission fails, and cascading 1 extension plate No. 3 again on the basis if the signal transmission succeeds, and so on.
Fig. 5 is a flowchart of another specific implementation manner of step S201 in fig. 2 according to an embodiment of the present invention.
As shown in fig. 5, on the basis of the foregoing embodiment, in the method for testing chip transmission capability provided in the embodiment of the present invention, step S201 may specifically include:
s501: and acquiring an estimated attenuation value between a chip signal sending end and a chip signal receiving end.
S502: and setting an initial extension plate combination according to the estimated attenuation value.
S503: the extension plate of the initial extension plate combination is replaced until a critical extension plate combination is obtained.
In order to reduce the number of experiments, an estimated attenuation value between a chip signal sending end and a chip signal receiving end can be obtained according to historical experience, chip design values and the like, and an initial extension plate combination is selected according to the estimated attenuation value so as to quickly obtain a critical extension plate combination.
The above description details the testing method for chip transmission capability provided by the present invention. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. A method for testing chip transmission capability is characterized by comprising the following steps:
cascading extension plates with known length specifications between a chip signal sending end and a chip signal receiving end until a critical extension plate combination ensuring successful signal transmission between the chip signal sending end and the chip signal receiving end is determined;
calculating to obtain a signal transmission test result between the chip signal sending end and the chip signal receiving end according to the length specification of each extension plate in the critical extension plate combination and the signal attenuation value of each extension plate;
the extension board is composed of a PCB board card, an extension line arranged on the PCB board card and golden fingers arranged at two ends of the extension line.
2. The method according to claim 1, wherein an extension board with a known length specification is cascaded between a chip signal transmitting terminal and a chip signal receiving terminal until a critical extension board combination ensuring successful signal transmission between the chip signal transmitting terminal and the chip signal receiving terminal is determined, and the method specifically comprises:
cascading a plurality of first extension plates with the largest length specification until signal transmission between the chip signal sending end and the chip signal receiving end fails;
replacing one first extension plate with a second extension plate with a length specification smaller than that of the first extension plate until signal transmission between the chip signal sending end and the chip signal receiving end fails;
judging whether an extension plate with a length specification smaller than that of the second extension plate exists or not;
if so, taking the second extension plate as the first extension plate, and entering the step of replacing one first extension plate with a second extension plate with a length specification smaller than that of the first extension plate until the signal transmission between the chip signal sending end and the chip signal receiving end fails;
if not, determining the critical extension plate combination according to the current extension plate combination.
3. The method according to claim 1, wherein the step of connecting extension boards of known length specifications in cascade between a chip signal transmitting terminal and a chip signal receiving terminal until determining a critical extension board combination for successful signal transmission between the chip signal transmitting terminal and the chip signal receiving terminal comprises:
acquiring an estimated attenuation value between the chip signal sending end and the chip signal receiving end;
setting an initial extension plate combination according to the estimated attenuation value;
replacing an extension plate of the initial extension plate combination until the critical extension plate combination is obtained.
4. The test method of claim 1, wherein the length specifications of the extension board include 20inch, 10inch, 5inch, 2inch and 1inch, corresponding to signal attenuation values of 10dB, 5dB, 2.5dB, 1dB and 0.5dB, respectively.
5. The testing method according to claim 1, wherein the extension board with a known length specification is connected between a chip signal sending end and a chip signal receiving end in a cascade manner, specifically:
and connecting the extension plate between the chip signal sending end and the chip signal receiving end in a cascade mode through the golden finger grooves.
6. The testing method according to claim 1, wherein the extension board with a known length specification is connected between a chip signal sending end and a chip signal receiving end in a cascade manner, specifically:
and connecting the extension board between the chip signal sending end and the chip signal receiving end in a cascading manner through a splint connector.
7. The testing method of claim 1, wherein the PCB board is specifically a flexible PCB board.
8. The test method of claim 1, wherein the gold fingers on one end of the extension plate are in the form of bent nuts.
9. The method of claim 1, wherein each of said extension strips is further provided with a power supply line for communicating with an adjacent extension strip.
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| CN201910931367.8A CN110750401B (en) | 2019-09-29 | 2019-09-29 | Method for testing chip transmission capability |
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| CN201910931367.8A CN110750401B (en) | 2019-09-29 | 2019-09-29 | Method for testing chip transmission capability |
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| CN110750401A true CN110750401A (en) | 2020-02-04 |
| CN110750401B CN110750401B (en) | 2022-07-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111965529A (en) * | 2020-08-28 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Chip signal transmission loss test method, test device and readable storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107949153A (en) * | 2017-12-05 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of device for strengthening high speed transmission of signals distance |
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2019
- 2019-09-29 CN CN201910931367.8A patent/CN110750401B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107949153A (en) * | 2017-12-05 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of device for strengthening high speed transmission of signals distance |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111965529A (en) * | 2020-08-28 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Chip signal transmission loss test method, test device and readable storage medium |
| CN111965529B (en) * | 2020-08-28 | 2022-12-23 | 苏州浪潮智能科技有限公司 | Chip signal transmission loss test method, test device and readable storage medium |
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| CN110750401B (en) | 2022-07-22 |
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