CN1120197A - Scalable system interrupt structure for a multiprocessing system - Google Patents

Abstract

This interrupt subsystem provides for queueing of interrupts from many sources, and for queueing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software.

Description

A kind of scaleable system break structure of multiprocessing system

The present invention relates to data handling system, relate more specifically to interrupt source in a kind of data handling system and a kind of method that sends the interrupting information signal between interrupt handler.

In data handling system, with interrupting being sent in the signal that has interrupt condition on the given interrupt source to processor.This interrupt source can be such as require adapter card of certain service on a system bus.The service of this requirement can be to start a secondary data to transmit, or reads a status register that had just changed.

When processor being adjusted to the acceptance interruption or being called the permission interruption, then when accepting interruption, processor will start Interrupt Process.This Interrupt Process comprises usually interrupts this interrupt source, carries out some function and this interruption that resets/close according to the type of this interruption.

In traditional system, also be provided with interrupt priority level.Be energized if be carved with more than one look-at-me when given, then use interrupt priority level to come notification processor which interruption of service earlier at one.

Designed interruptable controller such as some necessary look-at-me functions of exchange of unloading such as the look-at-mes that resets.These interruptable controllers be represented as Intel (Intel) 8259 controllers, it is described in Intel's data product catalogue in 1981, and (this products catalogue can be from Intel company's literature department, 3065, Bowers Avenue, Santa Clara, CA buys) thus quote at this material as a setting.These interruptable controllers can monitor a plurality of interrupt sources, and only come interrupt handler with a single interrupt line.

The method of current transmission look-at-me mainly is to design for the single processor system with minority interrupt source or priority.Most systems sends interruption by one or more interrupt line of hard wire on flat board.In multicomputer system, when existing more than one processor and can serve a certain interruption, this transmission look-at-me technology can increase the complicacy of bus.A look-at-me from each interrupt source must route to each processor or the interruptable controller that can serve this interruption.

Attempt to satisfy the needs of multiple deal with data disposal system, its special-purpose interruptable controller is arranged by each processor requirement in the system.This method not only price is high, and does not allow to manage concentratedly and generate and deliver to a plurality of processors by multiple source and go the interruption of serving.

Therefore, just need a kind of can the expansion, allow the method for many interrupt sources and priority.In addition, the method that needs a kind of transmission interrupting information signal of the multiprocessing system that be used to manage a plurality of processors and a plurality of interruptable controllers.

Current interrupt system is the dedicated hardware of depended software to some extent.Change the number or the type of interrupting and to change specific operating system software.Need one the interruption subsystem that the bottom hardware interrupt structure is had software independence is provided.

The present invention is that in the data handling system is interrupted subsystem.This interruption subsystem can be scaled to senior multiprocessor (MP) system from rudimentary single processor system.This interruption subsystem provides the cueue of interrupt from many interrupt sources, and provides the optimum processor in the MP system of the cueue of interrupt to.This is by being divided into two-layer reaching with external interrupt mechanism, and one interrupts Route Selection layer and an interruption display layer (presentation layer).Interrupting the Route Selection floor sends to interrupt condition and interrupts in the display layer in the suitable interrupt management district.Interrupt the Route Selection layer can demarcate into support rudimentary/low-cost and senior/high performance system.Interrupt on the system software of display layer with the interrupt source service of being communicated to/this interruption of processing.This software is accepted this interrupt condition and this interrupt condition of being responsible for resetting.This software also indicate the acceptance of interruption and notice interrupt display layer treated this interruption.

By in interrupting subsystem, providing two-layer, just can write the application software or the system software that are independent of interrupt source or type and first floor system hardware configuration.Interrupt the details of Route Selection layer to the hidden a kind of specific hardware tools of software.Interrupt display layer connected system and/or application software, and provide and be independent of the functional of hardware.

The present invention also defines a kind of abort packet agreement that is used for interrupt request and interruption reset condition.Adopted the address bus grouping, and more advantage has been arranged than hard wire method.When having an interrupt request, IOC is the request address bus just when an interrupt source (after this being called an I/O controller or IOC).When authorizing its this bus, IOC just sends an interrupt request grouping by address bus.Interruptable controller is handled this information and is sent a look-at-me to processor.In a multiprocessing system, interruptable controller can send to interrupting information a suitable processor.When this processor had been finished Interrupt Process, it just reminded interruptable controller to send the grouping that resets to IOC.Then, interruptable controller request address bus.When authorizing its address bus, interruptable controller just sends an interruption reset condition grouping by address bus.

Owing to for each address a plurality of data transfer cycles are arranged usually, so data bus uses manyly than address bus.Send interrupting information by address bus, just might use under-utilized resource, address bus, and do not use busy data bus.Use another advantage of address bus to be that in a preferred embodiment, all IC (integrated circuit) chip on the system bus all uses whole address bus.Yet these IC chips also not all use whole data bus.Thereby just can utilize the address wire in system in pin and the wiring that the abort packet of passing through on the address bus need not add.This point is different with the existing method of using some different interrupt lines.

Because the I/O of memory mapped is the most extensive method that is used to carry out input and output function, just be used as sending the method for abort packet with it.As the most popular method of carrying out I/O, all chips on the system bus had the I/O that carries out memory mapped volume.

In a preferred embodiment, the definition of abort packet allows from each 16 interrupt sources among 512 IOC.One has 256 interrupt priority levels.Can there be 256 ISR in each system.This just allows the abort packet definition to be used for machine-wide widely.The position of all withing a hook at the end in interrupt request grouping and interruption reset condition grouping, more necessary information in the abort packet can be transmitted with them in system.Thereby this grouping definition can provide extensibility in the system in future.

Hardwired interrupt system early only provide seldom relevant interrupt direct information.The bus group technology provides whole interrupt sources, IOID, priority and server info in the same time and place.Except system flexibility, this makes that the interruption debugging is greatly simple and easy.Which kind of interruption reset condition what the address bit 0-2 that information can be put into the reservation of interruption reset condition grouping notified that IOC sending is.

Owing to interrupt transmitting they and other interruption and other system operation queuing by address bus.This is helpful in debugging, and is more directly perceived and still less asynchronous with system because this make to interrupt system-level.

Because interrupting information is in each field that is defined in the abort packet rather than resembles hard wire on flat board that this interrupt system is programmable.Interrupt priority level, server number, interrupt source and I/O controller ID (identifier) are available this packet configuration programmings.Thereby this interrupt structure is more more flexible than the system of hard wire.

Therefore, one object of the present invention is for providing a kind of improved data handling system.

Another object of the present invention is for providing a kind of improved interruption subsystem in a data disposal system.

Another purpose of the present invention is for providing a kind of improved interrupt system in a multi-processor data process system.

A further object of the present invention is for providing a kind of method of improved transmission look-at-me.

Further describe above-mentioned and other purpose of the present invention with reference to the accompanying drawings, wherein:

Fig. 1 is the block scheme of a data disposal system;

Fig. 2 is the block scheme by the equipment of an interruptable controller and a data processor interface;

Fig. 3 illustrates the parts with a logical server of software queue interface;

Fig. 4 illustrates the inner structure of an interruptable controller;

Fig. 5 illustrates the structure of hardware and software queue;

Fig. 6 is the process flow diagram that comprises the I/O controller, interrupts the overall interruption subsystem of Route Selection layer and interruption display layer;

Fig. 7 is the bus timing figure of an interrupt request;

Fig. 8 is the bus timing figure of an interruption reset condition;

Fig. 1 shows the logical view of a data disposal system 20.System interconnection device 22 allows to transmit data between the various parts of system: processor 24, storer 26 and the I/O28 that connects via an i/o controller (IOC) 30 that directly is connected on the system interconnection device 22.Other I/O of connection of from processor and the available system bus 29 of IOC also can be arranged.System interconnection connects 22 and can be one of multiple not isostructure (for example, a system bus, a switch etc.), and depends on system.In this preferred embodiment, this system interconnection device is a system bus.

Require the external interrupt structure of native system can cover broad system requirements scope: the multi-user system that constitutes to hierarchy from simple single user personal computer by multiprocessor.Prior art is the such scope of addressing effectively.It is compatible that the DLL (dynamic link library) of interrupt system and logical view require.A kind of typical interrupt structure has been shown among Fig. 2, and an equipment 32 (I/O28 and the IOC30 that comprise Fig. 1) that wherein can generate an interruption is by an interruptable controller 34 and service processor 24 interfaces.The present invention determined a kind of can on wide system scope, calibrate but still keep the improved interrupt control structure of compatible programming model.

Referring to Fig. 3, the system logic view of observing from the system software aspect is the individual formation of n (reaching 256) of incident.In each software queue 42 and 43, the precedence table of an incident is arranged.Comprise the interruption (such as external interrupt) of hardware generation and the interruption (such as interrupting between processor) that software generates in these incidents from IOC. Individual queue 42,43 is associated with a logical server.Formation 0 to m is associated with logical server #0, and formation m+1 to n then is associated with logical server #1.Can dispose other logical server similarly with other processor.In a single-processor system, have only a server, therefore have only a formation.In a multicomputer system, a formation with each relational processor will be arranged, and have an omnidistance formation related at least with the processor group of regarding a server as.For example, Fig. 3 shows the individual queue 42 related with a processor 40, and an omnidistance formation 44 related with the combination of processor 0 to m.The logical server #0 at 38 places is regarded in the combination of processor 40 as.Similarly, individual queue 43 is related with a processor 41, and an omnidistance formation 45 then is associated with the combination of processor m+1 to n.The logical server #1 at 39 places is regarded in the combination of processor 41 as.For multicomputer system, must there be a kind of mechanism to determine which processor can use for each omnidistance formation.This mechanism is by using processor register (APR) (following will further describing with reference to Fig. 4) to provide.

Then see Fig. 3, the server that related with individual queue 42,43 is in 0x00 to the 0xff scope number.Each processor 40,41 in this complex is assigned to the server that makes progress from 0x00 number, and the formation (being omnidistance formation) of serving a plurality of processors then is assigned to the server that descends from 0xff number.Queue length (being the length of the precedence table in the formation) is then relevant with realization, but the degree of depth is at least 1.

External interrupt rise in IOC, the complex other processor and from other source in the system (for example, an emergency power off warning interrupt).Though different sources requires different physical signalling transmit mechanisms, but for server logical outward appearance (for the logical server of omnidistance formation or for the server of other formation) then is that this point will be further described below with a formation headed by the prepreerence incident.Limit priority (promptly prepreerence) interrupts being defined as 0x00 lowest priority interrupt (promptly least preferential) and then is defined as 0xff.Therefore, interrupt level 0x55 is more preferential but compare not preferential with interrupt level 0x00 than interrupt level 0xff.

The present invention is divided into external interrupt mechanism (being interruptable controller) two-layer: (i) interrupt display layer and (ii) interrupt the Route Selection layer.This two-layer being illustrated in Fig. 4 and 6.Referring to Fig. 4, interrupt comprising the register related in the display layer 50 with processor or server.Single interruption is set up and handled to operating system software and these processors or server interface.Interrupt display layer 50 and only have definition by the number change of an intrasystem processor or server.Interrupting Route Selection layer 52 will be sent to the destination from the interruption of interrupt source, and be subjected to the influence of the character of bigger particular tool.System software must be set up the configuration of interrupting Route Selection layer 52 when energized, but need be on the basis of interrupting one by one and this interruption Route Selection layer interface.

Describe the register that is used for management interrupt below briefly, and they will be described in more detail afterwards.* spendable processor register (APR)

-interrupt the Route Selection layer to be used for understanding which processor and to can be used for interrupting as sending

The available register of a particular server.APR is intended to be used for omnidistance team

Be listed as, and be illustrated in 39 places of Fig. 4.* omnidistance queuing interrupt request register (G_QIRR)

-this register can be used as a byte or 4 bytes (32 words) write, and shows

Go out 73 places at Fig. 4.

-in symmetrical MP (SMP) system, be used as the server team of a non-processor special use

Row.

-constitute by two registers:

* omnidistance override request register (G_MFRR), it is a MFRR.

* interrupt source illustrates register (ISSR)

-in smp system, be used for disposing the source that a G_MFRR interrupts to say

Bright (seeing XIOR).* the interrupt request register (QIRR) of lining up

-this register can be used as a single byte or 4 bytes (32 words) write, and

Be illustrated in 61 places of Fig. 4.

-each processor at least one, add the server queue of each non-processor special use

One.

-constitute by two registers:

* override request register (MFRR)

The priority of override request in the-preservation formation

-this register can be read back by software and occur writing with affirmation.

* interrupt source illustrates register (ISSR) * external interrupt request register (XIRR)

One of-each processor is illustrated in 60 places of Fig. 4, and provides one to system software

Individual single source identifier supplies the usefulness of interruption.

-constitute by two registers

* current processor priority register (CPRR)

-this register comprises current processor priority by software upgrading

-refer to when the loading of software on a certain address of XIRR issue

When making, the loading that this register is updated to by being performed refers to

The represented priority of interrupt of XIRR data that order is derived.

* external interrupt source-register (XISR)

The source of the waiting interruption of-indication (if there is not the interruption of wait, then is

Value 0).* external interrupt vector register (XIVR)

Each interrupt level is one among-each IOC, is illustrated in 70 places of Fig. 4.

-be used for determining the priority of each interrupt level

-can be used for specific interruption is directed to specific server.Interrupt the Route Selection layer

The target of interrupting the Route Selection layer is for to be directed at the processor of operating on the lowest priority with prepreerence interrupt request, i.e. optimum processor.Its optimum capacity is to interrupt Route Selection and avoid an interruption is delivered to than a processor that moves on the higher priority of the request that enters.Depend on system requirements, the present invention allows to realize in a different manner interrupting the Route Selection layer.Therefore, the precision that different realizations can be different is come near above-mentioned target, and this will present different time-delays in the Route Selection of interrupt request.Big more by the contemplated system load that interrupt to cause, then interrupt in order to reach correct system performance Route Selection hardware approaching target near more.In order to reach this target all sidedly, interrupt Route Selection hardware and must understand the state of system (be in each cycle the content of processor priority and all IPQ) accurately all sidedly.This is impossible in the practice, because: (i) have more potential interrupt request in interrupting the Route Selection layer than hardware queue; Perhaps (ii) processor priority could propagate into from processor with several cycles possibly and interrupts the Route Selection layer, and makes the processing priority in each correct cycle have uncertainty to a certain degree in interrupting the Route Selection layer.Queue depth's problem is to control by the interrupt request message that requires IOC to resubmit to be interrupted Route Selection hardware refusal.This allows to interrupt Route Selection hardware and realizes that a kind of queue depth (being at least 1) satisfies expection situation to a certain degree, overflows situation and handle all with the interruption reject mechanism.System software is not known reject mechanism, and the latter only is rendered as the different stand-by period to affected interrupt request.When first a request being sent to a processor, may and not know real processor priority owing to interrupt Route Selection hardware, therefore open circuit in the middle of by selecting hardware for the first time a request to be distributed to after the specific processor, it must can change its operator precedence level and get ready software.Do not consider that the processor priority that is changing can cause pirority inversion and serious system performance to reduce and (enter formation if having an interruption lower than current processor priority, perhaps this interruption that enters formation hindered an interruption that has than processor higher priority enter team to and interrupt this processor, pirority inversion just appears); The interruption that enters formation will can not get service be reduced to below the interrupt priority level of queuing in the priority of processor before.Moreover available interruption reject mechanism overcomes the queue resource problem.By interrupting refusing back IOC, IOC just opens circuit as centering and comes work by the expansion of selecting layer queuing mechanism.

Unless one of following incident occurs, an interrupt source only sends a specific interruption once to interrupting the Route Selection layer via interface 71 (Fig. 4) usually: (i) interrupt the Route Selection layer and refused this interruption; Perhaps (ii) software writes XIRR with an XISR value that equals interrupt source and the interruption of reset this interruption and this interrupt source still (does not promptly obtain service) as yet in wait.This point will further describe with reference to Fig. 6 below.

Various different realization of interrupting Route Selection layer 52 is possible, comprising (i) formation, perhaps (ii) for a plurality of exterior interrupt queuing registers of high level machine for a single-element of each processor that constitutes by a kind of external interrupt priority of rudimentary machine.The actual hardware queuing that the hardware assurance is interrupted in the Route Selection layer realizes that for the system software with interruption display layer interface be transparent.Have the known queueing technique of many kinds can support utilization in the present technique, such as United States Patent (USP) 4,807, a hardware register file of the entity of preserving with priority order described in 111 is quoted at this as a reference.Key being characterized as with an interruption display layer of the present invention used this formation.This interruption display layer provides centering to open circuit by the software transparency of selecting the bottom queuing mechanism in the layer.

When system forms, form software and must determine to interrupt the configuration of Route Selection layer, comprising supporting a plurality of logical servers, which logical server which processor supports, and with which server of which interrupt oriented.This is to finish by the register that reads some instrument special use or by configuration information is stored among the ROM.Specify which processor in which logical server formation, to work with APR.Hardware is depended in specific composition decision-making, and changes with different hardware toolses.Unique requirement is to make a strategic decision in any case, all above-listed composition information must be placed among the APR to visit later on for interrupting the Route Selection layer.Interrupt display layer

Interrupt mechanism has a physical queue (Fig. 5 57) of the request block that is associated with the individual queue 42,43 of Fig. 3 between processor in system storage.In the formation of these software administrations each is by software order maintenance according to priority.The realization of formation does not define in interrupt mechanism, goes definition but leave operating system software for.The realization of individual queue can be different, and this depends on the frequency of utilization of expection.What be associated with individual queue is a prepreerence request register (MFRR) (in the system storage space).When program needed service that a par-ticular processor carries out, it just entered a request block in the formation of this processor, and its judges that new request is whether on higher priority, if just the value of the priority that will newly ask writes among the MFRR.When a program during, just the priority value of next request in the formation is loaded among the MFRR a services request dequeue.If move back formation after the team become empty, just lowest priority values (0xff) is loaded among the MFRR.A value that is different from 0xff among the MFRR indicates the interrupt hardware of interrupting in the Route Selection layer look-at-me of this priority to be sent to the processor of serving this formation at 72 places.

Each preparation implement has the interrupt management district of a memory mapped associated therewith, wherein comprises external interrupt request register (XIRR) 60.XIRR is one 4 byte facility and is made up of two fields: current processor priority register (CPRR) and external interrupt source-register (XISR).

The operator precedence level that comprises processor among the CPPR.CPPR can be write to prevent bothering of lower priority request by system software.Only when its CPPR field is hanged down than the priority of interrupt request, interrupt the Route Selection layer just with an interrupt request guiding processor.The current operator precedence level of this processor of interrupt hardware in the Route Selection layer is interrupted in the system software storage with notice as the CPPR of a byte register.

In order to judge interrupt source, system software is by reading XISR to load instructions of XIRR issue.Value among the XISR specifies interrupt source (if be an IOC, then to represent its IOID and level; If be a processor, then represent which server queue).According to this information, software just can determine to call suitable program or process comes to be this break in service.XISR represents opening circuit by the state of a write-only register selecting layer from a read-only register that interrupts the Route Selection layer and the centering that supplies storage operation to use for load operation.Because hardware will write an a signal (rather than signal of the XISR position itself of writing direct that is interpreted as an interruption reset condition is sent to interrupt source to of XISR, this point will be described below), what therefore, write does not read natch.When with one 4 byte-accessed guiding XIRR, must be with CPPR atom level ground (atomically) visit XISR.For interruption from IOC, the IOID of the high bit representation IOC of XISR, low 4 nearly 16 sources (or level) that then define among the IOC of XISR field.Some kinds of values of this register have the implication of regulation.Will be further described below XISR.

The interruption display layer of interrupt mechanism is to embody by an interrupt management district of each processor in the system, as shown in following table 3.The interrupt management district is in the storage space of data handling system.The base address (BA) that the start address in the interrupt management district of processor is called the remainder of this file.The BA of each processor is different (being that each processor has an independently interrupt management district), and all addressable these zones of any one processor (to its not protection).The BA of a processor sets up when configuration.The layout in interrupt management district is as follows:

The address	Byte	0	Byte 1	Byte 2	Byte 3	Note
							BA＋0	?CPPR	????XISR			The XIRR that has no side effect
BA＋4	?CPPR	????XISR			XIRR with loading/storage spinoff
						BA＋8	?DSIER	????DSIER			Data-storing interrupt error register
BA＋12	?MPRR	????ISSR			Desired QIRR
						BA＋16	?MPRR	????ISSR			Optional 2QIRR
BA＋20	?MPRR	????ISSR			Optional 3QIRR
						000	?MPRR	????ISSR			Optional nQIRR

Table 1: interrupt management district: interrupt the queuing of display layer register

Fig. 5 illustrates the mutual relationship between the previously described individual queue.Show the software queue 42,43 that provides interface compatibility, that be independent of hardware of system software at 53 places for a specific processor X.XIRR register and the processor X interface of formation X by being illustrated in 54 places.This XIRR register can be revised by the interruption Route Selection layer at 55 places.The Route Selection layer at 55 places must be taken multiple interrupt type into account to the selection step of limit priority.To be maintained in hardware interrupts in the hardware queue at 56 places provides (present) to give to interrupt Route Selection layer 52 at 58 places.These hardware interrupts are each the IOC hardware queues that derives from 51 places.In addition, the interruption of software generation also can offer and interrupt Route Selection layer 52.These software interruption (such as interrupting between processor) are to remain in the formation of a software administration at 57 places, and offer at 59 places by the MFRR register and to interrupt the Route Selection layer.

Generally speaking, offer the software queue 42 and 43 combinations of system software among Fig. 4 for the formation of software administration and hardware interrupts formation.Thereby hardware queue can be distributed between Route Selection layer and the IOC.Moreover the formation with software administration that hardware generates is to use a unified interface XIRR register to offer system software.Interrupt Process

The main-process stream of Interrupt Process is illustrated among Fig. 6.74, when an IOC had the interruption of needs service, it judged that at first whether this interruption is that the interruption medium priority that need provide is the highest.If exist an interruption that does not obtain the higher priority of serving as yet, then at first provide this interruption 75.76, IOC selects the XIVR that is associated with specific interruption to be supplied, and will deliver to interruption Route Selection layer together with a number in the source of asking among IOCIOID and the indication IOC to serve from the server of this XIVR number and priority.77, interrupting the Route Selection floor just can use server in the interrupting information number with a specific processor of interrupt oriented (server) 98, if perhaps during par-ticular processor in the server number not corresponding system, then select one will interrupt sending to its processor 78.In this back one situation, the hardware of selecting interruption to be sent to which processor depends on instrument, and can be optimized according to the system design starting point (for example, the performance of the cost of rudimentary machine or senior machine).The information that enters this Route Selection decision block 78 has the priority (CPPR value) that each processor operating and other priority (for example, the MFRR of this processor or G_MFRR) of waiting in line this processor.If 79, the interrupt priority level of accepting from IOC is less than or equal to the priority of interrupt that exists the queuing, then should interrupt refusing back IOC 98, IOC then must provide (represent) this interruption (for example, having passed through after a certain regular time amount) again in the moment after a while.If be placed on more from the interruption of IOC among the XIRR of target processor 80 an interruption of lining up more preferably, then 95 with the front be placed on interruption among the XIRR return to it from IOC, and substitute it in the new interruption of 81 usefulness.Though interrupting a kind of specific instrument of Route Selection layer mechanism can select this cueue of interrupt is provided with the back demonstration in the Route Selection layer, but in this preferred embodiment, the Route Selection layer returns to interrupt source with this interruption, and interrupt source then provides this interruption again in the moment after a while.The loading of XISR must be minimum (atomic); Be that hardware must guarantee system software and interrupt the Route Selection layer and can not attempt to visit XISR (for example, when hardware was just attempting to upgrade XIRR with the request of a higher priority, processor was attempting to read this XIRR) simultaneously.

83, when XISR comprised a nonzero value, hardware just sent to this processor via the look-at-me that enters processor hardware with a look-at-me.When having sent look-at-me, and when 84 allow to interrupt, software just receives this look-at-me and in 85 beginning Interrupt Process.Software when Interrupt Process begins 86 read XIRR and should value be saved in the Interrupt Process end always till.86, when software read XIRR, the interrupt priority level that hardware is then represented XISR was placed among the CPPR and XISR is set to 0.CPPR is set to the priority of interrupt value, prevent that software from carrying out following operation: when the service of this interruption begins, therefore processor priority will equal this priority of interrupt, interrupt the interruption that the Route Selection layer will not use a lower priority and interrupt this service.Be set to 0 by XISR, just make the look-at-me to processor not be energized, and when if processor reads XIRR after a while, the value 0 among the XISR can notice not have waiting interruption.In case processor reads the XIRR at BA+4 place and an interruption has been offered this processor, this just notifies hardware-software will begin to handle this interruption, and therefore interrupting the Route Selection layer can not preemption can not cancel this interruption.Read after the XIRR, which Interrupt Service Routine is the value in the XISR field of software use XIRR determine to call.87, if XISR points to QIRR, then 88, software removes this prepreerence entries in queues from this formation, and the MFRR among the QIRR is set to the value of the priority of the new override item in the formation, if formation this moment is empty, and the value of being set to 0xff then.If 89, XISR points to G_QIRR, and then 90, software removes prepreerence entries in queues from whole process, and the G_MFRR among the G_QIRR is set to new prepreerence priority value in this formation, if formation at this moment is empty, and the value of being set to 0xff then.If XISR does not point to one of software queue, then it is to point to an external interrupt service routine, and software calls suitable device driver 91 and serves this interruption.Externally under the situation of Zhong Duaning, device driver was after serving this interruption, in the process of service routine, the interruption among the IOC will be reset (for example, most of hardware will by issue to reset the interruption among the IOC of a storage instruction of a certain address in the address space of IOC).No matter what interrupt source is, 92, when service finishes, software will write XIRR at the BA+4 place with the value of reading from XISR and preservation when break in service begins.When writing XIRR at the BA+4 place, CPPR will be configured to store in the data value (in this example, it will be the value of break in service CPPR when beginning), and 93, issue an interruption reset condition with IOID in the IOC specified in the XISR data that write and interrupt source to interrupting the Route Selection layer, and 94 to IOC issue, (value of the XISR when interrupting beginning in this example, thus this will reset served interruption just now).When IOC receives that this resets, if 97 hardware still think an interruption wait for (for example, since software service with write XIRR after interruption has appearred again), then 74 again starting interrupt show process.

The XIRR facility externally occurs twice in the interrupt management district.Address BA+4 is designed to use with interrupt inquiry, and address BA+4 is reading or writing the fashionable spinoff that has, and is designed so that hardware to assist software in cueue of interrupt's process and allows interrupt handler software efficiently.Further describe register and their purposes below.Processor interrupts processor

Preservation is according to the priority of the override request of the formation of the software administration of this processor in the override request register (MFRR).When writing the value of a non-0xff, the power of MFRR and other external interrupt competition interrupt handler.When the priority of MFRR is priority the highest in all interrupt request of this processor of guiding, just a suitable value is loaded among the XISR and (sees the XISR register declaration), and send a look-at-me to this processor.When processor reads XIRR at the BA+4 place, the value among the MFRR will be loaded among the CPPR by hardware.Software readable is returned MFRR and is confirmed that having carried out MFRR writes.

In the processing procedure of interrupting between a processor, software withdraws from highest priority request from the software queue related with MFRR, and with traditional queue management technology known in the present technique time preferential priority of asking is loaded among the MFRR.Omnidistance formation

In the MP system, the system storage space comprises one or more omnidistance formation MFRR, software with them with any one processor that interrupts between processor sending in a certain server zone.The Route Selection layer determines to receive requesting processor according to own algorithm and the value that is loaded among the XISR is to indicate the IOID of omnidistance formation except interrupting, and the work of the work of omnidistance formation MFRR and the MFRR of above-described each processor is just the same.This route selection algorithm can similarly be optimized according to the starting point of system design.For example, a system according to cost optimization can will be routed to a processor at random for fear of the priority Compare Logic is set, and is used to realize that a high performance system then attempts will be routed to the processor that moves forever on lowest priority.External interrupt vector register (XIVR)

The external interrupt that each IOC30 is supported for each it comprises an external interrupt vector register 70.Position in each register is defined as follows:

The position	Explanation
		0-15	Standby: these are standby and should be made as 0 value by software according to the storage instruction.These positions are returned as 0 value according to loading instruction by hardware, and (software annotation: as long as this field remains " standby ", these positions just only guarantee to be 0; If defined these future again, then software can be got certain value except that 0.)
16-23	ISR number: it determines that interruption will be interrupted Route Selection hardware and where point to.If the processor in this value representation system then interrupts leading this processor.If it does not represent par-ticular processor, then interrupting the Route Selection layer can select route according to its display algorithm.
		24-31	Interrupt priority level: this fields specify should be distributed to feed to cry and interrupted which kind of priority.

Table 2:XIVR register declaration

These register-bit are in the IOC address space, and the address of these registers is by the definition of the particular design of IOC.External interrupt request register (XIRR)

XIRR is one 4 a byte register at address BA+0 and BA+4.Issue a load instructions, cause the content of CPPR and XISR being delivered to processor and having no side effect the XIRR on the BA+0 of address.This is that design comes to inquire about external interrupt for software.Issue a load instructions to the XIRR on the BA+4 of address and have following minimum spinoff: return before the content of XIRR: * is 86 of Fig. 6, interrupts the Route Selection layer and makes the look-at-me 72 at the processor of accessed BA just is not energized.Only passing through after time enough guarantees that the look-at-me that does not activate has been propagated internal interrupt logic by processor, just the content with XIRR returns to requesting processor.To deliver to after the processor from the data of XIRR:

* the content of CPPR is arranged to send among the XISR priority of interrupt of signal

(if XISR is 0, does not then change the CPPR field).

* XISR is reset to 0 * 000000.Have the later of higher priority

Interrupt request will cause sending a look-at-me and provide in XIRR.

When system software begins to handle an interruption, the processor disabled interrupt---mask any later external interrupt.In the Interrupt Process sequence, software must allow to enable the interruption of interruption to allow to provide later.Must be noted that the content of guaranteeing before allowing to enable interruption the XIRR at BA+4 place returns to processor, this be for fear of with the once race of the interruption of interrupting the transmission end signal in the Route Selection layer.Once race like this can produce the consequence that can't expect.In the face of the speculative instruction of potential processor is carried out, a kind of method of guaranteeing that data have been returned is to add XIRR Value Data dependence in the code of the code front that allows to enable interruption.Receive the processor register of XIRR value and itself comparing, utilizing this result relatively, is carrying out " if equate then shift " (branch-if-equal) instruction, the storage unit that the destination address that shifts is then instructed for next bar.

When loading XIRR, be provided with like this CPPR have from one of software issue to time of the load instructions of XIRR up to it with one new value issue an effect of refusing the external interrupt of all lower or equal prioritys in to the time till the storage instruction of CPPR.

Storage instruction at an XIRR of BA+0 place issue is undefined (data is out in the cold).Storage to the XIRR on the BA+4 of address has minimum spinoff, and with 4 bytes store different effects is arranged for a byte.When storage instruction is a bytes store, then be storage (seeing CP PR register declaration) to CPPR.When with 4 byte lengths issues during, just an interruption reset condition is delivered to and followed the indicated interrupt source of the data of the storage instruction of XIRR (be not when delivering to storage among the XISR indicated interrupt source) to the storage instruction of XIRR.Following the data to the storage instruction of XISR is (and will can not obtain these data when reading with a load instructions subsequently) that do not write XISR.Otherwise it is to be used to indicate interrupt source is reset to (then is to reset to IOC for reaching omnidistance formation interruption interruption in addition between processor) of interrupting on the Route Selection layer.Article one, allow interrupt source to provide to the issue of the storage instruction of the XISR on this address by the interruption subsequently on the indicated level of the data of following this storage instruction.For one 4 bytes store instruction, byte 0 is stored among the CPPR, but system software is guaranteed this CPPR storage and is compared with the CPPR value of front and have priority lower or that equate, because do not need hardware to handle double reset (once be used for the CPPR value is changed to higher or equal priority, once be used to write XISR) for this situation.

If interrupt Route Selection layer hardware CPPR from higher when lower priority changes the decision refusal interrupt, then to one time 4 bytes store of XIRR the time, interruption Route Selection layer can carry out one of following two things:

1. send twice refusal (once be used for CPPR and change, once be used for XISR and write) to interrupt source

2. send and be used for the refusal that XISR writes and (utilize writing of CPPR must have priority this fact lower than the CPPR value of front; Be added in a requirement on the software).

Have potentially in the various system of different processor for interrupt mechanism as described herein can be used in, interrupt the constraint condition that the Route Selection layer must guarantee to satisfy a kind of all look-at-mes of specific processor.For example, if processor is the inner lock storage look-at-me not, if and in the interruption display cycle of processor, make look-at-me not activate just can not to guarantee normal operation, then interrupting the Route Selection layer must latch look-at-me in the outside, with reading XISR rather than coming reset latch as the result of interrupting refusal.

When interrupt handling routine finished, the XIRR that the value that reads when beginning with interrupt handling routine writes on the BA+4 had following combined effect: issue an explicit End of Interrupt to IOC, and the operator precedence level of processor is turned back to the preceding value of its interruption.

When software was being inquired about interruption, after an interruption was adopted in the software decision, software must notify this interruption of hardware just to be adopted by issuing a load instructions to the XIRR on the BA+4.Then, software must compare XISR and it to confirm that hardware does not change XISR between load instructions in the value that reads on the BA+0.Current processor priority register (CPPR)

This register is one one a byte register, and is used for depositing the current priority of the processor related with it.This register is on address BA+0 and BA+4.Issuing a byte load instruction to CPPR (BA+0 or BA+4) is free from side effects.CPPR is a field in the XIRR register.Each processor has its oneself CPPR.When processor changed state, software can be stored in the processing priority of this processor among the CPPR.Interrupt Route Selection layer refusal to all of a processor than the interruption on the low priority of CPPR priority.Thereby, keep CPPR to have current priority and can prevent that the external interrupt interruption has a process of higher or equal priority.

CPPR is a field among the XIRR, and a part that can be used as XIRR reads or writes.When changing the content of CPPR, interrupt the Route Selection layer and only guarantee that look-at-me with higher priority sends to this processor and reaches and provide in XIRR.This finishes with a hardware comparator.If the interrupt priority level of coming in is less than or equal to current CPPR, then should interrupt refusing back interrupt source.If to the change direction of priority after any storage of CPPR is towards a lower priority, then the hardware highest priority interrupt that recomputates (may by interrupt refusal) and will provide is desirable, if and be the priority higher or more equal than the interruption of any queuing to the storage of CPPR, it is enforceable then recomputating.When owing to the once storage of CPPR removed one when interrupting from XIRR, if the interruption (being higher than new CPPR value) that does not have a higher priority XISR medium to be replaced it, then interrupt viewing hardware XISR value of being set to 0 (minimum ground, with the CPPR storage), the interruption that expression is not being waited for, and reduction is to the interrupt request line of processor.External interrupt source-register (XISR)

This register is one three byte register and the address that comprises interrupt source.Each processor has its oneself XISR.This register is on address BA+1 and BA+5.Yet for the purpose of separability, this register must come access as the part of XIRR.Issue a load instructions, cause the content of XISR to return to processor and have no side effect the XIRR on the BA+0 of address.This is designed for software inquiry external interrupt.Issue the load instructions to the XIRR on the BA+4 of address and have following spinoff: after the content with XIRR returned to processor, (atomically) reset to 0 * 000000 with XISR atomically.Then, the subsequent interrupt request with higher priority will cause sending a look-at-me and provide in XIRR.

Described in following table 3, some value among the XISR has special implication.

Value 0 * 000,000 0 * 000,001 0 * 000002 is until (but not comprising) first IOID value

Implication resets: this value indication does not have current external interrupt waiting for.XISR with this value as spinoff from the loading of the XISR on the unit B A+4.Early stage outage warning (EPOW): this value indication has an EPOW waiting for.Interrupt between processor (IP): interrupt in wait (definition of face MFR R as follows) between processor of these value representations.Each MFRR assign a value.In a MP system, it is 0 * 000002 MFRR that each processor has its XISR value.System configuration software must be arranged so that first IOID in the system that value among the XISR that loads minimum IOID is greater than the IOID value of the previous definition of maximum.

Table 3:XISR particular value queuing interrupt request register (QIRR)

The queuing interrupt request register be one 4 byte register, first byte is override request register (MFRR), and if be provided with remaining 3 low byte, then they are ISSR.Software can be write a single byte MFRR or whole 4 bytes.Override request register (MFRR)

This is one one a byte register.The content of this register is subjected to system software controls, and the prepreerence IP interrupt priority level in (IP) interruption queue 42,43 between a processor of indication processor related with this specific MFRR or server.If the MFRR value of being set to 0xff of a processor does not then have item in the IP of this processor interruption queue 42,43, and hardware does not send an IP look-at-me to this processor yet.When putting into some things in the IP formation 42,43 of system software a processing, it is arranged to this register prepreerence priority in the IP formation simultaneously.When this register is not value 0xff, interrupt the Route Selection layer and just it is handled as another interrupt request, the processor of competing by XIRR shows.When the value among the MFRR for all interrupt request of pointing to this processor in during prepreerence value, just a suitable value is placed on and (sees the XISR explanation) among the XISR and to look-at-me of processor transmission.The same with all other interrupt sources, and if only if has refused that this interruption or software have been issued End of Interrupt and as yet not during the reset interrupt condition, just can resubmit a MFRR and interrupt at the Route Selection layer.Interrupt condition is a MFRR value beyond the 0xff.Therefore,, and interrupt the Route Selection layer and begun to select the route of interrupting, interrupt the Route Selection layer and will can again interrupt request be directed to and interrupt on the display layer owing to once changing after the value among the MFRR in case MFRR has had a non-0xff value.The mode that interruption Route Selection layer is reselected the route of MFRR interrupt request is because an interruption is refused or an interruption reset condition (supposition MFRR is not value 0xff).The value of MFRR can only be changed by the software storage operation.Each processor has a MFRR at least.In a MP system, also have one or more omnidistance MFRR.The MFRR related with the IP interrupt mechanism of a par-ticular processor is positioned on address BA+12, BA+16 or the like.Omnidistance queuing interrupt request register (G_QIRR)

Omnidistance queuing interrupt request register 73 is one 4 byte registers, and first byte is an omnidistance override request register (G_MFRR), and it is a MFRR, and remaining low three byte then is ISSR.Software can be write a single byte G_MFRR, perhaps whole 4 bytes.The start address in the interrupt management district of full-range service device is called its base address (BA).The BA of each full-range service device is different, and sets when setting up.The layout in full-range service device interrupt management district is as follows:

The address	Byte	0	Byte 1	Byte 2	Byte 3	Note
							BA＋12	?G_MFRR	????ISSR			The desired QIRR of MP system
BA＋16	?G_MFRR	????ISSR			Optional 2QIRR
						BA＋20	?G_MFRR	????ISSR			Optional 3QIRR
000	?G_MFRR	????ISSR			Optional nQIRR

Table 4: interrupt management district: interrupt the display layer register when will the look-at-me related sending to a processor, comprise the value that is loaded among the XISR among the ISSR (interrupt source explanation register) with corresponding MFRR.Look-at-me between equipment and the controller sends

Describe abort packet form in the table 5 in detail into the design of IBM Power PC 601 system buss.This system bus is at " Power PC 601 risc microcontroller user manuals ", 1992, in further describe, by reference at this material as a setting.Identical address bit definition can be used to adopt the data processor of other processor similarly.The transmission type position is exclusively used in 601 buses, may change in other bus structure.

Operation	Transmission type	GLB	Address bit 0-2	Address bit 3-11	Address bit 12-15	Address bit 16-12	Address bit 24-31
								Interrupt request	10110	?1	The following optional value B ' 001 '-the first of standby fault value B ' 000 ' interrupts expression B ' 010 '-refusal and interrupts expression	IOID	Interrupt source	Server number	Interrupt priority level
Interruption reset condition	10111	?1	The interruption reset condition B101 ' that the following optional value B100 ' of fault value BO00 ' for subsequent use-store causes to XIRR-by storage is to ' interruption refusal B110 ' that CPPR causes-because the full interruption refusal B111 ' that causes of XISR-because the interruption refusal that the priority of CPPR request causes	IOID	Interrupt source	Server number	The standby x ' 00 ' that is changed to

Table 5 transmission type field is used to identify the type of the transmission on the present address bus, such as an interrupt request or an interruption reset condition.Omnidistance (GBL) position is used to indicate each equipment on the bus monitoring transactions to handle, and always allows to enable that abort packet transmits.Bit line of address is grouped into 4 subclass.Address bit 0-2 is used to provide the further information of the transmission of occurent particular type.Whether for the operation of interrupt request, address bit 0-2 indicates whether this is the first time or the follow-up demonstration of an interruption, thereby and indicate this interruption to be rejected in the past and resubmit.For an interruption reset condition operation, the reason of address bit 0-2 indication interruption reset condition.The route of IOC in address bit 3-11 appointing system address or the request.Among the address bit 12-15 sign IOC nearly in 16 sources which this request is proposed.Address bit 16-23 is a server number, is directly to fetch from the XIVR register of interrupt source.Each server number compares the server position for this particular server writes a server in the configuration register when setting up in system.Address bit 24-31 in the request grouping comprises interrupt priority level, and it is also from the XIVR of interrupt source.The currency of these priority bit and CPPR is compared to judge whether accept an interrupt request.The address bit 24-31 in the grouping of resetting be keep and contain X ' 00 '.

Fig. 7 and 8 describes the bus signals transmission that data processing is interrupted subsystem.At first referring to Fig. 7, when an IOC had an interrupt request, this IOC came to central bus arbiter request address bus by activating its bus request signal BR100.Moderator is authorized (BG) signal 102 and is authorized bus to this IOC by activating corresponding bus.Then, this IOC sends an interrupt request grouping on address bus.This is undertaken by following manner: will transmit beginning (TS) 104, bus address 110 and transmission type (TT) 108 lines and be driven into the interruption that certain value (as defined in Table 5) is notified some interrupt source of interruptable controller existence and priority.In addition, IOC is driven into low level with busy (ABB) 106 of Signal Message Address bus and indicates and use address bus.Interruptable controller is handled these information and is sent a look-at-me to processor.In multiprocessing system, interruptable controller can be directed to interrupting information a suitable processor, as mentioned above.Bus arbiter is driven into low level with Address Confirmation signal (AACK) and indicates the address portion of having finished issued transaction.

Referring to Fig. 8, when processor has been finished Interrupt Process, it just the wake-up interrupts controller go to send one and reset and be grouped into IOC and (store in the XIRR register, as discussed above).Then, interruptable controller comes to central bus arbiter request address bus by activating its bus request signal BR100.Moderator is authorized (BG) signal 102 and is authorized bus to IOC by activating corresponding bus, and this IOC sends an interruption reset condition and divides into groups on address bus.It carries out in the following manner: notify IOC to serve this interruption by TS104, bus address 110 and TT108 line are driven into certain value (as defined in Table 5).In addition, IOC is urged to low level with busy (ABB) 106 of Signal Message Address bus and indicates and use address bus.Bus arbiter is urged to low level with Address Confirmation signal (AACK) and indicates the address portion of having finished issued transaction.

One takies the phase and comprises the data that transmit between an address and 0 and 8 cycle.Because each address has the data in 4 cycles to transmit usually, so the address bus of data bus uses heavylier.Utilize address bus to send interrupting information, just might utilize one to use not enough resource (address bus), and not utilize busy data bus.Utilize another advantage of address bus to be: in a preferred embodiment, current all IOC on system bus use whole address bus.Yet IOC but and not all uses whole data bus.The abort packet utilization that transmits on address bus has existed in the address wire in the system, does not need to increase pin and lead.This is with to have method now different, and they use some special interrupt lines.Because the I/O of memory mapped is the I/O method of using the most widely, so be used as sending the method for abort packet with it.As prevailing I/O method and used conventional art known in the present technique, on the system bus all chips have possessed the logic of carrying out the I/O of memory mapped.

In a preferred embodiment, abort packet definition allows from each 16 interrupt sources among 512 IOC.One has 256 interrupt priority levels.Each system can have 256 ISR.This makes the grouping definition be applicable in the machine of broad range.In interrupt request grouping and interruption reset condition grouping, all leave and keep the position, but their supply and demand to transmits system's use of more information in abort packet.Thereby this grouping definition can be following system provides extensibility.

Hardwired interrupt system early only provides few direct information about an interruption.The bus group technology provides interrupt source, IOID, priority and server info fully in the same time and place.Except system flexibility, this makes that the system break debugging is more easy.Information can be placed on what notify among the address bit 0-2 of reservation of interruption reset condition grouping that IOC sending is any interruption reset condition.

In the abort packet definition, allow 256 possible ISR.This means that nearly 256 processors can be accepted interruption in system.This grouping definition makes interruption can easily be directed to different processors.In addition, can reach 256 possible ISR, allow to have in the system nearly 256 interruptable controllers for each system definition.Each interruptable controller can be served a single processor, and perhaps batch server can be served each processor, as previously described.

Owing to interrupt transmitting on address bus, they interrupt lining up sequence with other system operation with other.This is helpful in debugging, because it more can observe and still less asynchronous with system interruption on system-level.For example, can the surveillance bus detect the interruption that is provided on the address bus.Because address packets is that (promptly not overlapping or provide concomitantly) of sequence is provided, this just is easier to determine to call which kind of operation or can cause which kind of follow-up operation.

Since interrupting information be in each field that is defined in the abort packet rather than hard wire on flat board, this interrupt system is very programmable.Utilize this packet configuration, interrupt priority level, server number, interrupt source and I/O controller ID are programmable.Therefore, this interrupt structure is more more flexible than hard wire system.

Though show with reference to its special embodiment and described the present invention, person skilled in the art person will be understood that can be under the condition that does not break away from spirit of the present invention and scope, make therein above-mentioned and other reach change on the details in form.

Claims (33)

1. the system of a plurality of interruptions of a data disposal system that is used for keeping having a plurality of processors is characterized in that comprehensively comprising:

Be used for device with a specific processor of described at least one guiding of described a plurality of interruptions; And

Be used for described at least one determined that the interruption of route arranges the into device of the formation of described par-ticular processor.

2. the system of claim 1 is characterized in that comprising: if describedly be used to select the device of route to receive an interruption more preferably, just refuse the device of an interruption.

3. the system of claim 1, it is characterized in that described at least one selected the interruption of route to line up for an optimum processor visit.

5. the system of claim 1 is characterized in that comprising the device that is used for generating from a plurality of interrupt sources described a plurality of interruptions.

6. system that is used for handling a plurality of interruptions of a data disposal system with a plurality of processors is characterized in that comprehensively comprising:

Be used for device with a specific processor of described at least one interrupt oriented;

Be used to line up described at least one selected the device of the interruption of route;

Be used for device with the interruption of described specific described at least one queuing of processor access; And

Be used for described at least one the accessed interrupting device of described specific processor service.

7. the system of claim 6 is characterized in that described at least one accessed interruption is to use a single interrupt source identifier to offer described specific processor.

8. the system of claim 6 is characterized in that comprising: if when the described device that is used to select route receives more preferably an interruption, be used to refuse an interrupting device.

9. the system of claim 6 is characterized in that comprising the device that is used to prevent pirority inversion.

10. the system of claim 6, it is characterized in that described at least one selected the interruption of route to line up for an optimum processor visit.

11. the system of claim 6 is characterized in that comprising the device that is used for generating from a plurality of interrupt sources described a plurality of interruptions.

12. a system that is used for handling a plurality of interruptions of a multi-processor data process system is characterized in that comprehensively comprising:

One interrupts the Route Selection layer, is used to accept at least one and interrupts, and described Route Selection layer has the device that is used for a specific processor of described at least one interrupt oriented; And

One interrupts display layer, have be used to accept from described interruption Route Selection layer described at least one selected the interrupting device of route, and be used to line up described at least one selected the device of the interruption of route.

13. the system of claim 12 is characterized in that described interruption Route Selection layer also comprises the device that is used to refuse an interruption.

14. the system of claim 12, it is characterized in that described at least one selected the interruption of route to line up to become for an optimum processor visit.

15. the system of claim 12 is characterized in that the interruption of described queuing comprises a single interrupt source identifier.

16. the method for a plurality of interruptions of a data disposal system that is used for keeping having a plurality of processors is characterized in that comprising the steps:

With specific processor of described at least one interrupt oriented; And

With described at least one selected the cueue of interrupt of route to described specific processor.

17. the method for claim 16 is characterized in that comprising the step that generates described a plurality of interruptions from a plurality of interrupt sources.

18. the method for claim 16 is characterized in that comprising the steps: just refusing an interruption when described data handling system receives more preferably an interruption subsequently.

19. the method for claim 16, it is characterized in that described at least one selected the interruption of route to line up to become for an optimum processor visit.

20. a method that is used for handling a plurality of interruptions of a data disposal system with a plurality of processors is characterized in that comprising the steps:

With specific processor of described at least one interrupt oriented;

Line up described at least one selected the interruption of route;

Interruption with described specific described at least one queuing of processor access; And

With described at least one the accessed interruption of described specific processor service.

21. the method for claim 20 is characterized in that described at least one accessed interruption is to offer described specific processor with a single interrupt source identifier.

22. the method for claim 20 is characterized in that comprising the steps: that described data handling system accepts at least one interruption subsequently, and if described at least one interruption subsequently more preferential, then refuse an interruption.

23. the method for claim 20 is characterized in that the interruption of described queuing comprises a single interrupt source identifier.

24. the system of a plurality of interruptions of a data disposal system that is used for keeping having a plurality of processors is characterized in that comprehensively comprising:

Be used for described a plurality of processors are combined into the device of a plurality of logical servers;

Be used for device with a specific logical server of described at least one guiding of described a plurality of interruptions; And

Be used for the device to the described specific logical server with described at least one cueue of interrupt of having selected route.

25. the system of claim 24 is characterized in that described at least one accessed interruption is to offer described specific logical server with a single interrupt source identifier.

26. the system of claim 24 is characterized in that comprising: if describedly be used to select the device of route to receive an interruption more preferably, just refuse the device of an interruption.

27. the system of claim 24 is characterized in that comprising the device that is used to prevent pirority inversion.

28. the system of claim 24, it is characterized in that described at least one to have selected the interruption of route be what to be lined up for an optimum processor visit in the described logical server.

29. the system of claim 24 is characterized in that comprising the device that is used for generating from a plurality of interrupt sources described a plurality of interruptions.

30. the method for a plurality of interruptions of a data disposal system that is used for keeping having a plurality of processors is characterized in that comprising the steps:

Described a plurality of processors are combined into a plurality of logical servers;

With the specific logical server of described at least one guiding in described a plurality of interruptions; And

With described at least one selected the cueue of interrupt of route to described specific logical server.

31. the method for claim 30 is characterized in that comprising: if receive an interruption more preferably subsequently, just refuse the step of an interruption.

32. the method for claim 30, it is characterized in that described at least one selected the queuing of the interruption of route to become for an optimum processor visit in the described logical server.

33. a method that is used for handling a plurality of interruptions of a data disposal system with a plurality of processors is characterized in that comprising the steps:

Described a plurality of processors are combined into a plurality of logical servers;

With specific logical server of described at least one interrupt oriented;

Line up described at least one selected the interruption of route;

Visit the interruption of described at least one queuing with described specific logical server; And

With described at least one the accessed interruption of described specific logical server service.

34. a system that is used for handling a plurality of interruptions of multi-processor data process system is characterized in that comprehensively comprising:

One interrupts the Route Selection layer, is used to accept at least one and interrupts, and described Route Selection layer has the device that is used for described at least one interrupt oriented is comprised a logical server of a plurality of processors; And

One interrupts display layer, have be used to accept from described interruption Route Selection layer described at least one selected the device of the interruption of route, and be used to line up described at least one selected the device of the interruption of route.

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