CN112019175B - Amplifier switch control system and method - Google Patents

Amplifier switch control system and method Download PDF

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Publication number
CN112019175B
CN112019175B CN202010466847.4A CN202010466847A CN112019175B CN 112019175 B CN112019175 B CN 112019175B CN 202010466847 A CN202010466847 A CN 202010466847A CN 112019175 B CN112019175 B CN 112019175B
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China
Prior art keywords
switching rate
predetermined
module
duty cycle
switching
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CN202010466847.4A
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Chinese (zh)
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CN112019175A (en
Inventor
C·德拉诺
D·海涅曼
G·多彻蒂
F·余
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Priority claimed from US16/874,857 external-priority patent/US11496096B2/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention relates to an amplifier switch control system and method. The first module is configured to determine a first duty cycle based on the input samples. The second module is configured to determine a second duty cycle based on the battery voltage and the first duty cycle. The third module is configured to: setting a scalar value based on at least one of a battery current, an amplitude of the input sample, the second duty cycle, and an output voltage; and generating an enable signal at a rate equal to the predetermined rate multiplied by the scalar value. The fourth module is configured to set a third duty cycle based on the second duty cycle and the scalar value. The fifth module is configured to generate a PWM output based on the start signal and the third duty cycle. The sixth module is configured to apply power to a gate of the FET of the voltage converter based on the PWM output.

Description

Amplifier switch control system and method
Cross Reference to Related Applications
The present application claims the benefit of U.S. provisional application No. 62/853,821, filed on 5/29 of 2019. The entire disclosure of the above-mentioned U.S. provisional application is incorporated herein by reference.
Technical Field
The present disclosure relates to amplifiers, and more particularly, to systems and methods for controlling the clock frequency of the switches of an amplifier.
Background
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Various types of electronic circuits use analog signals and digital signals. An analog-to-digital converter (ADC) may implement conversion of an analog signal into a digital signal that may be used by one or more digital components. Digital-to-analog converters (DACs) may enable conversion of digital signals to analog signals that may be used by one or more analog components.
For example, a portable device ("portable audio device") that outputs sound includes a DAC. The DAC receives, for example, a Pulse Density Modulated (PDM) or Pulse Code Modulated (PCM) digital signal. The DAC generates an analog signal based on the digital signal. The amplifier drives one or more speakers of the portable audio device to produce sound based on the analog signal.
Disclosure of Invention
In one feature, an amplifier system includes: a voltage converter comprising at least one of: a buck converter; a boost converter; a sigma-delta modulator module configured to determine a first duty cycle of a Field Effect Transistor (FET) for switching the voltage converter based on an input sample; a duty cycle module configured to determine a second duty cycle for switching the FET of the voltage converter based on a battery voltage and the first duty cycle; a start and clock module configured to: setting a scalar value to one of 1, 2, and 4 based on at least one of a battery current, an amplitude of the input sample, the second duty cycle, and an output voltage of the voltage converter; and generating an enable signal at a rate equal to a predetermined rate multiplied by the scalar value; a FET switching rate module configured to: setting a third duty cycle to the second duty cycle when the scalar value is set to 1; setting the third duty cycle to the second duty cycle divided by 2 when the scalar value is set to 2; setting the third duty cycle to the second duty cycle divided by 4 when the scalar value is set to 4; a Digital Pulse Width Modulation (DPWM) module configured to generate a Pulse Width Modulation (PWM) output for switching a FET of the voltage converter based on the start signal and the third duty cycle; and a gate drive module configured to apply power to a gate terminal of a FET of the voltage converter based on the PWM output.
In further features, the start-up and clock module is configured to set the scalar value to 1 when all of the following are satisfied: the battery current is less than a predetermined current; the amplitude of the input sample is less than a predetermined voltage; and the second duty cycle is less than a predetermined duty cycle.
In further features, the start-up and clock module is configured to set the scalar value to 2 when the battery current is greater than the predetermined current.
In further features, the start-up and clock module is configured to set the scalar value to 4 when the battery current is greater than a second predetermined current, wherein the second predetermined current is greater than the predetermined current.
In further features, the start-up and clock module is configured to transition the scalar value from 2 to 1 when the battery current transitions from greater than a second predetermined current to less than the second predetermined current, wherein the second predetermined current is less than the predetermined current.
In further features, the start-up and clock module is configured to set the scalar value to 2 when the amplitude of the input sample is greater than the predetermined voltage.
In further features, the start-up and clock module is configured to set the scalar value to 4 when the amplitude of the input sample is greater than a second predetermined voltage, wherein the second predetermined voltage is greater than the predetermined voltage.
In further features, the start-up and clock module is configured to transition the scalar value from 2 to 1 when the amplitude of the input sample transitions from greater than a second predetermined voltage to less than the second predetermined voltage, wherein the second predetermined voltage is less than the predetermined voltage.
In further features, the start-up and clock module is configured to set the scalar value to 2 when the second duty cycle is greater than the predetermined duty cycle.
In further features, the start-up and clock module is configured to set the scalar value to 4 when the second duty cycle is greater than a second predetermined duty cycle, wherein the second predetermined duty cycle is greater than the predetermined duty cycle.
In further features, the start-up and clock module is configured to transition the scalar value from 2 to 1 when the second duty cycle transitions from greater than a second predetermined duty cycle to less than the second predetermined duty cycle, wherein the second predetermined duty cycle is less than the predetermined duty cycle.
In further features, the start-up and clock module is configured to set the scalar value based on all of the battery current, the amplitude of the input sample, and the second duty cycle.
In further features, the start-up and clock module is configured to transition the scalar value from 1 to 2 when at least one of: the battery current is greater than a first predetermined current; the amplitude of the input sample is greater than a first predetermined voltage; and the second duty cycle is greater than the first predetermined duty cycle.
In further features, the start-up and clock module is configured to transition the scalar value from 2 to 4 when at least one of: the battery current is greater than a second predetermined current, wherein the second predetermined current is greater than the first predetermined current; the amplitude of the input sample is greater than a second predetermined voltage, wherein the second predetermined voltage is greater than the first predetermined voltage; and the second duty cycle is greater than a second predetermined duty cycle, wherein the second predetermined duty cycle is greater than the first predetermined duty cycle.
In a further feature, the amplifier system includes a speaker and an H-bridge configured to receive an output from the voltage converter and apply power to the speaker.
In further features, the DPWM module is configured to first transition the PWM output from OFF to ON upon generation of the start signal, to maintain the PWM output ON for a period of time corresponding to the third duty cycle after the first transition, and to transition the PWM output from ON to OFF upon elapse of the period of time.
In one feature, an audio amplifier system includes: a speaker; a voltage converter comprising at least one of: a buck converter; a boost converter; an H-bridge configured to receive a power output by the voltage converter and apply power to the speaker; a control module configured to set a switching rate of a Field Effect Transistor (FET) of the voltage converter based on a scalar multiplied by a predetermined rate, and to selectively set the scalar to a value greater than one based on one or more operating parameters; a Digital Pulse Width Modulation (DPWM) module configured to generate a Pulse Width Modulation (PWM) output for switching FETs of the voltage converter based on the switching rate; and a gate drive module configured to apply power to a gate terminal of a FET of the voltage converter based on the PWM output.
In further features, the control module is configured to increase the scalar from one as the battery current increases.
In further features, the control module is configured to increase the scalar from one as the amplitude of the input sample increases.
In further features, the control module is configured to determine a duty cycle of a FET for switching the voltage converter and to increase the scalar from one as the duty cycle increases.
In further features, the control module is configured to decrease the scalar toward one or to one as the battery current decreases.
In further features, the control module is configured to decrease the scalar toward one or to one as the amplitude of the input sample decreases.
In further features, the control module is configured to determine a duty cycle of a FET for switching the voltage converter and decrease the scalar toward one or to one as the duty cycle decreases.
In one feature, an amplifier control method includes: determining a first duty cycle of a Field Effect Transistor (FET) for a switching voltage converter based on an input sample, the voltage converter including at least one of a buck converter and a boost converter; determining a second duty cycle for switching the FET of the voltage converter based on the battery voltage and the first duty cycle; setting a scalar value to one of 1, 2, and 4 based on at least one of a battery current, an amplitude of the input sample, the second duty cycle, and an output voltage of the voltage converter; generating an enable signal at a rate equal to a predetermined rate multiplied by the scalar value; the third duty cycle is set as follows: setting the third duty cycle to the second duty cycle when the scalar value is set to 1; setting the third duty cycle to the second duty cycle divided by 2 when the scalar value is set to 2; and setting the third duty cycle to the second duty cycle divided by 4 when the scalar value is set to 4; generating a Pulse Width Modulation (PWM) output for switching the FET of the voltage converter based on the start signal and the third duty cycle; and applying power to a gate terminal of a FET of the voltage converter based on the PWM output.
In further features, setting the scalar value includes setting the scalar value to 1 when all of the following are satisfied: the battery current is less than a predetermined current; the amplitude of the input sample is less than a predetermined voltage; and the second duty cycle is less than a predetermined duty cycle.
In further features, setting the scalar value includes setting the scalar value to 2 when the battery current is greater than the predetermined current.
In further features, setting the scalar value includes setting the scalar value to 4 when the battery current is greater than a second predetermined current, wherein the second predetermined current is greater than the predetermined current.
In further features, setting the scalar value includes transitioning the scalar value from 2 to 1 when the battery current transitions from greater than a second predetermined current to less than the second predetermined current, wherein the second predetermined current is less than the predetermined current.
In further features, setting the scalar value includes setting the scalar value to 2 when the amplitude of the input sample is greater than the predetermined voltage.
In further features, setting the scalar value includes setting the scalar value to 4 when the amplitude of the input sample is greater than a second predetermined voltage, wherein the second predetermined voltage is greater than the predetermined voltage.
In further features, setting the scalar value includes transitioning the scalar value from 2 to 1 when the amplitude of the input sample transitions from greater than a second predetermined voltage to less than the second predetermined voltage, wherein the second predetermined voltage is less than the predetermined voltage.
In further features, setting the scalar value includes setting the scalar value to 2 when the second duty cycle is greater than the predetermined duty cycle.
In further features, setting the scalar value includes setting the scalar value to 4 when the second duty cycle is greater than a second predetermined duty cycle, wherein the second predetermined duty cycle is greater than the predetermined duty cycle.
In further features, setting the scalar value includes transitioning the scalar value from 2 to 1 when the second duty cycle transitions from greater than a second predetermined duty cycle to less than the second predetermined duty cycle, wherein the second predetermined duty cycle is less than the predetermined duty cycle.
In further features, setting the scalar value includes setting the scalar value based on all of the battery current, the amplitude of the input sample, and the second duty cycle.
In further features, setting the scalar value includes transitioning the scalar value from 1 to 2 when at least one of: the battery current is greater than a first predetermined current; the amplitude of the input sample is greater than a first predetermined voltage; and the second duty cycle is greater than the first predetermined duty cycle.
In further features, setting the scalar value includes transitioning the scalar value from 2 to 4 when at least one of: the battery current is greater than a second predetermined current, wherein the second predetermined current is greater than the first predetermined current; the amplitude of the input sample is greater than a second predetermined voltage, wherein the second predetermined voltage is greater than the first predetermined voltage; and the second duty cycle is greater than a second predetermined duty cycle, wherein the second predetermined duty cycle is greater than the first predetermined duty cycle.
In further features, the amplifier control method further comprises: a power output is applied from the voltage converter to the speaker via the H-bridge.
In further features, generating the PWM output comprises: turning the PWM output from OFF to ON for a first time upon generation of the start signal; holding the PWM output ON for a period of time after the first transition corresponding to the third duty cycle; and turning the PWM output from ON to OFF when the period of time has elapsed.
In one feature, an audio amplifier control method includes: applying a power output to the speaker via the H-bridge by a voltage converter comprising at least one of: a buck converter; a boost converter; setting a switching rate of a Field Effect Transistor (FET) of the voltage converter based on a scalar multiplied by a predetermined rate, and selectively setting the scalar to a value greater than one based on one or more operating parameters; generating a Pulse Width Modulation (PWM) output for switching FETs of the voltage converter based on the switching rate; and applying power to a gate terminal of a FET of the voltage converter based on the PWM output.
In further features, selectively setting the scalar to a value greater than one includes increasing the scalar from one as the battery current increases.
In further features, selectively setting the scalar to a value greater than one includes increasing the scalar from one as the amplitude of the input sample increases.
In further features, the audio amplifier control system further comprises determining a duty cycle of a FET for switching the voltage converter, wherein selectively setting the scalar to a value greater than one comprises increasing the scalar from one as the duty cycle increases.
In further features, the audio amplifier control system further comprises: the scalar is reduced toward one or to one as the battery current decreases.
In further features, the audio amplifier control system further comprises: the scalar is reduced toward or to one as the amplitude of the input samples decreases.
In further features, the audio amplifier control system further comprises: determining a duty cycle of a FET for switching the voltage converter; and decreasing the scalar toward one or to one as the duty cycle decreases.
Further areas of applicability of the present disclosure will become apparent from the detailed description, claims, and drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Drawings
The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
fig. 1 is a high-level functional block diagram of an exemplary audio amplifier 104 (e.g., a portable audio device).
FIG. 2 is a schematic diagram of an example embodiment including a power module.
Fig. 3 is a functional block diagram of an audio amplifier.
FIG. 4 is a functional block diagram of an example implementation of a control module.
Fig. 5 is a functional block diagram of an example implementation of a FET switching rate module.
Fig. 6 is a functional block diagram of an example implementation of a PWM pre-conditioner module.
Fig. 7 is a functional block diagram of an example implementation of a DPWM module.
Fig. 8 is an example graph including inductor current and output voltage.
Fig. 9 is an example graph including inductor current and output voltage.
Fig. 10 is an example graph including counter values, a start signal, and different PWM output signals generated based on differently divided second duty cycles.
Fig. 11 is an example plot of inductor current including switching frequency (Fsw), states of the first FET through the fourth FET, and boost mode operation of the buck-boost converter.
Fig. 12 is an example plot of inductor current including switching frequency (Fsw), states of the first FET through the fourth FET, and buck mode operation of the buck-boost converter.
FIG. 13 is an example graph including a selection signal, an inductor current, an output voltage, and a duty cycle.
Fig. 14 is an example graph including a counter value, a state of an enable signal, a state of a select signal, a PWM output signal, a second duty cycle signal, and a duty cycle signal.
FIG. 15 is a flowchart including an example method of controlling switching of FETs of a buck-boost converter.
FIG. 16 is a flow chart including an example method of controlling switching of FETs of a buck-boost converter.
In the drawings, reference numbers may be repeated to indicate similar and/or identical elements.
Detailed Description
Examples of amplifiers include audio amplifiers, piezoelectric drivers, motor drivers, and other types of switching amplifiers. Some amplifiers apply power from a battery or a Direct Current (DC) to DC converter to one or more speakers or another type of load. Some amplifiers operate in a buck mode, wherein the amplifier receives a first voltage and outputs a second voltage that is less than the first voltage. The other amplifiers operate in a boost mode, wherein the amplifier receives a first voltage and outputs a second voltage that is greater than the first voltage.
Some amplifiers operate in boost mode at some times and in buck mode at other times. More specifically, some amplifiers receive a first voltage, in some cases output a second voltage that is less than the first voltage (and operate in a buck mode), and in other cases output a third voltage that is greater than the first voltage (and operate in a boost mode). This type of amplifier may be referred to as a buck-boost amplifier.
According to the present application, the control module selectively scales the switching frequency of the Field Effect Transistor (FET) of the converter based on one or more operating parameters, such as battery current, duty cycle, and amplitude of the input signal. The converter may be a buck converter, a boost converter, or a combined buck-boost converter. The control module also scales a duty cycle to be applied to the FET based on the scaling of the switching frequency. Scaling reduces peak-to-peak current ripple and increases the performance (e.g., output power) of the converter.
Fig. 1 is a high-level functional block diagram of an exemplary audio amplifier 104 (e.g., a portable audio device). The audio amplifier 104 receives an audio input signal (audio signal). The audio input signal may be an analog signal or a digital signal. The audio input signal may be generated, for example, based on an audio file stored in a computer readable medium or received from a transceiver. The audio amplifier 104 applies power from the battery 112 to one or more speakers (such as speaker 108) based on the audio input signal to output sound corresponding to the audio input signal. The audio amplifier 104 includes a sigma-delta (ΣΔ) modulator module 116, a Field Effect Transistor (FET) switching rate module 120, a Digital Pulse Width Modulation (DPWM) and gate drive module 124, and a power module 128.
FIG. 2 is a schematic diagram of an example embodiment including a power module 128. The power module includes a buck-boost converter 204 and an H-bridge 208. Buck-boost converter 204 includes a first FET M1, a second FET M2, a third FET M3, a fourth FET M4, an inductor L, and a capacitor C. The first FET M1 and the second FET M2 (together with the inductor L and the capacitor C) form a buck converter. The third FET M3 and the fourth FET M4 (together with the inductor L and the capacitor C) form a boost converter. The ON/OFF times of the first, second, third and fourth FETs M1, M2, M3 and M4 determine the voltage at node N4.
The H-bridge 208 includes a fifth FET M5, a sixth FET M6, a seventh FET M7, and an eighth FET M8. The ON/OFF times of the fifth FET M5, sixth FET M6, seventh FET M7, and eighth FET M8 control the application of power from the buck-boost converter 204 (node N4) to the speaker 108 (via nodes N5 and N6).
The buck-boost converter shown in fig. 2 is a pulsed voltage converter. When the converter is in buck mode, the first FET M1 and the second FET M2 are switched. The third FET 3 and the fourth FET M4 are switched when the converter is in boost mode.
Fig. 3 is a functional block diagram including an audio amplifier 104. In examples where the audio input signal is a digital signal, the digital audio interface 304 may receive the input audio signal. A digital-to-analog (D/a) converter 308 converts the (digital) input audio signal into an analog signal and outputs the analog signal to an integrator comparator 312. In examples where the audio input signal is an analog signal, the D/a converter 308 may be omitted and an analog audio interface may be used in place of the digital audio interface 304.
Integrator comparator 312 generates an analog error signal based on the difference between the analog signal (at nodes N5 and N6) and the (analog) output to speaker 108. Analog-to-digital (a/D) converter 316 converts the analog error signal to a digitized error signal and outputs the error signal to control module 320. The a/D converter 324 converts the analog signal output by the D/a converter 308 into a digitized feedforward signal and outputs the feedforward signal to the control module 320.
The a/D converter 328 converts the voltage of the battery 112 (at node N1) to a digitized battery voltage signal (VBat) and outputs the battery voltage signal to the control module 320. The a/D converter 332 converts the current of the battery 112 (at node N1) to a digitized battery current signal (IBat) and outputs the battery current signal to the control module 320. The control module 320 generates duty cycle signals from the buck-boost converter 204 and the H-bridge 208 based on the error signal, the feed forward signal, the battery voltage signal, and the battery current signal.
A Digital Pulse Width Modulation (DPWM) module 336 converts the duty cycle signal for buck-boost converter 204 into Pulse Width Modulation (PWM) signals for the first FET M1, the second FET M2, the third FET M3, and the fourth FET M4 of switching buck-boost converter 204. The DPWM clock 340 generates a clock signal for controlling the PWM signal. The DPWM clock 340 generates pulses in the clock signal every predetermined period. The gate driving module 344 generates a gate driving signal according to the PWM signal and applies the gate driving signal to the first, second, third and fourth FETs M1, M2, M3 and M4 of the buck-boost converter 204.
The DPWM module 336 also converts the duty cycle signal of the H-bridge 208 into PWM signals for the fifth FET M5, sixth FET M6, seventh FET M7, and eighth FET M8 of the switching H-bridge 208. The clock signal is also used to control the PWM signal of the H-bridge 208. The gate driving module 348 generates a gate driving signal according to the PWM signal and applies the gate driving signal to the fifth FET M5, the sixth FET M6, the seventh FET tm7, and the eighth FET M8 of the H-bridge 208.
Fig. 4 is a functional block diagram of an example implementation of the control module 320. The control module 320 includes a sigma-delta (ΣΔ) modulator module 116, a FET switching rate module 120, a duty cycle module 404, and a PWM pre-regulator module 408.
The sigma-delta modulator module 116 determines a first duty cycle signal of the buck-boost converter 204 based on the error signal and the feed forward signal. The sigma-delta modulator module 116 may determine the first duty cycle signal, for example, using one of a look-up table and an equation that correlates the error value and the feedforward value with the first duty cycle value. The first duty cycle signal is not scaled to account for the battery voltage.
The sigma-delta modulator module 116 also determines the duty cycle signal of the H-bridge 208 based on the error signal and the feedforward signal. The sigma-delta modulator module 116 may determine the duty cycle signal of the H-bridge, for example, using one of a look-up table and an equation that correlates error values and feedforward values with duty cycle values.
The duty cycle module 404 determines a second duty cycle signal based on the first duty cycle signal and the battery voltage signal. The duty cycle module 404 may determine the second duty cycle signal, for example, using one of a look-up table and an equation that correlates the first duty cycle value and the battery voltage value to the duty cycle value. The duty cycle module 404 may set the second duty cycle signal to be greater than the first duty cycle signal, for example, when the battery voltage decreases below a predetermined voltage. The duty cycle module 404 may set the second duty cycle signal to be less than the first duty cycle signal when the battery voltage increases above a predetermined voltage. The duty cycle module 404 scales the first duty cycle signal based on the battery voltage to generate the second duty cycle signal.
The FET switching rate module 120 selectively generates an enable signal. The DPWM module 336 starts and resets the counter value each time a start signal is generated. The FET switching rate module 120 multiplies the scalar by a predetermined rate (corresponding to a predetermined frequency) to generate an enable signal. The scalar is greater than or equal to 1. The FET switching rate module 120 determines a scalar based on the second duty cycle signal, the feed forward signal, and the battery current signal.
Fig. 5 is a functional block diagram of an example embodiment including FET switching rate module 120. The first comparison module 504 compares the second duty cycle signal to a first predetermined duty cycle (program threshold 1b, on) and compares the second duty cycle signal to a second predetermined duty cycle (program threshold 1b, off). The first comparison module 504 sets a first comparison signal (on1_b) based On the comparison result. The first predetermined duty cycle is greater than the second predetermined duty cycle. The first comparison module 504 may set the first comparison signal to the first state when the second duty cycle signal is greater than the first predetermined duty cycle. The first comparison module 504 then maintains the first comparison signal in the first state until the second duty cycle signal becomes less than the second predetermined duty cycle. The first comparison module 504 transitions the first comparison signal from the first state to the second state when the second duty cycle signal becomes less than the second predetermined duty cycle. The first comparison module 504 then maintains the first comparison signal in the second state until the second duty cycle signal becomes greater than the first predetermined duty cycle.
The second comparison module 508 compares the second duty cycle signal with a third predetermined duty cycle (program threshold 1a, on) and compares the second duty cycle signal with a fourth predetermined duty cycle (program threshold 1a, off). The second comparison module 508 sets a second comparison signal (on1_a) based On the comparison result. The third predetermined duty cycle is greater than the fourth predetermined duty cycle, and the fourth predetermined duty cycle is greater than the second predetermined duty cycle. The second comparison module 508 may set the second comparison signal to the first state when the second duty cycle signal is greater than the third predetermined duty cycle. The second comparison module 508 then maintains the second comparison signal in the first state until the second duty cycle signal becomes less than the fourth predetermined duty cycle. The second comparison module 508 transitions the second comparison signal from the first state to the second state when the second duty cycle signal becomes less than the fourth predetermined duty cycle. The second comparison module 508 then maintains the second comparison signal in the second state until the second duty cycle signal becomes greater than the third predetermined duty cycle.
The first to fourth predetermined duty cycles may be programmable and may be accessed through an interface such as an I2C (inter-integrated circuit) interface or another suitable type of interface.
The third comparison module 512 compares the feedforward signal with a first predetermined voltage (program threshold 2b, on) and compares the feedforward signal with a second predetermined voltage (program threshold 2b, off). The third comparison module 512 sets a third comparison signal (on2_b) based On the comparison result. The first predetermined voltage is greater than the second predetermined voltage. The third comparison module 512 may set the third comparison signal to the first state when the feedforward signal is greater than the first predetermined voltage. The third comparison module 512 then maintains the third comparison signal in the first state until the feedforward signal becomes less than the second predetermined voltage. The third comparison module 512 transitions the third comparison signal from the first state to the second state when the feedforward signal becomes less than the second predetermined voltage. The third comparison module 512 then maintains the third comparison signal in the second state until the feedforward signal becomes greater than the first predetermined voltage.
The fourth comparison module 516 compares the feedforward signal with a third predetermined voltage (program threshold 2a, on) and compares the feedforward signal with a fourth predetermined voltage (program threshold 2a, off). The fourth comparison module 516 sets a fourth comparison signal (on2_a) based On the comparison result. The third predetermined voltage is greater than the fourth predetermined voltage, and the fourth predetermined voltage is greater than the second predetermined voltage. The fourth comparison module 516 may set the fourth comparison signal to the first state when the feedforward signal is greater than a third predetermined voltage. The fourth comparison module 516 then maintains the fourth comparison signal in the first state until the feedforward signal becomes less than the fourth predetermined voltage. The fourth comparison module 516 transitions the fourth comparison signal from the first state to the second state when the feedforward signal becomes less than the fourth predetermined voltage. The fourth comparison module 516 then maintains the fourth comparison signal in the second state until the feedforward signal becomes greater than the third predetermined voltage.
The first to fourth predetermined voltages may be programmable and may be accessed through an interface such as an I2C interface or another suitable type of interface.
The fifth comparison module 520 compares the battery current signal to a first predetermined current (program threshold 3b, on) and compares the battery current signal to a second predetermined current (program threshold 3b, off). The fifth comparison module 520 sets a fifth comparison signal (on3_b) based On the comparison result. The first predetermined current is greater than the second predetermined current. The fifth comparison module 520 may set the fifth comparison signal to the first state when the battery current signal is greater than the first predetermined current. The fifth comparison module 520 then maintains the fifth comparison signal in the first state until the battery current signal becomes less than the second predetermined current. The fifth comparison module 520 transitions the fifth comparison signal from the first state to the second state when the battery current signal becomes less than the second predetermined current. The fifth comparison module 520 then maintains the fifth comparison signal in the second state until the battery current signal becomes greater than the first predetermined current.
The sixth comparison module 524 compares the battery current signal to a third predetermined current (program threshold 3a, on) and compares the battery current signal to a fourth predetermined current (program threshold 3a, off). The sixth comparison module 524 sets a sixth comparison signal (on3_a) based On the comparison result. The third predetermined current is greater than the fourth predetermined current, and the fourth predetermined current is greater than the second predetermined current. The sixth comparison module 524 may set the sixth comparison signal to the first state when the battery current signal is greater than the third predetermined current. The sixth comparison module 524 then maintains the sixth comparison signal in the first state until the battery current signal becomes less than the fourth predetermined voltage. The sixth comparison module 524 transitions the sixth comparison signal from the first state to the second state when the battery current signal becomes less than the fourth predetermined current. The sixth comparison module 524 then maintains the sixth comparison signal in the second state until the battery current signal becomes greater than the third predetermined current.
The first through fourth predetermined currents may be programmable and may be accessed through an interface such as an I2C interface or another suitable type of interface.
Although examples of duty cycle, battery current, and feed forward voltage are discussed, one or more other parameters may additionally or alternatively be used. For example, the output voltages at nodes N5 and N6 may be used. As discussed above, the battery current may be instantaneous, or average (e.g., root mean square, RMS).
The start and clock module 528 determines the scalar based on the first comparison signal, the second comparison signal, the third comparison signal, the fourth comparison signal, the fifth comparison signal, and the sixth comparison signal. For example, the start and clock module 528 may set the scalar to 1 when the first comparison signal, the second comparison signal, the third comparison signal, the fourth comparison signal, the fifth comparison signal, and the sixth comparison signal are all in the second state. The start and clock module 528 may set the scalar to 2 when both: (a) At least one of the first comparison signal, the third comparison signal, and the fifth comparison signal is in a first state; and (b) the second comparison signal, the fourth comparison signal, and the sixth comparison signal are all in the second state. The start and clock module 528 may set the scalar to 4 when at least one of the following is satisfied: (a) Both the first comparison signal and the second comparison signal are in a first state; (b) Both the third comparison signal and the fourth comparison signal are in the first state; and (c) both the fifth comparison signal and the sixth comparison signal are in the first state. The enable and clock module 528 generates the enable signal at a rate equal to the predetermined rate multiplied by the scalar. Although examples are provided with scalar 1, 2, or 4, other values may be used. A scalar may be an integer greater than or equal to 1 or a real number.
The start-up and clock module 528 also sets the select signal (Sel Clk Max) based on the first, second, third, fourth, fifth, and sixth comparison signals. For example, the start and clock module 528 may set the select signal to the first state when the first, second, third, fourth, fifth, and sixth comparison signals are all in the second state. The start and clock module 528 may set the select signal to the second state when both: (a) At least one of the first comparison signal, the third comparison signal, and the fifth comparison signal is in a first state; and (b) the second comparison signal, the fourth comparison signal, and the sixth comparison signal are all in the second state. The start and clock module 528 may set the select signal to the third state when at least one of the following is satisfied: (a) Both the first comparison signal and the second comparison signal are in a first state; (b) Both the third comparison signal and the fourth comparison signal are in the first state; and (c) both the fifth comparison signal and the sixth comparison signal are in the first state.
Referring again to fig. 4, based on the select signal (Sel Clk Max), the PWM pre-regulator module 408 sets the duty cycle signal equal to the second duty cycle signal, the second duty cycle signal divided by 2, or the second duty cycle signal divided by 4.
Fig. 6 is a functional block diagram of an example embodiment including a PWM pre-regulator module 408. The multiplexer (Mux) 604 may comprise a three-input-one-output multiplexer. The multiplexer 604 may receive the second duty cycle signal at a first input, the second duty cycle divided by 2 at a second input, and the second duty cycle divided by 4 at a third input. The first shift register (SHR 1) 608 may shift the second duty cycle one bit to the right to divide the second duty cycle signal by 2 and provide the divided second duty cycle to the multiplexer 604. The second shift register (SHR 2) 612 may shift the second duty cycle by two bits to the right to divide the second duty cycle signal by 4 and provide the divided second duty cycle to the multiplexer 604.
When the select signal is in the first state, the multiplexer 604 outputs the second duty cycle signal as the duty cycle signal for the buck-boost converter 204. When the select signal is in the second state, multiplexer 604 outputs the second duty cycle signal divided by 2 as the duty cycle signal for buck-boost converter 204. When the select signal is in the third state, the multiplexer 604 outputs the second duty cycle signal divided by 4 as the duty cycle signal for the buck-boost converter 204.
Fig. 7 is a functional block diagram of an example implementation of DPWM module 336. The comparator module 704 generates a PWM signal based on a comparison of the duty cycle signal (output by the multiplexer 604) with the counter. More specifically, the comparator module 704 sets the PWM signal to the first state (FET ON) when the counter value (counter) is less than the second duty cycle signal. When the counter value is not less than the second duty cycle signal, the comparator module 704 sets the PWM signal to a second state (FET is OFF).
Counter 708 resets the counter value to zero each time an enable signal is generated. Counter 708 increments a counter value each time a DPWM clock signal is generated.
Fig. 8 is an example graph that includes the inductor current and output voltage (at node N4) with a scalar always equal to 1 and a second duty cycle signal always used as the duty cycle of buck-boost converter 204. Fig. 9 is an example graph including inductor current and output voltage (at node N4) resulting from the use of scalar values and adjustment of duty cycle as described above. As shown, the use of a scalar and adjustment of the duty cycle reduces ripple in the output voltage (at node N4) and reduces ripple in the inductor current.
Fig. 10 is an example graph including counter values, a start signal, and different PWM output signals generated based on differently divided second duty cycles.
Fig. 11 is an example plot of inductor current including switching frequency (Fsw), states of first FET M1 through fourth FET M4, and boost mode operation of buck-boost converter 204. Fig. 12 is an example plot of inductor current including switching frequency (Fsw), states of first FET M1 through fourth FET M4, and buck mode operation of buck-boost converter 204. The scalar is 1 during 1x FET switch mode and the scalar is 2 during 2x FET switch mode. Thus, a start signal that is twice as large as usual will be generated, and a second duty cycle divided by 2 will be used as the duty cycle during 2X FET switch mode. During 4x FET switch mode, the scalar is 4. Thus, a start signal that is four times as large as usual will be generated, and a second duty cycle (the number of counts) divided by 4 will be used as the duty cycle during 4X FET switch mode. As shown, the peak-to-peak inductor current ripple is reduced by operating in 2x FET switch mode.
Fig. 13 is an example graph including a selection signal, an inductor current, an output voltage (at node N4), and a duty cycle. As shown, peak-to-peak inductor current ripple and peak-to-peak output voltage ripple are reduced by operating in 2x FET switch mode.
Fig. 14 is an example graph including a counter value, a state of an enable signal, a state of a select signal, a PWM output signal, a second duty cycle signal, and a duty cycle signal (as output by multiplexer 604).
Fig. 15 is a flowchart including an example method of controlling switching of FETs of buck-boost converter 204. In various embodiments, the scalar may be initialized to 1. At 1504, the control module 320 receives a sample of the error signal. At 1508, the control module 320 receives or determines operating parameters such as the feedforward signal and the battery current.
At 1512, the sigma-delta modulator module 116 determines a first duty cycle signal, as discussed above. At 1516, the duty cycle module 404 determines a second duty cycle signal, as discussed above. At 1520, the first shift register 608 shifts the second duty cycle signal to the right by 1 bit to produce a duty cycle equal to half the second duty cycle signal (i.e., the second duty cycle signal divided by 2). The second shift register 612 shifts the second duty cycle signal by 2 bits to the right to generate a duty cycle equal to one-fourth of the second duty cycle signal (i.e., the second duty cycle signal divided by 4).
At 1524, the first comparison module 504-sixth comparison module 524 sets the state of the first comparison signal-sixth comparison signal, as discussed above. At 1528, the start-up and clock module 528 generates the select signal based on the first comparison signal through the sixth comparison signal. The launch and clock module 528 also determines a scalar based on the first comparison signal through the sixth comparison signal and generates a launch signal at a rate equal to the predetermined rate multiplied by the scalar.
At 1532, multiplexer 604 selects the second duty cycle signal, the second duty cycle signal of 1/2, or the second duty cycle signal of 1/4 as the duty cycle signal of buck-boost converter 204. When the scalar is 1, the second duty cycle signal will be selected. When the scalar is2, a second duty cycle signal of 1/2 will be selected. When the scalar is 4, a second duty cycle signal of 1/4 will be selected.
At 1536, DPWM module 336 generates a PWM signal for the FETs of buck-boost converter 204 based on the duty cycle output from multiplexer 604 and the enable signal. At 1540, gate drive module 344 applies a signal to the gate of the FET of buck-boost converter 204 based on the PWM signal output by DPWM module 336. For the next sample, control returns to 1504.
Fig. 16 is a flowchart including an example method of controlling switching of FETs of buck-boost converter 204. In various embodiments, the scalar may be initialized to 1. At 1604, the control module 320 receives a sample of the error signal. At 1608, the control module 320 receives or determines operating parameters such as feed forward signals and battery current.
At 1612, control module 320 selectively adjusts the FET switching frequency based on one or more operating parameters. For example, the control module 320 may increase the scalar (from 1) with at least one of: the battery current increases; the amplitude of the input signal increases; and the second duty cycle increases. The control module 320 may decrease the scalar toward 1 (or to 1) as a function of at least one of: the battery current decreases; the amplitude of the input signal decreases; and the second duty cycle is reduced. The control module 320 may multiply the scalar by a predetermined rate (corresponding to a predetermined frequency). At 1616, DPWM and gate drive module 124 drives the FETs of buck-boost converter 204 based on the FET switching frequency.
The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be performed in a different order (or simultaneously) without altering the principles of the present disclosure. Further, while each embodiment is described above as having certain features, any one or more of those features described with respect to any other embodiment of the disclosure may be implemented in and/or combined with the features of any other embodiment, even if a combination of the features with any other embodiment is not explicitly described. In other words, the described embodiments are not mutually exclusive, and an arrangement of one or more embodiments with each other is still within the scope of the present disclosure.
Spatial and functional relationships between elements (e.g., between modules, circuit elements, semiconductor layers, etc.) are described using various terms including "connected," joined, "" coupled, "" adjacent, "" at the top of … …, "" above … …, "" below … …, "and" disposed. Unless specifically stated as "direct", when a relationship between a first element and a second element is described in the above disclosure, such relationship may be a direct relationship when no other intermediate elements are present between the first element and the second element, but may also be an indirect relationship when one or more intermediate elements are present (spatially or functionally) between the first element and the second element. As used herein, the phrase "at least one of A, B and C" should be interpreted to mean logic (a or B or C) that uses a non-exclusive logical or, and should not be interpreted to mean "at least one of a, at least one of B, and at least one of C".
In the figures, the direction of the arrows (as indicated by the arrows) generally indicates the flow of information (such as data or instructions) that is advantageous for illustration. For example, when element a and element B exchange various information but the information transmitted from element a to element B is related to the illustration, an arrow may be directed from element a to element B. This unidirectional arrow does not mean that no other information is transmitted from element B to element a. Further, for information sent from element a to element B, element B may send a request for the information to element a or receive an acknowledgement of the information.
In the present application, including the following definitions, the term "module" or the term "controller" may be replaced with the term "circuit". The term "module" may refer to, be part of, or include the following: an Application Specific Integrated Circuit (ASIC); digital, analog or hybrid analog/digital discrete circuits; digital, analog, or hybrid analog/digital integrated circuits; a combinational logic circuit; a Field Programmable Gate Array (FPGA); processor circuitry (shared, dedicated, or group) that executes code; a memory circuit (shared, dedicated, or group) that stores code executed by the processor circuit; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.
The module may include one or more interface circuits. In some examples, the interface circuit may include a wired or wireless interface to a Local Area Network (LAN), the internet, a Wide Area Network (WAN), or a combination thereof. The functionality of any given module of the present disclosure may be distributed among a plurality of modules connected via interface circuitry. For example, multiple modules may allow load balancing. In further examples, a server (also referred to as a remote or cloud) module may implement some functionality on behalf of a client module.
The term "code" as used above may include software, firmware, and/or microcode, and may refer to programs, routines, functions, classes, data structures, and/or objects. The term "shared processor circuit" encompasses a single processor circuit that executes some or all code from multiple modules. The term "set of processor circuits" includes processor circuits that execute some or all code from one or more modules in combination with additional processor circuits. References to "multiple processor circuits" include multiple processor circuits on a discrete die, multiple processor circuits on a single die, multiple cores of a single processor circuit, multiple threads of a single processor circuit, or combinations thereof. The term "shared memory circuit" encompasses a single memory circuit that stores some or all code from multiple modules. The term "set of memory circuits" encompasses memory circuits that store some or all code from one or more modules in combination with additional memory.
The term "memory circuit" is a subset of the term "computer-readable medium". The term "computer-readable medium" as used herein does not include transitory electrical or electromagnetic signals propagating through a medium (such as on a carrier wave); thus, the term "computer-readable medium" may be considered tangible and non-transitory. Non-limiting examples of the non-transitory tangible computer readable medium are non-volatile memory circuits (such as flash memory circuits, erasable programmable read-only memory circuits, or mask read-only memory circuits), volatile memory circuits (such as static random access memory circuits or dynamic random access memory circuits), magnetic storage media (such as analog or digital magnetic tape or hard disk drives), and optical storage media (such as CDs, DVDs, or blu-ray discs).
The apparatus and methods described in this disclosure may be practiced, in part or in whole, by special purpose computers created by configuring a general purpose computer to perform one or more specific functions that are embodied in a computer program. The above-described functional blocks, flowchart components, and other elements serve as software specifications that can be converted into computer programs by routine work of a skilled person or programmer.
The computer program includes processor-executable instructions stored on at least one non-transitory tangible computer-readable medium. The computer program may also include or be dependent on stored data. The computer program may include a basic input/output system (BIOS) that interacts with the hardware of a special purpose computer, a device driver that interacts with a particular device of a special purpose computer, one or more operating systems, user applications, background services, background applications, and the like.
The computer program may include: (i) Descriptive text to be parsed, such as HTML (hypertext markup language), XML (extensible markup language) or JSON (JavaScript object notation); (ii) assembly code; (iii) object code generated by a compiler from source code; (iv) source code for execution by the interpreter; (v) Source code for compilation and execution by a just-in-time compiler, and so forth. For example only, source code may be used from the sources including C, C ++, C#, objective-C, swift, haskell, go, SQL, R, lisp,Fortran、Perl、Pascal、Curl、OCaml、/>HTML5 (hypertext markup language 5 th revision), ada, ASP (dynamic server page), PHP (PHP: hypertext preprocessor), scala, eiffel, smalltalk, erlang, ruby,/>Visual />Lua, MATLAB, SIMULINK and/>Is written in the grammar of the language.
No element recited in a claim is intended to be a means-plus-function element within the meaning of 35u.s.c. ≡112 (f) unless the element is explicitly recited using the phrase "means for … …" or in the case of a method claim, using the phrase "operation for … …" or "step for … …".

Claims (20)

1. An amplifier system, comprising:
A voltage converter comprising at least one of:
A buck converter; and
A boost converter;
A first module configured to determine a first switching rate for switching a Field Effect Transistor (FET) of the voltage converter based on an input sample;
a second module configured to determine a second switching rate for switching FETs of the voltage converter based on a battery voltage and the first switching rate;
a third module configured to generate a third switching rate of a FET of the voltage converter based on the second switching rate and at least one of a battery current and an amplitude of the input sample;
A fourth module configured to generate a switching output for switching a FET of the voltage converter based on the third switching rate; and
A fifth module configured to apply power to a gate terminal of a FET of the voltage converter based on the switch output.
2. The amplifier system of claim 1, wherein the third module is configured to set the third switching rate to the second switching rate when all of the following are satisfied:
the battery current is less than a predetermined current; and
The amplitude of the input sample is less than a predetermined voltage.
3. The amplifier system of claim 2, wherein the third module is configured to set the third switching rate to be greater than the second switching rate when the battery current is greater than the predetermined current.
4. The amplifier system of claim 3, wherein the third module is configured to set the third switching rate to at least twice the second switching rate when the battery current is greater than a second predetermined current, wherein the second predetermined current is greater than the predetermined current.
5. The amplifier system of claim 3, wherein the third module is configured to transition the third switching rate from greater than the second switching rate to the second switching rate when the battery current transitions from greater than a second predetermined current to less than the second predetermined current, wherein the second predetermined current is less than the predetermined current.
6. The amplifier system of claim 2, wherein the third module is configured to set the third switching rate to be greater than the second switching rate when the amplitude of the input samples is greater than the predetermined voltage.
7. The amplifier system of claim 6, wherein the third module is configured to set the third switching rate to at least twice the second switching rate when the amplitude of the input sample is greater than a second predetermined voltage, wherein the second predetermined voltage is greater than the predetermined voltage.
8. The amplifier system of claim 6, wherein the third module is configured to transition the third switching rate from greater than the second switching rate to the second switching rate when the amplitude of the input sample transitions from greater than a second predetermined voltage to less than the second predetermined voltage, wherein the second predetermined voltage is less than the predetermined voltage.
9. The amplifier system of claim 2, wherein the third module is configured to set the third switching rate to be greater than the second switching rate when the second switching rate is greater than a predetermined switching rate.
10. The amplifier system of claim 9, wherein the third module is configured to set the third switching rate to at least twice the second switching rate when the second switching rate is greater than a second predetermined switching rate, wherein the second predetermined switching rate is greater than the predetermined switching rate.
11. The amplifier system of claim 9, wherein the third module is configured to transition the third switching rate from greater than the second switching rate to less than the second predetermined switching rate when the second switching rate transitions from greater than the second predetermined switching rate to less than the second predetermined switching rate, wherein the second predetermined switching rate is less than the predetermined switching rate.
12. The amplifier system of claim 1, wherein the third module is configured to set the third switching rate based on all of the battery current, the amplitude of the input sample, and the second switching rate.
13. The amplifier system of claim 1, wherein the third module is configured to transition the third switching rate to be greater than the second switching rate when at least one of:
the battery current is greater than a first predetermined current;
The amplitude of the input sample is greater than a first predetermined voltage; and
The second switching rate is greater than the first predetermined switching rate.
14. The amplifier system of claim 13, wherein the third module is configured to transition the third switching rate to at least twice the second switching rate when at least one of:
The battery current is greater than a second predetermined current, wherein the second predetermined current is greater than the first predetermined current;
The amplitude of the input sample is greater than a second predetermined voltage, wherein the second predetermined voltage is greater than the first predetermined voltage; and
The second switching rate is greater than a second predetermined switching rate, wherein the second predetermined switching rate is greater than the first predetermined switching rate.
15. The amplifier system of claim 1, further comprising:
A speaker; and
An H-bridge configured to receive an output from the voltage converter and apply power to the speaker.
16. An amplifier system, comprising:
A voltage converter comprising at least one of:
A buck converter; and
A boost converter;
a power stage configured to receive a power output from the voltage converter and apply power to a load;
a control module configured to set a switching rate of a Field Effect Transistor (FET) of the voltage converter based on one or more operating parameters;
A Digital Pulse Width Modulation (DPWM) module configured to generate a Pulse Width Modulation (PWM) output for switching FETs of the voltage converter based on the switching rate; and
A gate drive module configured to apply power to a gate terminal of a FET of the voltage converter based on the PWM output.
17. The amplifier system of claim 16, wherein the control module is configured to at least one of:
increasing the switching rate as the battery current increases; and
The switching rate is reduced as the battery current decreases.
18. The amplifier system of claim 16, wherein the control module is configured to at least one of:
increasing the switching rate as the amplitude of the input samples increases; and
The switching rate is reduced as the amplitude of the input samples decreases.
19. The amplifier system of claim 16, wherein the control module is configured to determine the switching rate based on a second switching rate and at least one of:
increasing the switching rate as the second switching rate increases; and
The switching rate is reduced as the second switching rate is reduced.
20. An amplifier control method, comprising:
determining a first switching rate of a Field Effect Transistor (FET) for a switching voltage converter based on an input sample, the voltage converter comprising at least one of:
A buck converter; and
A boost converter;
Determining a second switching rate for switching FETs of the voltage converter based on the battery voltage and the first switching rate;
Generating a third switching rate of the FET of the voltage converter based on the second switching rate and at least one of a battery current and an amplitude of the input sample;
Generating a switching output for switching the FET of the voltage converter based on the third switching rate; and
Power is applied to a gate terminal of a FET of the voltage converter based on the switch output.
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