CN112018127B - Method for forming metal layer, 3D memory device and manufacturing method thereof - Google Patents

Abstract

Disclosed are a metal layer forming method, a 3D memory device and a method of manufacturing the same, the metal layer forming method including: sequentially stacking a hard mask, a first sacrificial layer and a first photoresist layer on the surface of the dielectric layer; etching the first sacrificial layer through the patterned first photoresist layer to form a plurality of axial cores; forming oxide layers on the surfaces of a plurality of shaft cores; patterning the oxide layer to remove the shaft core and form a plurality of side walls; forming a second sacrificial layer at the gaps and the tops of the side walls; etching the second sacrificial layer and part of the hard mask through the patterned second photoresist layer by taking the side wall as a barrier; etching the dielectric layer through the opening of the hard mask; and filling a metal layer in the opening of the dielectric layer, wherein the hard mask comprises a nitride layer. The forming method of the metal layer adopts the nitride layer as a hard mask, reduces the process temperature, ensures the line roughness of the metal layer and expands the process application range.

Description

Method for forming metal layer, 3D memory device and manufacturing method thereof

Technical Field

The present invention relates to the field of memory technology, and more particularly, to a method of forming a metal layer, a 3D memory device, and a method of manufacturing the same.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor fabrication processes become smaller, memory density of memory devices becomes higher. In order to further increase the storage density, three-dimensional structured memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can improve integration in multiple per unit area of a wafer, and can reduce cost. Currently two main 3D memory devices used as non-volatile flash memories employ NAND and NOR structures, respectively. The NAND memory device has the advantages of high writing speed, simple erasing operation, realization of smaller memory cells and wide application.

In a 3D memory device of a NAND structure, a stacked structure is employed to provide gate conductors of a selection transistor and a memory transistor, and a large number of metal wirings are employed to provide electrical connection of the transistors to external circuits. The formation of peripheral circuits requires a good process environment, such as the fabrication of bit lines, and currently polysilicon masks are usually used to form the peripheral circuits in a high temperature environment, and the wafer is easily warped due to the excessive temperature, so that some film layers on the back surface of the wafer are cracked and fall off, and the device is disabled. Accordingly, further improvements in the structure of 3D memory devices and methods of manufacturing the same are desired to improve the yield and reliability of 3D memory devices.

Disclosure of Invention

In view of the foregoing, an object of the present invention is to provide a method for forming a metal layer, a 3D memory device and a method for manufacturing the same, in which a self-aligned double patterning process is used to form a metal layer inside the 3D memory device, and nitride is used as a hard mask, so that the process temperature is reduced, the process range is enlarged, and wafer deformation and film falling are avoided, thereby improving the yield and reliability of the 3D memory device.

According to a first aspect of the present invention, there is provided a method of forming a metal layer, comprising:

sequentially stacking a hard mask, a first sacrificial layer and a first photoresist layer on the surface of the dielectric layer;

etching the first sacrificial layer through the patterned first photoresist layer to form a plurality of axial cores;

Forming oxide layers on the surfaces of a plurality of shaft cores;

Patterning the oxide layer to remove the shaft core and form a plurality of side walls;

Forming a second sacrificial layer at the gaps and the tops of the side walls;

Etching the second sacrificial layer and part of the hard mask through the patterned second photoresist layer by taking the side wall as a barrier;

Etching the dielectric layer through the opening of the hard mask;

and filling a metal layer in the opening of the dielectric layer, wherein the hard mask comprises a nitride layer.

Preferably, the hard mask comprises a multilayer structure including a first silicon oxynitride layer, a titanium nitride layer and a second silicon oxynitride layer sequentially stacked on the surface of the dielectric layer.

Preferably, the thickness of the first silicon oxynitride layer is 75-150 angstroms; the thickness of the titanium nitride layer is 50-150 angstroms; the thickness of the second silicon oxynitride layer is 250-500 angstroms.

Preferably, the first sacrificial layer comprises a first spin-on carbon layer and a third silicon oxynitride layer; the second sacrificial layer comprises a second spin-on carbon layer and a fourth silicon oxynitride layer.

Preferably, the hard mask is etched using an integrated etching method.

Preferably, the metal layer comprises copper, and bit lines are formed in communication with the metal layer.

Preferably, patterning the oxide layer to remove the mandrel, and forming the plurality of side walls includes:

etching to remove an oxide layer on the top surface of the shaft core and the oxide layer at the bottom of a gap between two adjacent shaft cores;

Etching to remove a plurality of shaft cores;

And forming a plurality of side walls positioned on the surface of the hard mask.

According to a second aspect of the present invention, there is provided a 3D memory device comprising:

A substrate, wherein an epitaxial layer is formed inside the substrate;

A stacked structure on a surface of the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

A plurality of channel pillars extending through the stacked structure; and

The dielectric layer is positioned on the surface of the laminated structure, and the metal layer is positioned in the dielectric layer and is electrically connected with the channel column.

Preferably, the metal layer includes a plurality of metal blocks, one of the metal blocks being formed above each of the channel pillars.

Preferably, a connecting block is formed between the top of the channel column and the metal block, and the connecting block is made of tungsten.

According to a third aspect of the present invention, there is provided a method of manufacturing a 3D memory device, comprising:

Growing an epitaxial layer on the substrate;

forming a stacked structure on a surface of the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

forming a plurality of channel pillars through the stacked structure;

Forming a dielectric layer on the surface of the laminated structure; and

And forming a metal layer inside the dielectric layer by adopting the forming method of the metal layer.

According to the metal layer forming method, the 3D memory device and the manufacturing method thereof, the SADP (self-aligned double patterning) process is adopted to etch the structure on the surface of the dielectric layer, nitride is adopted as a hard mask, the process temperature required by etching is reduced, wafer warpage caused by thermal stress in the heat treatment process is avoided, the application range of the SADP process is enlarged, the line roughness of the metal layer is further controlled, and the process is controllable, so that the yield and reliability of the 3D memory device are improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1a and 1b show an equivalent circuit diagram and a schematic structure diagram of a memory cell string of a 3D memory device, respectively.

Fig. 2 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention.

Fig. 3a and 3b are schematic cross-sectional views illustrating an etching process of a metal layer in a conventional 3D memory device and an etching process of a metal layer in a 3D memory device according to an embodiment of the present invention, respectively.

Fig. 4a to 4l show schematic cross-sectional views of stages of a method of forming a metal layer in a 3D memory device according to an embodiment of the present invention.

Fig. 5 illustrates a schematic cross-sectional structure of a 3D memory device according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.

It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.

If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying and adjoining … …" will be used herein.

In the present application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a memory device, including all layers or regions that have been formed. Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.

In a 3D memory device of a NAND structure, a stacked structure is used to provide gate conductors of a select transistor and a memory transistor, and a large number of metal wirings are used to provide electrical connection.

Fig. 1a and 1b show a circuit diagram and a schematic diagram of a memory cell string of a 3D memory device, respectively. The memory cell string shown in this embodiment includes a case of 4 memory cells.

As shown in fig. 1a, the memory cell string 100 has a first terminal connected to the bit line BL and a second terminal connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string selection line SSL, and the gate of the second selection transistor Q2 is connected to the ground selection line GSL. The gates of the memory transistors M1 to M4 are connected to the corresponding word lines of the word lines WL1 to WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductors 121, respectively. The gate conductors 121, 122, and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 penetrates the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are sandwiched between a gate conductor 121 and a channel layer 111, thereby forming memory transistors M1 to M4. A blocking dielectric layer 114 is interposed between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are each composed of an oxide, for example, silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, for example, silicon nitride containing microparticles of a metal or semiconductor, and the gate conductors 121, 122, and 123 are composed of a metal, for example, tungsten. The channel layer 111 is used to provide channel regions for controlling the select transistors and the memory transistors.

In the write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 to M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, the ground selection line GSL is biased to about zero volt while the source line SL is grounded, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to the high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, the bit line BL is grounded, the word line WL2 is biased at a programming voltage VPG, e.g. around 20V, and the remaining word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.

In the read operation, the memory cell string 100 judges the amount of charge in the charge storage layer according to the on state of a selected one of the memory transistors M1 to M4, thereby obtaining data representing the amount of charge. Taking memory transistor M2 as an example, word line WL2 is biased at read voltage VRD and the remaining word lines are biased at high voltage VPS2. The on state of the memory transistor M2 is related to its threshold voltage, i.e. to the amount of charge in the charge storage layer, so that the data value can be determined from the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in the on state, and thus, the on state of the memory cell string 100 depends on the on state of the memory transistor M2. The control circuit judges the on state of the memory transistor M2 from the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention. For clarity, the various insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device shown in this embodiment includes 4*4 total 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 total 64 memory cells. It will be appreciated that the invention is not so limited.

In a 3D memory device, the memory cell strings include respective channel pillars 110, and common gate conductor layers 121, 122, and 123, respectively. Adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The channel pillars 110 penetrate the gate stack 120 and are arranged in an array, and the plurality of channel pillars 110 of a same column are commonly connected to a same bit line (i.e., one of bit lines BL1 to BL 4) at first ends thereof, are commonly connected to the substrate 101 at second ends thereof, and form a common source connection via the substrate 100. The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail herein.

The gate conductor 122 of the string select transistor Q1 is split into different gate lines by a gate line slit (GATE LINE SLIT). The gate lines of the plurality of channel pillars 110 of the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SGD1 to SGD 4).

The gate conductors 121 of the memory transistors M1 and M4 are connected to each other in different layers. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by gate line slits, the gate lines of the same level reach the interconnection layer 132 via the respective electrical connection structures 131 to be interconnected with each other and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the electrical connection structures 133.

The gate conductors of the ground select transistors Q2 are connected in one piece. If the gate conductor 123 of the ground select transistor Q2 is split into different gate lines by gate line slits, the gate lines reach the interconnect layer 132 via the respective electrical connection structures 131, thereby being interconnected with each other, and then are connected to the same ground select line SGS via the electrical connection structures 133.

In 3D memory devices, bit lines play a critical role, and typically, metal wiring is used to provide electrical connections, including the formation of bit lines. The fabrication of the bit line metal layer is described below with respect to fig. 3 a-5.

Fig. 3a and 3b are schematic cross-sectional views illustrating an etching process of a metal layer in a conventional 3D memory device and an etching process of a metal layer in a 3D memory device according to an embodiment of the present invention, respectively.

As shown in fig. 3a, a schematic diagram of a portion of a structure above a channel pillar is shown when a conventional bit line metal layer is fabricated. A plurality of connection blocks 161 are formed at the bottom of the dielectric layer 140, channel pillars are connected below the connection blocks (see fig. 1 a-2), a mask 150 is formed above the dielectric layer, the mask 150 is patterned, and the dielectric layer 140 is used as a barrier to be etched to form grooves 162, the grooves 162 are located above the connection blocks 161 and are in contact with the connection blocks 161, and the metal layers are filled in the grooves 162 to be bit lines. In this embodiment, polysilicon is used as the mask 150, and an SADP (self-aligned double patterning) process is used to complete the etch.

The SADP Process is used to etch the polysilicon mask 150, the working temperature is higher than 500 ℃, the temperature is higher than 850 ℃ in the RTA (RAPID THERMAL Process, rapid thermal annealing) Process, the wafer will warp due to the influence of thermal processing stress, and some film layers on the back of the wafer will crack, break or even break away, and the structure will be damaged, thereby causing WAT (WAFER ACCEPTANCE TEST ) failure or device failure due to LKG (leakage currents, leakage current) between adjacent metal lines. Therefore, the conventional polysilicon thin film limits the application of the SADP process at low temperature. In addition, the development of 3D-NAND flash memory at present will require the roughness and defect performance of SADP bit lines more strictly, and the polysilicon mask 150 cannot further control the line roughness, so that the line surface roughness is higher, and the device performance is affected.

Based on the above problems, the embodiment of the present invention improves the forming method of the metal layer, mainly in that the mask is improved.

As shown in fig. 3b, in the present embodiment, the bottom of the dielectric layer 240 is formed with, for example, 4 connection blocks 261, and the hard mask 250 is formed on the surface of the dielectric layer 240, and the hard mask 250 includes a three-layer structure including a first silicon oxynitride layer 251, a titanium nitride layer 252 and a second silicon oxynitride layer 253 sequentially stacked on the surface of the dielectric layer 240. The hard mask 250 is patterned by an integrated etching AIO (All-in-One Etch) process, the dielectric layer 240 is etched through the opening of the hard mask 250 to form a recess 262 over the connection block 261, and a metal layer is filled inside the recess 262 to form a bit line.

In this embodiment, a three-layer structure including the titanium nitride layer 252 is used as the hard mask 250, and the etching process temperature is only 300 ℃, so that wafer warpage caused by thermal stress is avoided, and the problem of falling off or breaking of the back surface film of the wafer can be well solved. And the hard mask 250 (SiON/TiN/SiON) can be developed at a low temperature (300 c), expanding the application range of the SADP process. In addition, tiN is adopted as a mask, so that the metal layer has better line roughness control, higher etching selectivity, reduced roughness, finer process and higher reliability of the device.

Further, the thickness of the first silicon oxynitride layer 251 is 75-150 angstroms; the titanium nitride layer 252 has a thickness of 50-150 angstroms; the second silicon oxynitride layer 253 has a thickness of 250-500 angstroms.

The embodiment of the invention improves the manufacture of the bit line metal layer of the traditional 3D memory device so as to improve the reliability and the process application range of the memory and improve the memory performance. The method for forming the metal layer in the 3D memory device according to the embodiment of the present invention is described in detail below with reference to fig. 4a to 4 l.

Fig. 4a to 4l show schematic cross-sectional views of stages of a method of forming a metal layer in a 3D memory device according to an embodiment of the present invention.

As shown in fig. 4a, a hard mask, a first sacrificial layer and a first photoresist layer are sequentially stacked on the surface of the dielectric layer. The dielectric layer 240, the hard mask 250 and the connection block 261 are the same as those described in fig. 3b, and will not be repeated here. Dielectric layer 240 is, for example, an oxide layer and connection block 261 is, for example, tungsten metal. The present embodiment further includes forming a first sacrificial layer 270 and a first photoresist layer 291 on the surface of the hard mask 250, wherein the first sacrificial layer 270 includes a first spin-on carbon layer 271 (SOC) and a third silicon oxynitride layer 272, and the hard mask 250 of the present embodiment includes a three-layer structure, which can be implemented at a lower process temperature, thereby expanding a process application range.

Further, as shown in fig. 4b, the first photoresist layer 291 is patterned. The patterning of the photoresist, i.e. the conventional steps of exposure, development, etching, etc., is not limited by the choice of photoresist.

Further, as shown in fig. 4c, the first sacrificial layer is etched through the patterned first photoresist layer to form a plurality of mandrels. The first sacrificial layer 270 is etched through the patterned first photoresist layer 291 to remove unnecessary portions, and the remaining first sacrificial layer 270 forms a plurality of cores 273 spaced apart from each other, with voids 263 formed between the plurality of cores 273.

Further, as shown in fig. 4d, oxide layers are formed on the surfaces of the plurality of mandrels. An oxide layer 311 is formed on the surfaces and sidewalls of mandrel 273 and gap 263 using an atomic layer deposition process (ALD).

Further, as shown in fig. 4e, the oxide layer is patterned. And removing part of the oxide layer 311 positioned on the top of the shaft core 273 and the surface of the gap 263 by adopting wet etching, dry etching or other processes, and reserving the oxide layer 311 deposited on the side wall of the shaft core 273.

Further, as shown in fig. 4f, the mandrel is removed to form a plurality of side walls. In this step, the mandrel 273 is etched away, leaving only the oxide layer on the sidewalls thereof to form a plurality of sidewalls 312. The plurality of spacers are directly on the surface of the hard mask 250.

Further, as shown in fig. 4g, a second sacrificial layer is formed at the top and the gaps of the plurality of sidewalls. And filling gaps of the side walls 312 by using the second spin-on carbon layer 281, depositing a fourth silicon oxynitride layer 282 on the surface of the second spin-on carbon layer 281, and forming a second sacrificial layer 280 by using the second spin-on carbon layer 281 and the fourth silicon oxynitride layer 282. A second photoresist layer 292 is deposited on the surface of the second sacrificial layer 280. Only a small part of the 3D memory structure is shown in the drawing of the present embodiment, and when the rest is etched according to the process requirement, the etching of the hard mask of the present embodiment is not affected by performing this step.

Further, as shown in fig. 4h, the second photoresist layer 292 is patterned, and the patterning of the second photoresist layer 292 is performed according to actual process requirements, for example, the photoresist corresponding to the top of the sidewall 312 is completely patterned, so as to expose the fourth silicon oxynitride layer 282, which is not limited herein.

Further, as shown in fig. 4i, the second sacrificial layer and a portion of the hard mask are etched through the patterned second photoresist layer. The second photoresist layer 292 is used as a barrier, the fourth silicon oxynitride layer 282, the second spun-on carbon layer 281 and the sidewall 312 are etched, and during the etching process, the sidewall 312 forms a barrier layer on the hard mask 250, as shown in the figure, and the etching is continued with the expanded sidewall as a barrier to the lower hard mask 250, for example, the titanium nitride layer 252 and the second silicon oxynitride layer 253 of the hard mask 250 are partially etched, so as to form a plurality of openings 264 spaced apart from each other. The second sacrificial layer 280, the second photoresist layer 292, and the sidewalls 312 on the hard mask 250 are then removed.

Further, as shown in fig. 4j, the dielectric layer is etched through the openings of the hard mask. The dielectric layer 240 is etched through the opening 264 formed on the hard mask 250, forming a recess 263 over the connection block 261, and removing the uppermost silicon oxynitride layer 253 of the hard mask 250.

Further, as shown in fig. 4k, a metal layer is filled in the opening of the dielectric layer. The opening of the dielectric layer 240, i.e. the recess 263 is filled with a metal layer 320, the metal layer 320 being for example tungsten.

Further, as shown in fig. 4l, the metal layer is subjected to chemical mechanical polishing. The hard mask 250 on the surface of the dielectric layer 240 is removed and CMP (CHEMICAL MECHANICAL Polishing) is used to remove the metal layer 320 above the surface of the dielectric layer 240, forming a metal bump on top of the dielectric layer 240. The bit line BL is connected to the metal blocks.

The present embodiment only shows the process of fabricating the bit line, and the structure of the trench pillar and the like at the lower portion thereof is not shown, but the bit line shown in the present embodiment is actually electrically connected to the trench pillar located under the dielectric layer 240, and typically, the electrical connection is formed through the connection block 261 at the bottom of the dielectric layer 240.

Fig. 5 illustrates a schematic cross-sectional structure of a 3D memory device according to an embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

As shown in fig. 5, it includes a substrate 301 and a stacked structure stacked on the surface of the substrate 301, and a dielectric layer 240 and a metal layer 320 shown in fig. 4 l. The stacked structure includes a plurality of gate conductors 120 and a plurality of interlayer insulating layers 124 alternately stacked, and the memory device further includes a plurality of channel pillars (4 are shown) penetrating the stacked structure. The inside of the channel pillar is the same as the structure shown in fig. 1b, and the channel pillar of this embodiment includes a channel layer 111 extending along the inner wall of the channel hole, a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114, and further, an insulating void 116 and a filling insulating layer 115 surrounding the insulating void are formed in the channel hole.

The 3D memory device further includes forming a conductive block 261 and a bit line structure 320 on top of the channel pillar (the end remote from the substrate 101), and a dielectric layer 240. The conductive block 261 is located between the top of the channel pillar and the metal block. The conductive block 261 may also be located on top of the channel pillar, surrounded by the channel layer 111.

A method of manufacturing the 3D memory device will be briefly described with reference to fig. 5. First, a semiconductor substrate 101 is provided, and then an epitaxial layer 102 is formed on the substrate. In this embodiment, the semiconductor substrate 101 is, for example, a single crystal silicon substrate. An insulating stack structure is then formed on the substrate 101. The insulating stack structure includes a plurality of interlayer insulating layers and a plurality of sacrificial layers alternately stacked. In this embodiment, the interlayer insulating layer is composed of, for example, silicon oxide, and the sacrificial layer is composed of, for example, silicon nitride. The number of insulating layers and sacrificial layers between the inner layers of the insulating laminated structure can be 32, 64, 96 or 128, etc., and can be set according to actual needs, without limitation. In a subsequent process, the sacrificial layer will be replaced with a gate conductor 120, which gate conductor 120 is further connected to the word line.

Further, a plurality of channel pillars penetrating the stacked structure are formed. A channel hole is first formed in a middle region (core region) in the insulating stack. Then, a channel pillar is formed in the channel hole. The structure of the channel pillar is, for example, ONOP (oxide-nitride-oxide-polysilicon), that is, the channel pillar includes a functional sidewall layer and a channel layer 111, the functional sidewall layer continuously extending along the inside of the channel hole is formed, the functional sidewall layer sequentially includes a blocking dielectric layer 114, a charge storage layer 113 and a tunneling dielectric layer 112 from the sidewall to the center of the channel hole, the channel layer 111 is located on the surface of the functional sidewall layer, extends along the inner wall of the channel hole 110, and the channel layer 111 is a polysilicon layer. In an example, the sum of the thicknesses of the functional sidewall layer and the channel layer 111 may be less than half the width of the channel hole, where a reserved space for filling the insulating layer remains in the channel hole after the channel layer 111 is formed. When the reserved space is reserved, the step of forming the filling insulation layer 115 in the channel hole 110 is further included, and the filling insulation layer 115 may be formed in the channel hole 110 by using a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. The material of the filling insulating layer 115 may include an oxide dielectric layer, such as silicon oxide, etc., and the filling insulating layer 115 may fill the channel hole 110. In addition, in an example, the insulating gap 116 may also be formed in the filling insulating layer 115 by controlling deposition process parameters of the filling insulating layer 115.

As an example, the channel layer 111 is formed further including the steps of: the channel hole 110 is filled with a filling insulating layer 115, a connection block 261 is prepared on the filling insulating layer 115, the side edge of the connection block 261 is contacted with the channel layer 111, and the surface of the connection block 117 is covered with a dielectric layer 240. The connection block 261 is located on top of the channel hole and is in contact with the functional sidewall layer and the channel layer 111 to realize electrical connection. Further, a plurality of bit lines are formed at the tops of the channel pillars, and the plurality of channel pillars are respectively connected to the plurality of bit lines. A plurality of bit lines 320 are formed at the tops of the channel pillars, and a connection block 261, such as tungsten, provides electrical connection between the channel pillars and the bit lines 320.

Further, back end of line (BEOL) and peripheral circuits are formed around the channel pillar. For example, pads may also be provided around the channel pillars to connect with peripheral circuits, or to form CMOS circuits. Thereby completing the fabrication of the 3D memory device.

In summary, according to the method for forming the metal layer provided by the invention, nitride is adopted as a hard mask, and SADP (self-aligned double patterning) technology is adopted to etch the hard mask, the sacrificial layer and other structures on the surface of the dielectric layer, so that the temperature required by the technology is reduced, the wafer warpage caused by the action of thermal stress in the heat treatment process is avoided, the application range of the SADP technology is enlarged, the line roughness of the metal layer is further controlled, and the technological process is controllable, thereby improving the yield and reliability of the 3D memory device.

Further, in the 3D memory device, the metal layer is used for fabricating the bit line, and is formed on the top of the channel pillar, and the metal layer and the channel pillar are electrically connected through the connection block, so that data can be transmitted better.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present invention are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims (10)

1. A method for forming a metal layer includes:

sequentially stacking a hard mask, a first sacrificial layer and a first photoresist layer on the surface of the dielectric layer, wherein the hard mask comprises a multilayer structure, and the multilayer structure comprises a first silicon oxynitride layer, a titanium nitride layer and a second silicon oxynitride layer which are sequentially stacked on the surface of the dielectric layer;

etching the first sacrificial layer through the patterned first photoresist layer to form a plurality of axial cores;

Forming oxide layers on the surfaces of a plurality of shaft cores;

Patterning the oxide layer to remove the shaft core and form a plurality of side walls;

Forming a second sacrificial layer at the gaps and the tops of the side walls;

Etching the second sacrificial layer and part of the hard mask through the patterned second photoresist layer by taking the side wall as a barrier, and etching part of the titanium nitride layer and the second silicon oxynitride layer of the hard mask to form a plurality of openings which are spaced mutually;

Etching the dielectric layer through the opening of the hard mask;

Filling a metal layer in the opening of the dielectric layer;

and carrying out chemical mechanical polishing on the metal layer, and removing the hard mask on the surface of the dielectric layer.

2. The method of forming a metal layer according to claim 1, wherein the first silicon oxynitride layer has a thickness of 75-150 angstroms; the thickness of the titanium nitride layer is 50-150 angstroms; the thickness of the second silicon oxynitride layer is 250-500 angstroms.

3. The method of forming a metal layer of claim 1, wherein the first sacrificial layer comprises a first spin-on carbon layer and a third silicon oxynitride layer; the second sacrificial layer comprises a second spin-on carbon layer and a fourth silicon oxynitride layer.

4. The method of forming a metal layer according to claim 1, wherein the hard mask is etched using an integrated etching method.

5. The method of claim 1, wherein the metal layer comprises copper and a bit line is formed in communication with the metal layer.

6. The method of forming a metal layer of claim 1, wherein patterning the oxide layer to remove the mandrel, forming a plurality of sidewalls comprises:

etching to remove an oxide layer on the top surface of the shaft core and the oxide layer at the bottom of a gap between two adjacent shaft cores;

Etching to remove a plurality of shaft cores;

And forming a plurality of side walls positioned on the surface of the hard mask.

7. A 3D memory device, comprising:

A substrate, wherein an epitaxial layer is formed inside the substrate;

A stacked structure on a surface of the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

A plurality of channel pillars extending through the stacked structure; and

The metal layer is positioned in the dielectric layer and is electrically connected with the channel column, and the metal layer is positioned in the dielectric layer and is formed according to the forming method of the metal layer in any one of claims 1-6.

8. The 3D memory device of claim 7, wherein the metal layer comprises a plurality of metal blocks, one formed over each of the channel pillars.

9. The 3D memory device of claim 8, wherein a connection block is formed between the channel pillar top and the metal block, the connection block being of tungsten.

10. A method of manufacturing a 3D memory device, comprising:

Growing an epitaxial layer on a substrate;

forming a stacked structure on a surface of the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

forming a plurality of channel pillars through the stacked structure;

Forming a dielectric layer on the surface of the laminated structure; and

A metal layer is formed inside the dielectric layer by the metal layer forming method as claimed in any one of claims 1 to 6.