CN112018079A - Copper interconnection structure and preparation method thereof - Google Patents
Copper interconnection structure and preparation method thereof Download PDFInfo
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
The invention discloses a copper interconnection structure and a preparation method thereof. The copper interconnect structure includes: the device comprises a copper metal wire (200), a first etching stop layer (201), a first dielectric layer (202), a second etching stop layer (203) and a second dielectric layer (204) from bottom to top in sequence; a through hole/trench structure vertically communicated with the first etching stop layer (201), the first dielectric layer (202), the second etching stop layer (203) and the second dielectric layer (204), wherein the trench is positioned above the through hole; AlN/Al2O3A laminated film (206), a barrier layer (207) and a copper film (208), wherein AlN/Al2O3A laminated film (206) is formed on the side walls of the via hole and the trench, and is not in contact with the bottom of the via hole; a barrier layer (207) covers the AlN/Al2O3Laminating a film (206) and covering the surface of the copper metal line (200) at the bottom of the via; copper foilThe film (208) completely fills the via/trench interior; a copper diffusion capping layer (209) covers an upper surface of the copper interconnect structure.
Description
Technical Field
The invention belongs to the field of integrated circuit manufacturing, and particularly relates to a copper interconnection structure and a preparation method thereof.
Background
With the rapid development of very large scale integrated circuits, the integration level of chips is continuously improved, and the feature size is continuously reduced. The multilayer wiring of metal interconnects causes an increase in resistance of metal wires, line-to-line capacitance, and interlayer capacitance, thereby increasing RC delay time, crosstalk noise, power consumption, and the like, which are the limiting factors for further development of integrated circuits. In order to solve the above problems, on one hand, a Cu metal interconnection (resistivity of 1.7 μ Ω · cm) is used instead of an Al metal interconnection (resistivity of 3 μ Ω · cm), reducing the resistance; on the other hand, the low dielectric constant (low-k) dielectric material (such as SiCOH) is used to replace silicon dioxide (k > 3.9), so as to reduce the parasitic capacitance between metal interconnection layers. In order to fill more copper layers with low resistivity and without holes in the trenches and vias of the copper interconnect dual damascene process, the requirements of the latter processes of the integrated circuit on the thickness and quality of the diffusion barrier layer are increasing. According to the international semiconductor technology development program, the thickness requirement of an advanced microprocessor unit (MPU) technology in an integrated circuit process on a diffusion barrier layer is reduced to be below 3nm at a technical node below 14 nm. For such a thin diffusion barrier layer, it is still required to have good compactness, excellent deep hole step coverage and high temperature thermal stability, thereby improving reliability and life of the chip. The atomic layer deposition has the characteristic of self-limiting growth, so that the grown diffusion barrier layer film has high step coverage rate and good conformality. However, copper interconnect processes still face some challenges. For example, although the use of low dielectric constant films can reduce parasitic capacitance, low dielectric constant films generally have the property of being porous; therefore, when the atomic layer deposition technology is adopted to deposit the conductive barrier layer film on the surface of the low-dielectric-constant film, the conductive barrier layer film can easily permeate into the porous structure of the low-dielectric-constant film, so that the electric leakage of the low-dielectric-constant film is increased. Furthermore, since the barrier layer will be reduced to below 3nm, this requires that the barrier layer be grown to avoid the occurrence of pinholes. However, for barrier layers of TaN, TiN and the like, steric hindrance occurs when precursor molecules are adsorbed on the surface of the substrate, so that when the barrier layer is very thin, pinholes are easy to occur in the atomic layer deposition process, and the barrier effect of the barrier layer on copper diffusion is reduced.
Disclosure of Invention
In order to solve the above problems, the present invention discloses a copper interconnect structure, comprising: the device comprises a copper metal wire, a first etching stop layer, a first dielectric layer, a second etching stop layer and a second dielectric layer from bottom to top in sequence; a through hole/trench structure vertically connected to each other and penetrating through the first etching stop layer, the first dielectric layer, the second etching stop layer and the second dielectric layer, wherein the trench is located above the through hole; AlN/Al2O3A laminated film, a barrier layer and a copper film, wherein the AlN/Al2O3The laminated film is formed on the side walls of the through hole and the groove and is not contacted with the bottom of the through hole; the barrier layer covers the AlN/Al2O3Laminating a film and covering the surface of the copper metal wire at the bottom of the through hole; the copper film completely fills the through hole/the groove; and a copper diffusion covering layer covering the upper surface of the copper interconnection structure.
In the copper interconnection structure of the present invention, preferably, the barrier layer is at least one of Ru/TaN, Co/TiN, Co/WN, Co/ZrN, and Ru/TiN.
In the copper interconnect structure of the present invention, preferably, the top layer of the stacked thin film of the barrier layer is Ru or Co as a seed layer and an adhesion layer.
In the copper interconnect structure of the present invention, the copper diffusion cap layer is preferably at least one of SiCN, SiC, SiN, Co, CoWP, and CuSiN.
The invention also discloses a preparation method of the copper interconnection structure, which comprises the following steps: sequentially forming a first etching termination layer, a first dielectric layer, a second etching termination layer and a second dielectric layer by taking a first copper metal wire as an initial substrate; forming a via/trench structure vertically connected to the first etch stop layer and the first dielectricThe layer, the second etching stop layer and the second dielectric layer, wherein the groove is positioned above the through hole; forming AlN/Al on the upper surface and the side wall of the through hole/groove2O3Laminating the film without contacting the bottom of the through hole; forming a barrier layer and a copper film, wherein the barrier layer covers the AlN/Al2O3Laminating a film and covering the surface of the copper metal wire at the bottom of the through hole; the copper film completely fills the through hole/the groove; removing the Cu film, the barrier layer and the AlN/Al on the upper surface by adopting a chemical mechanical polishing method2O3Laminating the film; and forming a copper diffusion covering layer on the surface of the structure.
In the method for producing a copper interconnect structure of the present invention, it is preferable that AlN/Al is formed2O3The method for laminating the film comprises the following steps: immersing the through hole/groove structure into a n-octadecyl phosphate solution, and only forming a layer of n-octadecyl phosphate film on the surface of the copper metal wire at the bottom of the through hole in a self-assembly manner; depositing AlN/Al by using trimethylaluminum as Al precursor molecule and adopting an atomic layer deposition method2O3A laminated film, wherein AlN/Al is formed only on the upper surface and the side wall of the trench/via structure2O3Laminating the film; and removing the n-octadecyl phosphate film at the bottom of the through hole by adopting a wet etching method.
In the method for preparing the copper interconnection structure, the barrier layer is preferably at least one of Ru/TaN, Co/TiN, Co/WN, Co/ZrN and Ru/TiN.
In the method for manufacturing a copper interconnection structure of the present invention, preferably, the top layer of the lamination film of the barrier layer is Ru or Co, which is used as a seed layer and an adhesion layer.
In the method for manufacturing a copper interconnect structure of the present invention, preferably, the copper diffusion cap layer is at least one of SiCN, SiC, SiN, Co, CoWP, and CuSiN.
In the method for producing a copper interconnect structure of the present invention, preferably, the AlN/Al is2O3The thickness of the laminated film is 1 to 1.5 nm.
Drawings
FIG. 1 is a flow chart of a method of fabricating a copper interconnect structure.
Fig. 2 to 10 are schematic structural views of steps of a method for manufacturing a copper interconnect structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
The technical scheme of the invention is further explained by combining the attached figures 1-10 and the embodiment. Fig. 1 is a flowchart of a method for manufacturing a copper interconnect structure, and fig. 2 to 10 are schematic structural diagrams showing steps of the method for manufacturing a copper interconnect structure. As shown in fig. 1, the preparation method comprises the following specific steps:
step S1: providing a copper metal line 200 as an initial substrate, and then sequentially depositing a first etch stop layer 201, a first dielectric layer 202, a second etch stop layer 203, and a second dielectric layer 204 by using a chemical vapor deposition process, wherein the resulting structure is shown in fig. 2. Here, the first etch stop layer 201 and the second etch stop layer 203 may be selected from at least one of SiCN, SiN, SiC, SiON, and SiOC, and SiCN is selected in this embodiment. The first dielectric layer 202 and the second dielectric layer 204 may be SiO2SiCOH, or other low dielectric constant material, SiCOH being selected in this embodiment. Then, a via/trench structure is formed inside the stack layer formed by the etch stop layer and the dielectric layer by using a dual damascene process, and the resulting structure is shown in fig. 3. Wherein, the narrower structure at the lower part is a through hole, and the wider structure at the upper part is a groove.
Step S2: the above structure was immersed in a solution of n-octadecyl phosphate (ODPA). Since the phosphate group in ODPA is difficult to bond with silicon atoms, ODPA cannot self-assemble to form a film on the surface and inside the trench/via, and only the surface of the copper metal line at the bottom of the via will self-assemble to form an ODPA film 205, and the resulting structure is shown in fig. 4.
Then, depositing AlN/Al by using an atomic layer deposition method2O3The laminated film is prepared by growing AlN layer and Al layer2O3So that the growth is cyclically alternated until the desired thickness is obtained, and the last layer is grown of Al2O3That is, the uppermost layer of the laminated film is Al2O3. Wherein, AlN/Al2O3The thickness of the laminated film is 1 to 1.5 nm. Due to the growth of AlN/Al2O3The Al precursor molecule of the laminated film is trimethyl aluminum, and the trimethyl aluminum is difficult to adsorb on the surface of the ODPA film, so that AlN/Al is only on the surface of the groove/through hole and the dielectric layer inside the groove/through hole2O3The stacked film 206 is grown and the resulting structure is shown in fig. 5. Finally, removing by wet etching methodThe resulting structure is shown in fig. 6 for the ODPA film at the bottom of the via. Covering the surface of the low dielectric constant film with ultrathin AlN/Al2O3The laminated film can seal the porous structure of the low dielectric constant film, so that the barrier layer cannot permeate into the porous structure of the low dielectric constant film in the subsequent growth process of the barrier layer. And, Al2O3The film can prevent the diffusion of water vapor and oxygen, so that Al is coated on the surface of the low dielectric constant film2O3The film can enhance the water and oxygen permeation resistance of the low dielectric constant film. In addition, AlN has good thermal conductivity, contributing to the thermal conduction of the interconnect lines.
Step S3: by atomic layer deposition method on AlN/Al2O3The stack film 206 and the via bottom are grown with a Ru/TaN stack film as a barrier layer 207, and the resulting structure is shown in FIG. 7. Specifically, a layer of TaN is grown firstly, then a layer of Ru is grown, the TaN and the Ru are grown circularly and alternately until the required thickness is obtained, and the Ru is grown in the last layer, namely the uppermost layer of the laminated film is Ru, because the Ru can be used as a seed layer and an adhesion layer for copper electroplating; wherein the thickness range of the Ru/TaN laminated film is 1.5-2 nm. However, the present invention is not limited thereto, and the copper diffusion barrier layer may be selected from at least one of Ru/TaN, Co/TiN, Co/WN, Co/ZrN, and Ru/TiN. Finally, a copper film 208 is electroplated on the surface of the structure to serve as a higher copper interconnection line, and copper is filled in the trench/through hole, so that the structure is shown in fig. 8. In Al2O3The surface of the film adopts the atomic layer deposition process to grow the copper diffusion impervious layer, because of Al2O3The surface of the film is rich in hydroxyl active groups, and metal precursor molecules are easy to be on Al2O3The surface of the film is adsorbed, so that the probability of the occurrence of pinholes in the growth process of the barrier layer is greatly reduced.
Step S4: removing the surface metal Cu film 208, the barrier layer 207 and the AlN/Al by adopting a chemical mechanical polishing method2O3The film 206 is laminated, and the resulting structure is shown in fig. 9.
Step S5: a SiN film is grown on the surface of the interconnection structure by physical vapor deposition to form a copper diffusion cap 209, and the resulting structure is shown in fig. 10. However, the present invention is not limited thereto, and the copper diffusion coating may be at least one selected from SiCN, SiC, SiN, Co, CoWP, and CuSiN, and the growth process may be chemical vapor deposition, pulsed laser deposition, and atomic layer deposition.
As shown in fig. 10, a copper interconnect structure includes: the device comprises a copper metal wire 200, a first etching stop layer 201, a first dielectric layer 202, a second etching stop layer 203 and a second dielectric layer 204 from bottom to top in sequence; a through hole/trench structure vertically connected to each other and penetrating through the first etching stop layer 201, the first dielectric layer 202, the second etching stop layer 203 and the second dielectric layer 204, wherein the trench is located above the through hole; AlN/Al2O3A laminated film 206, a barrier layer 207 and a copper film 208, wherein AlN/Al2O3The laminated film 206 is formed on the side walls of the via hole and the trench, and does not contact the bottom of the via hole; barrier layer 207 covers AlN/Al2O3Laminating a film 206 and covering the surface of the copper metal line 200 at the bottom of the through hole; the copper film 208 completely fills the via/trench interior; and a copper diffusion capping layer 209 covering the upper surface of the copper interconnect structure.
Preferably, barrier layer 207 is at least one of Ru/TaN, Co/TiN, Co/WN, Co/ZrN, Ru/TiN. The top layer of the stack film of barrier layer 207 is Ru or Co, which serves as a seed layer and an adhesion layer. The copper diffusion cap layer 209 is at least one of SiCN, SiC, SiN, Co, CoWP, and CuSiN.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A copper interconnect structure characterized in that,
the method comprises the following steps:
the device comprises a copper metal wire (200), a first etching stop layer (201), a first dielectric layer (202), a second etching stop layer (203) and a second dielectric layer (204) from bottom to top in sequence;
a via/trench structure vertically communicating with each other and penetrating through the first etch stop layer (201), the first dielectric layer (202), the second etch stop layer (203), and the second dielectric layer (204), wherein the trench is located above the via;
AlN/Al2O3a laminated film (206), a barrier layer (207) and a copper film (208), wherein the AlN/Al2O3A laminated film (206) is formed on the side walls of the via hole and the trench, and is not in contact with the bottom of the via hole; the barrier layer (207) covers the AlN/Al2O3Laminating a film (206) and covering the surface of the copper metal line (200) at the bottom of the through hole; the copper film (208) completely fills the inside of the via/trench;
a copper diffusion capping layer (209) covers an upper surface of the copper interconnect structure.
2. The copper interconnect structure of claim 1,
the barrier layer (207) is at least one of Ru/TaN, Co/TiN, Co/WN, Co/ZrN, Ru/TiN.
3. The copper interconnect structure of claim 2,
the top layer of the laminated film of the barrier layer (207) is Ru or Co and is used as a seed layer and an adhesion layer.
4. The copper interconnect structure of claim 1,
the copper diffusion coating (209) is at least one of SiCN, SiC, SiN, Co, CoWP, and CuSiN.
5. A method for preparing a copper interconnection structure is characterized in that,
the method comprises the following steps:
sequentially forming a first etching stop layer (201), a first dielectric layer (202), a second etching stop layer (203) and a second dielectric layer (204) by taking a first copper metal wire (200) as an initial substrate;
forming a through hole/trench structure which is vertically communicated with the first etching stop layer (201), the first dielectric layer (202), the second etching stop layer (203) and the second dielectric layer (204), wherein the trench is positioned above the through hole;
forming AlN/Al on the upper surface and the side wall of the through hole/groove structure2O3A laminated film (206) not in contact with the bottom of the via hole;
forming a barrier layer (207) and a copper film (208), wherein the barrier layer (207) covers the AlN/Al2O3Laminating a film (206) and covering the surface of the copper metal line (200) at the bottom of the through hole; the copper film (208) completely fills the inside of the via/trench;
removing the Cu film (208), the barrier layer (207) and the AlN/Al on the upper surface by adopting a chemical mechanical polishing method2O3A laminated film (206);
a copper diffusion coating (209) is formed on the surface of the structure.
6. The method of claim 5, wherein the copper interconnect structure is formed by a chemical vapor deposition process,
form AlN/Al2O3The method for laminating the film comprises the following steps:
immersing the through hole/groove structure into a n-octadecyl phosphate solution, and only forming a layer of n-octadecyl phosphate film (205) on the surface of the copper metal wire (200) at the bottom of the through hole in a self-assembly manner;
depositing AlN/Al by using trimethylaluminum as Al precursor molecule and adopting an atomic layer deposition method2O3A laminated film (206) forming AlN/Al only on the upper surface and the sidewall of the trench/via structure2O3A laminated film (206);
and removing the n-octadecyl phosphate film (205) at the bottom of the through hole by adopting a wet etching method.
7. The method of claim 5, wherein the copper interconnect structure is formed by a chemical vapor deposition process,
the barrier layer (207) is at least one of Ru/TaN, Co/TiN, Co/WN, Co/ZrN, Ru/TiN.
8. The method of claim 7, wherein the copper interconnect structure is formed by a chemical vapor deposition process,
the top layer of the laminated film of the barrier layer (207) is Ru or Co and is used as a seed layer and an adhesion layer.
9. The copper interconnect structure of claim 5,
the copper diffusion coating (209) is at least one of SiCN, SiC, SiN, Co, CoWP, and CuSiN.
10. The method of claim 5, wherein the copper interconnect structure is formed by a chemical vapor deposition process,
the AlN/Al2O3The thickness of the laminated film is 1 to 1.5 nm.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509267B1 (en) * | 2001-06-20 | 2003-01-21 | Advanced Micro Devices, Inc. | Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer |
| US20050184397A1 (en) * | 2004-02-19 | 2005-08-25 | International Business Machines Corporation | Structures and methods for intergration of ultralow-k dielectrics with improved reliability |
| CN101427361A (en) * | 2006-02-28 | 2009-05-06 | St微电子(克偌林斯2)股份有限公司 | Metal interconnects in a dielectric material |
| CN103053228A (en) * | 2010-08-02 | 2013-04-17 | 安美特德国有限公司 | Method to form solder deposits and non-melting bump structures on substrates |
| CN106206408A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN107743653A (en) * | 2015-06-18 | 2018-02-27 | 英特尔公司 | Bottom-up filling for the metallicity of semiconductor structure（BUF） |
| CN111106091A (en) * | 2018-10-25 | 2020-05-05 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
-
2020
- 2020-07-29 CN CN202010747376.4A patent/CN112018079B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509267B1 (en) * | 2001-06-20 | 2003-01-21 | Advanced Micro Devices, Inc. | Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer |
| US20050184397A1 (en) * | 2004-02-19 | 2005-08-25 | International Business Machines Corporation | Structures and methods for intergration of ultralow-k dielectrics with improved reliability |
| CN101427361A (en) * | 2006-02-28 | 2009-05-06 | St微电子(克偌林斯2)股份有限公司 | Metal interconnects in a dielectric material |
| CN103053228A (en) * | 2010-08-02 | 2013-04-17 | 安美特德国有限公司 | Method to form solder deposits and non-melting bump structures on substrates |
| CN106206408A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN107743653A (en) * | 2015-06-18 | 2018-02-27 | 英特尔公司 | Bottom-up filling for the metallicity of semiconductor structure（BUF） |
| CN111106091A (en) * | 2018-10-25 | 2020-05-05 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
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