CN103545292A - TSV structure and manufacturing method thereof - Google Patents
TSV structure and manufacturing method thereof Download PDFInfo
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- CN103545292A CN103545292A CN201310556225.0A CN201310556225A CN103545292A CN 103545292 A CN103545292 A CN 103545292A CN 201310556225 A CN201310556225 A CN 201310556225A CN 103545292 A CN103545292 A CN 103545292A
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Abstract
The invention provides a TSV structure. The TSV structure ensures the TSV reliability and insulation integrity, simplifies technological processes, and reduces manufacturing cost. The TSV structure comprises a TSV hole formed in a silicon substrate. The TSV structure is characterized in that an insulating layer, a plurality of diffusion impervious layers, a seed layer and an electric conduction metal layer are arranged in the TSV hole in sequence. The invention further provides a manufacturing method of the TSV structure.
Description
Technical field
The present invention relates to microelectronic industry substrate package technical field, be specifically related to a kind of silicon through hole (TSV) structure and manufacture method thereof of wearing.
Background technology
Development along with integrated circuit technology, except the performance requirement of high speed that device itself is proposed, low-power consumption, high reliability, the development of interconnection technique has also affected the overall performance of device to an increasingly great extent, reducing RC, (wherein R is the resistance of interconnecting metal time of delay, C is the electric capacity relevant with medium), reach that to postpone suitable level with device be a very large challenge.Silicon through hole (TSV) technology can effectively reduce RC time delay.TSV technology is that the core .TSV insulation integrity of advanced three-dimensional systematic encapsulation (3D SIP) integrated technology and even three dimensional integrated circuits (3D IC) integrated technology is the key factor that determines its electrical property and long-term reliability.
Copper has higher diffusion rate in silicon or medium, for example, 300 ℃ to 700 ℃ temperature ranges, copper diffusion rate in Si is 4.7*10-3exp(-0.43kT) cm2/s, once copper atom enters silicon device, just can become deep energy level acceptor impurity, thereby produce complex centre, carrier lifetime is reduced, finally cause device performance degeneration even to lose efficacy.In addition the adhesion property of copper and medium a little less than, be also vulnerable to corrosion.
In TSV manufacture craft, the existence of dielectric film (as SiO2) can prevent that the electric conducting material (as copper) of rear formation from diffusing into substrate, prevents from forming conductive channel between interconnection material copper and silicon base; Because thereby Cu is easy to be diffused into the dielectric property serious degradation that makes medium in medium, for fear of the alloying in copper interconnection circuit, stop and fill metal (such as copper) to insulating barrier diffusion, thereby between Cu and Si, must add a diffusion impervious layer to improve the electricity reliability and stability of chip.Diffusion impervious layer should possess following key property:
1) characteristic of good stability and copper diffusion barrier;
2) low resistivity.Because diffusion impervious layer is enclosed in around the copper conductor of every layer, the resistance of diffusion impervious layer is also a part for interconnect resistance.Resistivity is low can be so that the resistance of whole interconnection line be less;
3) ultra-thin and free of pinholes crack, identical with reason above, lower thereby thin diffusion impervious layer can make copper that resistivity is lower occupy the total interconnection resistance in more space;
4) depositing temperature of whole technique is less than 400 ℃;
5) and low k dielectric, copper, etching stop layer etc. have good adhesiveness, but can not with any chemical reaction of its generation.
In most cases dielectric film adopts SiO2 layer, and the formation of SiO2 generally adopts PECVD technology.Diffusion impervious layer is generally selected Ti, Ta and their materials such as nitride, and the manufacture method of main flow is the mode that adopts sputter, at present the main modes such as physical vapor deposition (PVD) that adopt.
When TSV adopts single insulating layer, at the follow-up back side, appear in technical process, requirement due to etching depth requirement and etch rate, often etching solution can adopt hydrofluoric acid+nitric acid system, but this solution system also can etching silicon dioxide insulating barrier, and the etching selection of silicon and silicon dioxide is less, after once silicon dioxide insulating layer etching is complete, the diffusion impervious layer such as Ti or TiN will be exposed in etching solution, this etching liquid is higher to the speed of Ti, the result causing or be: 1) cause etching (in individual layer diffuse layer structure to filling metal, after Ti diffusion impervious layer etching is complete, etching liquid can react with filling metal immediately), 2) there is serious Undercutting Phenomenon in diffusion impervious layer, 3) complexity of technological process and the raising of cost (because the above results can consider to use other etching liquids or dry etching, the etch rate of other wet etching liquid is slower, and dry etching is higher for the etching cost of the larger degree of depth).
When diffusion impervious layer adopts as Ti or Ti/TiN structure, in TSV manufacturing process, single barrier layer and silicon and Cu conductive layer adhesion are not same good, thereby employing double-decker, but double-decker also exists a problem, that is exactly that TiN membrane stress is larger, and Ti/TiN structure may cause larger stress, this double-deck resistance is also larger simultaneously, and reliability and electrical property are reduced.
Summary of the invention
For the problems referred to above, the invention provides a kind of silicon through hole (TSV) structure and manufacture method thereof of wearing, when guaranteeing TSV reliability and insulation integrity, simplified technological process, reduced manufacturing cost.
Its technical scheme is such: a kind of silicon through hole (TSV) structure of wearing, and it comprises TSV hole, described TSV hole is arranged on silicon substrate, it is characterized in that: in described TSV hole, be disposed with insulating barrier, multilayer diffusion impervious layer, Seed Layer and conductive metal layer.
It is further characterized in that: described diffusion impervious layer comprises multilayer diffusion impervious layer.
A manufacture method of wearing silicon through hole (TSV) structure, is characterized in that: it comprises the following steps:
(1), on silicon substrate, deposit TSV hole;
(2), at the long-pending insulating barrier of TSV inner hole deposition;
(3), deposit multilayer diffusion impervious layer on insulating barrier;
(4), on diffusion impervious layer, deposit Seed Layer;
(5), filled conductive metal in Seed Layer;
It is further characterized in that,
On silicon substrate, etching TSV hole lower bulk silicon, exposes TSV hole head;
In step (1), adopt dry etching TSV hole;
In step (3), deposit multilayer diffusion impervious layer, deposits ground floor diffusion impervious layer Ti or Ta successively, the second barrier layer TiN or TaN and the 3rd barrier layer Ti or Ta;
Further, etching TSV hole lower bulk silicon on silicon substrate: adopt three stage etching TSV hole lower bulk silicon, first stage adopts the solution of HF:HNO3=3:1-1:2 v% volume ratio, second stage adopts the solution of HF:HNO3=1:3-1:9 v% volume ratio, and the phase III adopts the solution of HF:HNO3=1:10-1:50v % volume ratio;
Further, etching TSV hole lower bulk silicon on silicon substrate: adopt two stage etching TSV hole lower bulk silicon, the first stage adopts the solution of HF:HNO3=3:1-1:9v% volume ratio, and second stage adopts the solution of HF:HNO3=1:10-1:50v% volume ratio.
Further, etching TSV hole lower bulk silicon on silicon substrate: the solution etching TSV hole lower bulk silicon that directly adopts HF:HNO3=3:1-1:50 v% volume ratio.
Above-mentioned wearing in silicon through hole (TSV) structure of the present invention, owing to being provided with multilayer diffusion impervious layer in TSV hole, at etching TSV hole lower bulk silicon, expose in the head process of TSV hole, effectively prevented the etching of conducting metal, in the time of reliability and insulation integrity, simplify technological process, reduced manufacturing cost.
Accompanying drawing explanation
Fig. 1 is TSV pore structure schematic diagram of the present invention;
Fig. 2 is TSV pore structure bottom etching schematic diagram.
Embodiment
See Fig. 1, a kind of silicon through hole (TSV) structure of wearing, it comprises TSV hole 201, TSV hole 201 is arranged on silicon substrate 101, in TSV hole 201, be disposed with insulating barrier 301, ground floor diffusion impervious layer 401, second layer diffusion impervious layer 501, the 3rd layer of diffusion impervious layer 601, Seed Layer (not shown in FIG.) and conductive metal layer (not shown in FIG.).
A manufacture method of wearing silicon through hole (TSV) structure, is characterized in that: it comprises the following steps:
(1), on silicon substrate etching TSV hole 201: dry etching TSV hole 201 first, etching certain depth, making it is T21 apart from substrate bottom thickness;
(2), the interior depositing insulating layer 301 in TSV hole 201: such as utilizing PECVD deposition TEOS, insulating barrier can be one deck, can be also multilayer (only having drawn one deck in figure);
(3), on insulating barrier 301, depositing successively ground floor diffusion impervious layer 401(can be Ti, Ta), second layer diffusion impervious layer 501(can be TiN, TaN) the and three layer of diffusion impervious layer 601(can be Ti, Ta), the deposition process of diffusion impervious layer has CVD, PVD, sputter, technique for atomic layer deposition (ALD) etc.;
(4), on the 3rd layer of diffusion impervious layer 601, deposit Seed Layer: for the interior filled conductive metal in TSV hole 201, also need on diffusion impervious layer 601, first deposit one deck Seed Layer (not shown in FIG.), deposition process has PVD, ALD etc.;
(5), filled conductive metal (not shown in FIG.) in Seed Layer: final by method filled conductive metals such as plating, conductive fill metal is generally copper, can be also the other materials such as tungsten, polysilicon.
After above-mentioned steps completes, just can utilize wet etching to substitute that the technological processes such as traditional attenuate, CMP complete attenuate and polishing step carrys out etching TSV hole lower bulk silicon,, expose TSV head simultaneously.
In figure: 202 is TSV head, 301 is insulating barrier, and 401 is ground floor diffusion impervious layer, and 501 is second layer diffusion impervious layer, and 601 is the 3rd layer of diffusion impervious layer, and T11 is initial substrates thickness, and T21 is that TSV head is apart from the thickness of substrate bottom; T22 be after etching body silicon certain depth TSV head apart from the distance of substrate bottom.
Embodiment mono-,
See Fig. 2, etching TSV hole lower bulk silicon: etching liquid adopts hydrofluoric acid/nitric acid system (comprising with dilutions such as deionized water or acetic acid).In order better to realize said process, in corrosion process, can select according to different phase the HF/HNO3 mixed solution of different volumes ratio, such as the first stage, need a large amount of body silicon of etching, can adopt the preferred 2:1 v% of HF:HNO3=3:1-1:2 v%() solution of volume ratio, the speed of its etching body silicon is larger; Etching body silicon is to certain depth, when TSV head is apart from substrate bottom certain distance (such as 2-5 μ m), enters second stage and carries out polishing, can adopt the preferred 1:3 v% of HF:HNO3=1:3-1:9 v%() solution of volume ratio, this solution has polishing action; Then in order to expose TSV head, the body silicon that also needs etching certain depth (determining according to demand), in order to guarantee the coplanarity of substrate and to reduce subsequent etching, introduce larger difference in height (TTV), can use the preferred 1:25v % of HF:HNO3=1:10-1:50v%() solution of volume ratio.In traditional TSV structure, this etching solution is inapplicable, reason is HF/HNO3 mixed solution etch silicon and silicon dioxide simultaneously, once silicon dioxide etching is complete, diffusion impervious layer will be exposed in etching solution, the diffusion impervious layer that this etching solution etching is traditional (Ti), even etching conductive packed layer, has seriously reduced reliability.And the structure that the present invention introduces, even if silicon dioxide layer is etched, solution corrosion falls, but therefore this etching solution etch silicon nitride layer not substantially plays a very good protection to the diffusion impervious layer in TSV hole and conductive fill layer.
Embodiment bis-,
See Fig. 2, etching TSV hole lower bulk silicon: etching liquid adopts hydrofluoric acid/nitric acid system (comprising with dilutions such as deionized water or acetic acid).In order better to realize said process, in corrosion process, can select according to different phase the HF/HNO3 mixed solution of different volumes ratio, such as the first stage, need a large amount of body silicon of etching, the solution that can adopt HF:HNO3=3:1-1:9 v% (preferably 2:1v%) volume ratio, the speed of its etching body silicon is larger; Etching body silicon is to certain depth, when TSV head is apart from substrate bottom certain distance (such as 2-5 μ m), enter second stage and carry out etching, object is in order to expose TSV head, so also need the body silicon of etching certain depth (determining according to demand), in order to guarantee the coplanarity of substrate and to reduce subsequent etching, introduce larger difference in height (TTV), can use the preferred 1:25v% of HF:HNO3=1:10-1:50v%() solution of volume ratio.In traditional TSV structure, this etching solution is inapplicable, reason is HF/HNO3 mixed solution etch silicon and silicon dioxide simultaneously, once silicon dioxide etching is complete, diffusion impervious layer will be exposed in etching solution, the diffusion impervious layer (Ti) that this etching solution is traditional to etching, even etching conductive packed layer, has seriously reduced reliability.And the structure that the present invention introduces, even if silicon dioxide layer is etched, solution corrosion falls, but therefore this etching solution etch silicon nitride layer not substantially plays a very good protection to the diffusion impervious layer in TSV hole and conductive fill layer.
Embodiment tri-,
See Fig. 2, etching TSV hole lower bulk silicon: etching liquid adopts hydrofluoric acid/nitric acid system (comprising with dilutions such as deionized water or acetic acid).Etchant solution can adopt the preferred 1:10v% of HF:HNO3=3:1-1:50 v%() solution of volume ratio, etching body silicon is until expose TSV head.In traditional TSV structure, this etching solution is inapplicable, reason is HF/HNO3 mixed solution etch silicon and silicon dioxide simultaneously, once silicon dioxide etching is complete, diffusion impervious layer will be exposed in etching solution, the diffusion impervious layer (Ti) that this etching solution is traditional to etching, even etching conductive packed layer, has seriously reduced reliability.And the structure that the present invention introduces, even if silicon dioxide layer is etched, solution corrosion falls, but therefore this etching solution etch silicon nitride layer not substantially plays a very good protection to the diffusion impervious layer in TSV hole and conductive fill layer.
A kind ofly in the present invention wear silicon through hole (TSV) structure and manufacture method advantage is:
Can adopt hydrofluoric acid+nitric acid system etched substrate body silicon, save attenuate and the CMP equipment in conventional process flow, this etching system has the function of collection attenuate, polishing and one, simplification of flowsheet.
1) insulating barrier adopts at least 2 layers of structure, such as silica/silicon nitride.The benefit of this structure is:
2) diffusion impervious layer adopts 3-tier architecture, and such as Ti/TiN/Ti structure, the benefit of this structure is:
the interface of three-decker is more level and smooth, thereby reduces the rising of the Cu interconnection line effective resistivity that causes because of interface scattering.
Claims (10)
1. wear silicon through hole (TSV) structure, it comprises TSV hole, and described TSV hole is arranged on silicon substrate, it is characterized in that: in described TSV hole, be disposed with insulating barrier, multilayer diffusion impervious layer, Seed Layer and conductive metal layer.
2. a kind of silicon through hole (TSV) structure of wearing according to claim 1, is characterized in that: described insulating barrier comprises multilayer dielectric layer.
3. a kind of silicon through hole (TSV) structure of wearing according to claim 1, is characterized in that: described diffusion impervious layer is Ti/TiN/Ti structure.
4. a kind of silicon through hole (TSV) structure of wearing according to claim 2, is characterized in that: described insulating barrier is silica/silicon nitride structure.
5. a kind of manufacture method of wearing silicon through hole (TSV) structure according to claim 1, is characterized in that: it comprises the following steps:
(1), etching TSV hole on silicon substrate;
(2), at the long-pending insulating barrier of TSV inner hole deposition;
(3), deposit multilayer diffusion impervious layer on insulating barrier;
(4), on diffusion impervious layer, deposit Seed Layer;
(5), filled conductive metal in Seed Layer.
6. a kind of manufacture method of wearing silicon through hole (TSV) structure according to claim 5, is characterized in that: etching TSV hole lower bulk silicon on silicon substrate, exposes TSV hole head.
7. a kind of manufacture method of wearing silicon through hole (TSV) structure according to claim 5, it is characterized in that: in step (3), deposit three layers of diffusion impervious layer, depositing successively ground floor diffusion impervious layer is Ti or Ta, and second layer diffusion impervious layer is that TiN or TaN and the 3rd layer of diffusion impervious layer are Ti or Ta.
8. a kind of manufacture method of wearing silicon through hole (TSV) structure according to claim 5, it is characterized in that: etching TSV hole lower bulk silicon on silicon substrate: adopt three stage etching TSV hole lower bulk silicon, first stage adopts the solution of HF:HNO3=3:1-1:2v% volume ratio, second stage adopts the solution of HF:HNO3=1:3-1:9 v% volume ratio, and the phase III adopts the solution of HF:HNO3=1:10-1:50v % volume ratio.
9. a kind of manufacture method of wearing silicon through hole (TSV) structure according to claim 5, it is characterized in that: etching TSV hole lower bulk silicon on silicon substrate: adopt two stage etching TSV hole lower bulk silicon, first stage adopts the solution of HF:HNO3=3:1-1:9v% volume ratio, and second stage adopts the solution of HF:HNO3=1:10-1:50v% volume ratio.
10. a kind of manufacture method of wearing silicon through hole (TSV) structure according to claim 5, is characterized in that: etching TSV hole lower bulk silicon on silicon substrate: the solution etching TSV hole lower bulk silicon that directly adopts HF:HNO3=3:1-1:50 v% volume ratio.
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| CN105006467A (en) * | 2014-04-25 | 2015-10-28 | 台湾积体电路制造股份有限公司 | Metal contact structure and method of forming the same |
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