CN112018076A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

Info

Publication number
CN112018076A
CN112018076A CN202010737827.6A CN202010737827A CN112018076A CN 112018076 A CN112018076 A CN 112018076A CN 202010737827 A CN202010737827 A CN 202010737827A CN 112018076 A CN112018076 A CN 112018076A
Authority
CN
China
Prior art keywords
contact hole
silicon layer
active region
epitaxial growth
selective epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010737827.6A
Other languages
Chinese (zh)
Inventor
安重镒
金成基
白国斌
崔恒玮
王桂磊
高建峰
田光辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Original Assignee
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS, Zhenxin Beijing Semiconductor Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN202010737827.6A priority Critical patent/CN112018076A/en
Publication of CN112018076A publication Critical patent/CN112018076A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Geometry (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. A semiconductor structure includes a semiconductor substrate; an active region on the semiconductor substrate; at least one contact hole connected with the active region, the contact hole including a groove at the active region; the groove is filled with a selective epitaxial growth silicon layer; and filling a polycrystalline silicon layer connected with the selective epitaxial growth silicon layer in the contact hole. According to the invention, selective epitaxial growth silicon is filled at the bottom of the groove in which the cavity is easy to form, so that the purpose of eliminating the hole by 100% is realized.

Description

Semiconductor structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor preparation, in particular to a semiconductor structure and a preparation method thereof.
Background
DRAM bit line contacts need to maximize the contact area to ensure the contact resistance characteristics with the active elements. Therefore, it is composed of a sphere-like shape or a bowl shape, that is, at least one contact hole connected with the active region is formed on the semiconductor substrate, the contact hole forms a bowl shape at the active region, the structure is shown in fig. 1, after the bowl-shaped groove is filled with deposited polysilicon, the appearance is shown in fig. 2, and a bottom hole is generated due to the bowl-shaped contact. It does not matter if the hole is located at the center, but if eccentricity occurs on the active area surface, resistance failure may occur, and thus the hole must be removed. In the prior art, a DED (depth-etch-depth) technology is adopted to eliminate holes, but the method cannot eliminate the holes 100% and still has partial holes 101, as shown in FIG. 3, so that the industrial mass production is difficult to realize.
Disclosure of Invention
The invention aims to provide a semiconductor structure, which fills selective epitaxial growth silicon at the bottom of a groove where a cavity is easy to form, thereby realizing the aim of eliminating the cavity by 100 percent.
In order to achieve the above purpose, the invention provides the following technical scheme:
a semiconductor structure includes a semiconductor substrate;
an active region on the semiconductor substrate;
at least one contact hole connected with the active region, the contact hole including a groove at the active region;
the groove is filled with a selective epitaxial growth silicon layer; and filling a polycrystalline silicon layer connected with the selective epitaxial growth silicon layer in the contact hole.
In the prior art, polysilicon is generally used when filling the trench shape, such as a bit line contact, so that the void cannot be eliminated 100% even if a depo-etch-depo process is used. Therefore, the invention replaces partial polycrystalline silicon with a selective epitaxial growth silicon layer, the selective epitaxial growth silicon layer is positioned at the bottom of the groove which is easy to form defects such as holes, gaps and the like, and then the polycrystalline silicon is deposited on the selective epitaxial growth silicon layer, and the selective epitaxial growth silicon layer can not form the defects such as holes, gaps and the like, so the aim of eliminating the holes by 100 percent can be realized by adopting the structure.
The invention also provides a preparation method of the semiconductor structure, which comprises the following steps:
providing a semiconductor substrate with an active region;
forming at least one contact hole connected with the active region, the contact hole being formed as a groove structure at the active region;
selectively epitaxially growing a silicon layer in the groove;
and depositing polycrystalline silicon on the selective epitaxial growth silicon layer.
The semiconductor structure and the preparation method can be applied to various semiconductor devices including but not limited to DRAM, 2D NAND, 3D NAND or LCD.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
FIG. 1 is a structure of a contact hole connected to an active region in a conventional semiconductor structure;
FIG. 2 is the structure of FIG. 1 after filling the grooves with polysilicon;
FIG. 3 is a topography of the structure of FIG. 2 after being processed by a DED technique;
FIG. 4 is a graph of the morphology resulting from the deposition of polysilicon in accordance with the present invention;
fig. 5 is the structure of fig. 3 after the recess is filled with SEG silicon;
FIG. 6 is the structure after depositing polysilicon on the SEG silicon surface of FIG. 5;
fig. 7 is a resistance curve of a semiconductor structure obtained by the present invention and the DED technique, respectively.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Examples
In many semiconductor devices, it is often necessary to fill polysilicon in a trench with a high aspect ratio, such as a contact part (e.g. a bit line contact) commonly found in a capacitor, and as the devices are miniaturized, the aspect ratio is increased, which causes defects such as holes during polysilicon filling. To this end, the present invention proposes the following method.
Taking the bit line contact of DRAM as an example, as shown in fig. 4, the recess is bowl-shaped, and when depositing polysilicon in the structure, selectively epitaxially growing a silicon layer (SEG) in the plurality of bowl-shaped recesses in advance, that is, filling part of SEG silicon, to form the structure shown in fig. 5; polysilicon is then deposited over the SEG silicon layer to form the structure shown in fig. 6. In the process, because the SEG can not form defects such as holes and gaps, the problem of cavities when the polycrystalline silicon is deposited at the bottom of the groove is solved.
Comparing the inventive technique (partial SEG, partially selective epitaxial growth) described above with the DED technique (i.e., conventional technique), the results of fig. 7 show that: the resistance of the invention is lower with the same filling height of the contact hole.
The contact portion may be formed by a typical process, such as: various functional films are formed on a semiconductor substrate (e.g., a wafer) and then etched to form desired trenches.
Selective epitaxial growth of silicon refers to a technique of growing a single crystal layer on a substrate in the crystal orientation of the substrate, and growing in a specific region while not growing in other regions. It may be applied by vapor, liquid or solid phase epitaxy. Taking vapor phase epitaxy as an example, a silicon source with strong volatility reacts with hydrogen gas or is pyrolyzed at high temperature to generate silicon atoms, the silicon atoms are deposited on a substrate to grow an epitaxial layer, and a commonly used silicon source is SiCl4、SiH2Cl2、SiHCl3、SiH4And the like.
The dry cleaning may employ a typical inert gas purge, or a plasma cleaning technique.
Fig. 4 to 6 only illustrate one shape of the contact portion with a high aspect ratio, but the application of the present invention is not limited thereto, and the present invention further includes a recess with a convex shape, etc. to solve the defect of void, etc. caused by filling polysilicon in the recess with an arbitrary shape with a high aspect ratio.
In the above method, in order to improve the quality of the device, dry cleaning is preferably performed after SEG and before depositing polysilicon to remove contaminants such as impurities generated by previous etching.
The SEG mode mainly comprises: silicon growth-etch-silicon growth-etch, to and fro, the source of gaseous silicon employed is arbitrary, including but not limited to: SiH2Cl2、SiCl4Etc., the etchants employed include, but are not limited to: HCl, HBr, etc.
The above process can be carried out in a typical apparatus such as a cluster apparatus, a furnace-type apparatus or a rotary-type apparatus (Merry-go-round).
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A semiconductor structure, comprising:
a semiconductor substrate;
an active region on the semiconductor substrate;
at least one contact hole connected with the active region, the contact hole including a groove at the active region;
the groove is filled with a selective epitaxial growth silicon layer; and filling a polycrystalline silicon layer connected with the selective epitaxial growth silicon layer in the contact hole.
2. The semiconductor structure of claim 1, wherein the contact hole is a bit line contact hole.
3. The semiconductor structure of claim 1 or 2, wherein the recess is bowl-shaped.
4. A semiconductor device comprising the semiconductor structure of any one of claims 1-3.
5. The semiconductor device according to claim 4, which is a DRAM, a 2D NAND, a 3D NAND, or an LCD.
6. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate with an active region;
forming at least one contact hole connected with the active region, the contact hole being formed as a groove structure at the active region;
selectively epitaxially growing a silicon layer in the groove;
and depositing polycrystalline silicon on the selective epitaxial growth silicon layer.
7. The method of claim 6, comprising, after said selectively epitaxially growing a silicon layer and before said depositing polysilicon: and cleaning the selective epitaxial growth silicon layer by a dry method.
8. The method according to claim 6 or 7, wherein the selective epitaxial growth of the silicon layer and the deposition of the polycrystalline silicon are carried out using: cluster type equipment, furnace type equipment or rotary type equipment (Merry-go-round).
9. The method of claim 6, wherein the contact hole is a bit line contact hole.
10. The method of claim 6, wherein the method of selectively epitaxially growing a silicon layer comprises: silicon growth and etching are carried out repeatedly, and SiH is used as a gas silicon source2Cl2The etchant is HCl.
CN202010737827.6A 2020-07-28 2020-07-28 Semiconductor structure and preparation method thereof Pending CN112018076A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010737827.6A CN112018076A (en) 2020-07-28 2020-07-28 Semiconductor structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010737827.6A CN112018076A (en) 2020-07-28 2020-07-28 Semiconductor structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN112018076A true CN112018076A (en) 2020-12-01

Family

ID=73498867

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010737827.6A Pending CN112018076A (en) 2020-07-28 2020-07-28 Semiconductor structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN112018076A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101317253A (en) * 2005-11-28 2008-12-03 Nxp股份有限公司 Method of fabricating self aligned schottky junctions for semiconductors devices
CN101866833A (en) * 2009-04-16 2010-10-20 上海华虹Nec电子有限公司 Silicon epitaxy method for filling groove
CN101989552A (en) * 2009-08-07 2011-03-23 上海华虹Nec电子有限公司 Method for manufacturing lengthwise region of CoolMOS
CN108231738A (en) * 2017-12-29 2018-06-29 睿力集成电路有限公司 Semiconductor device structure and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101317253A (en) * 2005-11-28 2008-12-03 Nxp股份有限公司 Method of fabricating self aligned schottky junctions for semiconductors devices
CN101866833A (en) * 2009-04-16 2010-10-20 上海华虹Nec电子有限公司 Silicon epitaxy method for filling groove
CN101989552A (en) * 2009-08-07 2011-03-23 上海华虹Nec电子有限公司 Method for manufacturing lengthwise region of CoolMOS
CN108231738A (en) * 2017-12-29 2018-06-29 睿力集成电路有限公司 Semiconductor device structure and its manufacturing method

Similar Documents

Publication Publication Date Title
KR100327596B1 (en) Method for fabricating contact plug of semiconductor device using Selective Epitaxial Growth of silicon process
JP2021082817A (en) Method for providing semiconductor device with silicon filled gaps
TWI420573B (en) Method of forming integrated circuit structure
JP6207170B2 (en) Mask structure and method for defect-free heteroepitaxial
TWI660507B (en) Semiconductor device and method for manufacturing the same
JP2017532779A (en) Self-aligned alternative fin formation
US7413967B2 (en) Yield improvement in silicon-germanium epitaxial growth
KR100406580B1 (en) Method for forming contact plug of semiconductor device
US6818537B2 (en) Method of manufacturing a contact plug for a semiconductor device
JP5556851B2 (en) Manufacturing method of semiconductor device
CN112018076A (en) Semiconductor structure and preparation method thereof
US20030068885A1 (en) Method of forming a contact plug for a semiconductor device
KR100335124B1 (en) Method for forming epitaxial layer of semiconductor device
KR20190098715A (en) Methods for bottom up fin structure formation
CN104217957A (en) Transistor and formation method thereof
KR100364813B1 (en) Method for Forming Epitaxial Layer of Semiconductor Device
KR102135769B1 (en) Methods for etch mask and fin structure formation
JPH10284588A (en) Manufacture of semiconductor device
KR100524802B1 (en) Semiconductor device having contact plug formed using double selective epitaxial growth and method for fabrication of the same
CN117198982A (en) Groove type epitaxial structure and preparation method thereof
JP2013105770A (en) Semiconductor device manufacturing method
KR20020049349A (en) Method for growing an epi-silicon layer
KR100832022B1 (en) Method for fabricating contact plug in semiconductor device
CN116825798A (en) CIS manufacturing method
KR100357199B1 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20201201

RJ01 Rejection of invention patent application after publication